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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5 Date: Fri, 28 Feb 2020 16:38:12 +0000 Message-Id: <20200228163840.23585-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sai Pavan Boddu All A9 CPUs have a GIC with 5 bits of priority. Signed-off-by: Sai Pavan Boddu Reviewed-by: Peter Maydell Message-id: 1582537164-764-3-git-send-email-sai.pavan.boddu@xilinx.com Suggested-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/cpu/a9mpcore.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 1f8bc8a196f..b4f6a7e8a54 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -16,6 +16,8 @@ #include "hw/qdev-properties.h" #include "hw/core/cpu.h" +#define A9_GIC_NUM_PRIORITY_BITS 5 + static void a9mp_priv_set_irq(void *opaque, int irq, int level) { A9MPPrivState *s = (A9MPPrivState *)opaque; @@ -68,6 +70,8 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + A9_GIC_NUM_PRIORITY_BITS); /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do.