| Message ID | 20200211173726.22541-2-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm: Implement ARMv8.1-PMU and ARMv8.4-PMU | expand |
On 2/11/20 9:37 AM, Peter Maydell wrote: > Enforce a convention that an isar_feature function that tests a > 32-bit ID register always has _aa32_ in its name, and one that > tests a 64-bit ID register always has _aa64_ in its name. > We already follow this except for three cases: thumb_div, > arm_div and jazelle, which all need _aa32_ adding. > > (As noted in the comment, isar_feature_aa32_fp16_arith() > is an exception in that it currently tests ID_AA64PFR0_EL1, > but will switch to MVFR1 once we've properly implemented > FP16 for AArch32.) > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/cpu.h | 13 ++++++++++--- > linux-user/elfload.c | 4 ++-- > target/arm/cpu.c | 6 ++++-- > target/arm/helper.c | 2 +- > target/arm/translate.c | 6 +++--- > 5 files changed, 20 insertions(+), 11 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 2/11/20 6:37 PM, Peter Maydell wrote: > Enforce a convention that an isar_feature function that tests a > 32-bit ID register always has _aa32_ in its name, and one that > tests a 64-bit ID register always has _aa64_ in its name. > We already follow this except for three cases: thumb_div, > arm_div and jazelle, which all need _aa32_ adding. > > (As noted in the comment, isar_feature_aa32_fp16_arith() > is an exception in that it currently tests ID_AA64PFR0_EL1, > but will switch to MVFR1 once we've properly implemented > FP16 for AArch32.) > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > target/arm/cpu.h | 13 ++++++++++--- > linux-user/elfload.c | 4 ++-- > target/arm/cpu.c | 6 ++++-- > target/arm/helper.c | 2 +- > target/arm/translate.c | 6 +++--- > 5 files changed, 20 insertions(+), 11 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 608fcbd0b75..ad2f0e172a7 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -3396,20 +3396,27 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) > /* Shared between translate-sve.c and sve_helper.c. */ > extern const uint64_t pred_esz_masks[4]; > > +/* > + * Naming convention for isar_feature functions: > + * Functions which test 32-bit ID registers should have _aa32_ in > + * their name. Functions which test 64-bit ID registers should have > + * _aa64_ in their name. > + */ > + > /* > * 32-bit feature tests via id registers. > */ > -static inline bool isar_feature_thumb_div(const ARMISARegisters *id) > +static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) > { > return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; > } > > -static inline bool isar_feature_arm_div(const ARMISARegisters *id) > +static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) > { > return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; > } > > -static inline bool isar_feature_jazelle(const ARMISARegisters *id) > +static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) > { > return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; > } > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index f3080a16358..b1a895f24ce 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -475,8 +475,8 @@ static uint32_t get_elf_hwcap(void) > GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); > GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); > GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); > - GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA); > - GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT); > + GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA); > + GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT); > /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c. > * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of > * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index f86e71a260d..5712082c0b9 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1470,7 +1470,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > * Presence of EL2 itself is ARM_FEATURE_EL2, and of the > * Security Extensions is ARM_FEATURE_EL3. > */ > - assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)); > + assert(!tcg_enabled() || no_aa32 || > + cpu_isar_feature(aa32_arm_div, cpu)); > set_feature(env, ARM_FEATURE_LPAE); > set_feature(env, ARM_FEATURE_V7); > } > @@ -1496,7 +1497,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > if (arm_feature(env, ARM_FEATURE_V6)) { > set_feature(env, ARM_FEATURE_V5); > if (!arm_feature(env, ARM_FEATURE_M)) { > - assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu)); > + assert(!tcg_enabled() || no_aa32 || > + cpu_isar_feature(aa32_jazelle, cpu)); > set_feature(env, ARM_FEATURE_AUXCR); > } > } > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 19a57a17da5..ddfd0183d98 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6781,7 +6781,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) > if (arm_feature(env, ARM_FEATURE_LPAE)) { > define_arm_cp_regs(cpu, lpae_cp_reginfo); > } > - if (cpu_isar_feature(jazelle, cpu)) { > + if (cpu_isar_feature(aa32_jazelle, cpu)) { > define_arm_cp_regs(cpu, jazelle_regs); > } > /* Slightly awkwardly, the OMAP and StrongARM cores need all of > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 2f4aea927f1..052992037cc 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -42,7 +42,7 @@ > #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) > /* currently all emulated v5 cores are also v5TE, so don't bother */ > #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) > -#define ENABLE_ARCH_5J dc_isar_feature(jazelle, s) > +#define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s) > #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) > #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) > #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) > @@ -9850,8 +9850,8 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool u) > TCGv_i32 t1, t2; > > if (s->thumb > - ? !dc_isar_feature(thumb_div, s) > - : !dc_isar_feature(arm_div, s)) { > + ? !dc_isar_feature(aa32_thumb_div, s) > + : !dc_isar_feature(aa32_arm_div, s)) { > return false; > } > >
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 608fcbd0b75..ad2f0e172a7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3396,20 +3396,27 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[4]; +/* + * Naming convention for isar_feature functions: + * Functions which test 32-bit ID registers should have _aa32_ in + * their name. Functions which test 64-bit ID registers should have + * _aa64_ in their name. + */ + /* * 32-bit feature tests via id registers. */ -static inline bool isar_feature_thumb_div(const ARMISARegisters *id) +static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; } -static inline bool isar_feature_arm_div(const ARMISARegisters *id) +static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; } -static inline bool isar_feature_jazelle(const ARMISARegisters *id) +static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; } diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f3080a16358..b1a895f24ce 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -475,8 +475,8 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); - GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA); - GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT); + GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA); + GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT); /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c. * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f86e71a260d..5712082c0b9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1470,7 +1470,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * Presence of EL2 itself is ARM_FEATURE_EL2, and of the * Security Extensions is ARM_FEATURE_EL3. */ - assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)); + assert(!tcg_enabled() || no_aa32 || + cpu_isar_feature(aa32_arm_div, cpu)); set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_V7); } @@ -1496,7 +1497,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); if (!arm_feature(env, ARM_FEATURE_M)) { - assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu)); + assert(!tcg_enabled() || no_aa32 || + cpu_isar_feature(aa32_jazelle, cpu)); set_feature(env, ARM_FEATURE_AUXCR); } } diff --git a/target/arm/helper.c b/target/arm/helper.c index 19a57a17da5..ddfd0183d98 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6781,7 +6781,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, lpae_cp_reginfo); } - if (cpu_isar_feature(jazelle, cpu)) { + if (cpu_isar_feature(aa32_jazelle, cpu)) { define_arm_cp_regs(cpu, jazelle_regs); } /* Slightly awkwardly, the OMAP and StrongARM cores need all of diff --git a/target/arm/translate.c b/target/arm/translate.c index 2f4aea927f1..052992037cc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -42,7 +42,7 @@ #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) -#define ENABLE_ARCH_5J dc_isar_feature(jazelle, s) +#define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s) #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) @@ -9850,8 +9850,8 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool u) TCGv_i32 t1, t2; if (s->thumb - ? !dc_isar_feature(thumb_div, s) - : !dc_isar_feature(arm_div, s)) { + ? !dc_isar_feature(aa32_thumb_div, s) + : !dc_isar_feature(aa32_arm_div, s)) { return false; }
Enforce a convention that an isar_feature function that tests a 32-bit ID register always has _aa32_ in its name, and one that tests a 64-bit ID register always has _aa64_ in its name. We already follow this except for three cases: thumb_div, arm_div and jazelle, which all need _aa32_ adding. (As noted in the comment, isar_feature_aa32_fp16_arith() is an exception in that it currently tests ID_AA64PFR0_EL1, but will switch to MVFR1 once we've properly implemented FP16 for AArch32.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 13 ++++++++++--- linux-user/elfload.c | 4 ++-- target/arm/cpu.c | 6 ++++-- target/arm/helper.c | 2 +- target/arm/translate.c | 6 +++--- 5 files changed, 20 insertions(+), 11 deletions(-)