diff mbox series

[PULL,33/48] target/arm: Update arm_phys_excp_target_el for TGE

Message ID 20200207143343.30322-34-peter.maydell@linaro.org
State New
Headers show
Series [PULL,01/48] target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none | expand

Commit Message

Peter Maydell Feb. 7, 2020, 2:33 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>

The TGE bit routes all asynchronous exceptions to EL2.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3b7b459314d..56a62b11d09 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8446,6 +8446,12 @@  uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
         break;
     };
 
+    /*
+     * For these purposes, TGE and AMO/IMO/FMO both force the
+     * interrupt to EL2.  Fold TGE into the bit extracted above.
+     */
+    hcr |= (hcr_el2 & HCR_TGE) != 0;
+
     /* Perform a table-lookup for the target EL given the current state */
     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];