| Message ID | 20200202010439.6410-2-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Implement PAN, ATS1E1, UAO | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > Use a common predicate for querying stage1-ness. > > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > v2: Rename from arm_mmu_idx_is_stage1 to arm_mmu_idx_is_stage1_of_2 > --- > target/arm/internals.h | 18 ++++++++++++++++++ > target/arm/helper.c | 8 +++----- > 2 files changed, 21 insertions(+), 5 deletions(-) > > diff --git a/target/arm/internals.h b/target/arm/internals.h > index 6d4a942bde..1f8ee5f573 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -1034,6 +1034,24 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) > ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); > #endif > > +/** > + * arm_mmu_idx_is_stage1_of_2: > + * @mmu_idx: The ARMMMUIdx to test > + * > + * Return true if @mmu_idx is a NOTLB mmu_idx that is the > + * first stage of a two stage regime. > + */ > +static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) > +{ > + switch (mmu_idx) { > + case ARMMMUIdx_Stage1_E0: > + case ARMMMUIdx_Stage1_E1: > + return true; > + default: > + return false; > + } > +} > + > /* > * Parameters of a given virtual address, as extracted from the > * translation control register (TCR) for a given regime. > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 70b10428c5..852fd71dcc 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3261,8 +3261,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, > bool take_exc = false; > > if (fi.s1ptw && current_el == 1 && !arm_is_secure(env) > - && (mmu_idx == ARMMMUIdx_Stage1_E1 || > - mmu_idx == ARMMMUIdx_Stage1_E0)) { > + && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { > /* > * Synchronous stage 2 fault on an access made as part of the > * translation table walk for AT S1E0* or AT S1E1* insn > @@ -9294,8 +9293,7 @@ static inline bool regime_translation_disabled(CPUARMState *env, > } > } > > - if ((env->cp15.hcr_el2 & HCR_DC) && > - (mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1)) { > + if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { > /* HCR.DC means SCTLR_EL1.M behaves as 0 */ > return true; > } > @@ -9604,7 +9602,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, > hwaddr addr, MemTxAttrs txattrs, > ARMMMUFaultInfo *fi) > { > - if ((mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1) && > + if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && > !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { > target_ulong s2size; > hwaddr s2pa;
diff --git a/target/arm/internals.h b/target/arm/internals.h index 6d4a942bde..1f8ee5f573 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1034,6 +1034,24 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); #endif +/** + * arm_mmu_idx_is_stage1_of_2: + * @mmu_idx: The ARMMMUIdx to test + * + * Return true if @mmu_idx is a NOTLB mmu_idx that is the + * first stage of a two stage regime. + */ +static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + return true; + default: + return false; + } +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/helper.c b/target/arm/helper.c index 70b10428c5..852fd71dcc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3261,8 +3261,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, bool take_exc = false; if (fi.s1ptw && current_el == 1 && !arm_is_secure(env) - && (mmu_idx == ARMMMUIdx_Stage1_E1 || - mmu_idx == ARMMMUIdx_Stage1_E0)) { + && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { /* * Synchronous stage 2 fault on an access made as part of the * translation table walk for AT S1E0* or AT S1E1* insn @@ -9294,8 +9293,7 @@ static inline bool regime_translation_disabled(CPUARMState *env, } } - if ((env->cp15.hcr_el2 & HCR_DC) && - (mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1)) { + if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -9604,7 +9602,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, ARMMMUFaultInfo *fi) { - if ((mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1) && + if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa;