diff --git a/hw/display/atom-bits.h b/hw/display/atom-bits.h
deleted file mode 100644
index e8fae5c775..0000000000
--- a/hw/display/atom-bits.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Author: Stanislaw Skowronek
- */
-
-#ifndef ATOM_BITS_H
-#define ATOM_BITS_H
-
-static inline uint8_t get_u8(void *bios, int ptr)
-{
-    return ((unsigned char *)bios)[ptr];
-}
-#define U8(ptr) get_u8(ctx->ctx->bios, (ptr))
-#define CU8(ptr) get_u8(ctx->bios, (ptr))
-static inline uint16_t get_u16(void *bios, int ptr)
-{
-    return get_u8(bios ,ptr)|(((uint16_t)get_u8(bios, ptr+1))<<8);
-}
-#define U16(ptr) get_u16(ctx->ctx->bios, (ptr))
-#define CU16(ptr) get_u16(ctx->bios, (ptr))
-static inline uint32_t get_u32(void *bios, int ptr)
-{
-    return get_u16(bios, ptr)|(((uint32_t)get_u16(bios, ptr+2))<<16);
-}
-#define U32(ptr) get_u32(ctx->ctx->bios, (ptr))
-#define CU32(ptr) get_u32(ctx->bios, (ptr))
-#define CSTR(ptr) (((char *)(ctx->bios))+(ptr))
-
-#endif
diff --git a/hw/display/atom-names.h b/hw/display/atom-names.h
deleted file mode 100644
index 6f907a5ffa..0000000000
--- a/hw/display/atom-names.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Author: Stanislaw Skowronek
- */
-
-#ifndef ATOM_NAMES_H
-#define ATOM_NAMES_H
-
-#include "atom.h"
-
-#ifdef ATOM_DEBUG
-
-#define ATOM_OP_NAMES_CNT 123
-static char *atom_op_names[ATOM_OP_NAMES_CNT] = {
-"RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL",
-"MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC",
-"OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG",
-"SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL",
-"SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS",
-"SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG",
-"MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS",
-"DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS",
-"ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB",
-"SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT",
-"SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS",
-"COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH",
-"JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL",
-"JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS",
-"TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC",
-"CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB",
-"CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS",
-"MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG",
-"RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB",
-"XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL",
-"SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC",
-"DEBUG", "CTB_DS",
-};
-
-#define ATOM_TABLE_NAMES_CNT 74
-static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = {
-"ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit",
-"VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit",
-"GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl",
-"GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock",
-"DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice",
-"MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController",
-"EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange",
-"DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl",
-"DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl",
-"CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl",
-"TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl",
-"EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock",
-"EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing",
-"SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source",
-"EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters",
-"LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock",
-"GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection",
-"DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp",
-"ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C",
-"ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection",
-"MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion",
-"VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining",
-"EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl",
-"CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource",
-"MemoryDeviceInit", "EnableYUV",
-};
-
-#define ATOM_IO_NAMES_CNT 5
-static char *atom_io_names[ATOM_IO_NAMES_CNT] = {
-"MM", "PLL", "MC", "PCIE", "PCIE PORT",
-};
-
-#else
-
-#define ATOM_OP_NAMES_CNT 0
-#define ATOM_TABLE_NAMES_CNT 0
-#define ATOM_IO_NAMES_CNT 0
-
-#endif
-
-#endif
diff --git a/hw/display/atom-types.h b/hw/display/atom-types.h
deleted file mode 100644
index 1125b866cd..0000000000
--- a/hw/display/atom-types.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2008 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Author: Dave Airlie
- */
-
-#ifndef ATOM_TYPES_H
-#define ATOM_TYPES_H
-
-/* sync atom types to kernel types */
-
-typedef uint16_t USHORT;
-typedef uint32_t ULONG;
-typedef uint8_t UCHAR;
-
-
-#ifndef ATOM_BIG_ENDIAN
-#if defined(__BIG_ENDIAN)
-#define ATOM_BIG_ENDIAN 1
-#else
-#define ATOM_BIG_ENDIAN 0
-#endif
-#endif
-#endif
diff --git a/hw/display/atom.h b/hw/display/atom.h
deleted file mode 100644
index 364b895e7e..0000000000
--- a/hw/display/atom.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Author: Stanislaw Skowronek
- */
-
-#ifndef ATOM_H
-#define ATOM_H
-
-#include <linux/types.h>
-
-#define ATOM_BIOS_MAGIC		0xAA55
-#define ATOM_ATI_MAGIC_PTR	0x30
-#define ATOM_ATI_MAGIC		" 761295520"
-#define ATOM_ROM_TABLE_PTR	0x48
-
-#define ATOM_ROM_MAGIC		"ATOM"
-#define ATOM_ROM_MAGIC_PTR	4
-
-#define ATOM_ROM_MSG_PTR	0x10
-#define ATOM_ROM_CMD_PTR	0x1E
-#define ATOM_ROM_DATA_PTR	0x20
-
-#define ATOM_CMD_INIT		0
-#define ATOM_CMD_SETSCLK	0x0A
-#define ATOM_CMD_SETMCLK	0x0B
-#define ATOM_CMD_SETPCLK	0x0C
-#define ATOM_CMD_SPDFANCNTL	0x39
-
-#define ATOM_DATA_FWI_PTR	0xC
-#define ATOM_DATA_IIO_PTR	0x32
-
-#define ATOM_FWI_DEFSCLK_PTR	8
-#define ATOM_FWI_DEFMCLK_PTR	0xC
-#define ATOM_FWI_MAXSCLK_PTR	0x24
-#define ATOM_FWI_MAXMCLK_PTR	0x28
-
-#define ATOM_CT_SIZE_PTR	0
-#define ATOM_CT_WS_PTR		4
-#define ATOM_CT_PS_PTR		5
-#define ATOM_CT_PS_MASK		0x7F
-#define ATOM_CT_CODE_PTR	6
-
-#define ATOM_OP_CNT		123
-#define ATOM_OP_EOT		91
-
-#define ATOM_CASE_MAGIC		0x63
-#define ATOM_CASE_END		0x5A5A
-
-#define ATOM_ARG_REG		0
-#define ATOM_ARG_PS		1
-#define ATOM_ARG_WS		2
-#define ATOM_ARG_FB		3
-#define ATOM_ARG_ID		4
-#define ATOM_ARG_IMM		5
-#define ATOM_ARG_PLL		6
-#define ATOM_ARG_MC		7
-
-#define ATOM_SRC_DWORD		0
-#define ATOM_SRC_WORD0		1
-#define ATOM_SRC_WORD8		2
-#define ATOM_SRC_WORD16		3
-#define ATOM_SRC_BYTE0		4
-#define ATOM_SRC_BYTE8		5
-#define ATOM_SRC_BYTE16		6
-#define ATOM_SRC_BYTE24		7
-
-#define ATOM_WS_QUOTIENT	0x40
-#define ATOM_WS_REMAINDER	0x41
-#define ATOM_WS_DATAPTR		0x42
-#define ATOM_WS_SHIFT		0x43
-#define ATOM_WS_OR_MASK		0x44
-#define ATOM_WS_AND_MASK	0x45
-#define ATOM_WS_FB_WINDOW	0x46
-#define ATOM_WS_ATTRIBUTES	0x47
-#define ATOM_WS_REGPTR  	0x48
-
-#define ATOM_IIO_NOP		0
-#define ATOM_IIO_START		1
-#define ATOM_IIO_READ		2
-#define ATOM_IIO_WRITE		3
-#define ATOM_IIO_CLEAR		4
-#define ATOM_IIO_SET		5
-#define ATOM_IIO_MOVE_INDEX	6
-#define ATOM_IIO_MOVE_ATTR	7
-#define ATOM_IIO_MOVE_DATA	8
-#define ATOM_IIO_END		9
-
-#define ATOM_IO_MM		0
-#define ATOM_IO_PCI		1
-#define ATOM_IO_SYSIO		2
-#define ATOM_IO_IIO		0x80
-
-struct card_info {
-	struct drm_device *dev;
-	void (* reg_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
-        uint32_t (* reg_read)(struct card_info *, uint32_t);          /*  filled by driver */
-	void (* ioreg_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
-        uint32_t (* ioreg_read)(struct card_info *, uint32_t);          /*  filled by driver */
-	void (* mc_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
-        uint32_t (* mc_read)(struct card_info *, uint32_t);          /*  filled by driver */
-	void (* pll_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
-        uint32_t (* pll_read)(struct card_info *, uint32_t);          /*  filled by driver */
-};
-
-struct atom_context {
-	struct card_info *card;
-	struct mutex mutex;
-	struct mutex scratch_mutex;
-	void *bios;
-	uint32_t cmd_table, data_table;
-	uint16_t *iio;
-
-	uint16_t data_block;
-	uint32_t fb_base;
-	uint32_t divmul[2];
-	uint16_t io_attr;
-	uint16_t reg_block;
-	uint8_t shift;
-	int cs_equal, cs_above;
-	int io_mode;
-	uint32_t *scratch;
-	int scratch_size_bytes;
-};
-
-extern int atom_debug;
-
-struct atom_context *atom_parse(struct card_info *, void *);
-int atom_execute_table(struct atom_context *, int, uint32_t *);
-int atom_execute_table_scratch_unlocked(struct atom_context *, int, uint32_t *);
-int atom_asic_init(struct atom_context *);
-void atom_destroy(struct atom_context *);
-bool atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size,
-			    uint8_t *frev, uint8_t *crev, uint16_t *data_start);
-bool atom_parse_cmd_header(struct atom_context *ctx, int index,
-			   uint8_t *frev, uint8_t *crev);
-int atom_allocate_fb_scratch(struct atom_context *ctx);
-#include "atom-types.h"
-#include "atombios.h"
-#include "ObjectID.h"
-
-#endif
diff --git a/hw/display/atombios.h b/hw/display/atombios.h
deleted file mode 100644
index 4b86e8b450..0000000000
--- a/hw/display/atombios.h
+++ /dev/null
@@ -1,7981 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.  
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-
-/****************************************************************************/	
-/*Portion I: Definitions  shared between VBIOS and Driver                   */
-/****************************************************************************/
-
-
-#ifndef _ATOMBIOS_H
-#define _ATOMBIOS_H
-
-#define ATOM_VERSION_MAJOR                   0x00020000
-#define ATOM_VERSION_MINOR                   0x00000002
-
-#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
-
-/* Endianness should be specified before inclusion,
- * default to little endian
- */
-#ifndef ATOM_BIG_ENDIAN
-#error Endian not specified
-#endif
-
-#ifdef _H2INC
-  #ifndef ULONG 
-    typedef unsigned long ULONG;
-  #endif
-
-  #ifndef UCHAR
-    typedef unsigned char UCHAR;
-  #endif
-
-  #ifndef USHORT 
-    typedef unsigned short USHORT;
-  #endif
-#endif
-      
-#define ATOM_DAC_A            0 
-#define ATOM_DAC_B            1
-#define ATOM_EXT_DAC          2
-
-#define ATOM_CRTC1            0
-#define ATOM_CRTC2            1
-#define ATOM_CRTC3            2
-#define ATOM_CRTC4            3
-#define ATOM_CRTC5            4
-#define ATOM_CRTC6            5
-#define ATOM_CRTC_INVALID     0xFF
-
-#define ATOM_DIGA             0
-#define ATOM_DIGB             1
-
-#define ATOM_PPLL1            0
-#define ATOM_PPLL2            1
-#define ATOM_DCPLL            2
-#define ATOM_PPLL0            2
-#define ATOM_PPLL3            3
-
-#define ATOM_EXT_PLL1         8
-#define ATOM_EXT_PLL2         9
-#define ATOM_EXT_CLOCK        10
-#define ATOM_PPLL_INVALID     0xFF
-
-#define ENCODER_REFCLK_SRC_P1PLL       0       
-#define ENCODER_REFCLK_SRC_P2PLL       1
-#define ENCODER_REFCLK_SRC_DCPLL       2
-#define ENCODER_REFCLK_SRC_EXTCLK      3
-#define ENCODER_REFCLK_SRC_INVALID     0xFF
-
-#define ATOM_SCALER1          0
-#define ATOM_SCALER2          1
-
-#define ATOM_SCALER_DISABLE   0   
-#define ATOM_SCALER_CENTER    1   
-#define ATOM_SCALER_EXPANSION 2   
-#define ATOM_SCALER_MULTI_EX  3   
-
-#define ATOM_DISABLE          0
-#define ATOM_ENABLE           1
-#define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)
-#define ATOM_LCD_BLON                           (ATOM_ENABLE+2)
-#define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)
-#define ATOM_LCD_SELFTEST_START									(ATOM_DISABLE+5)
-#define ATOM_LCD_SELFTEST_STOP									(ATOM_ENABLE+5)
-#define ATOM_ENCODER_INIT			                  (ATOM_DISABLE+7)
-#define ATOM_INIT			                          (ATOM_DISABLE+7)
-#define ATOM_GET_STATUS                         (ATOM_DISABLE+8)
-
-#define ATOM_BLANKING         1
-#define ATOM_BLANKING_OFF     0
-
-#define ATOM_CURSOR1          0
-#define ATOM_CURSOR2          1
-
-#define ATOM_ICON1            0
-#define ATOM_ICON2            1
-
-#define ATOM_CRT1             0
-#define ATOM_CRT2             1
-
-#define ATOM_TV_NTSC          1
-#define ATOM_TV_NTSCJ         2
-#define ATOM_TV_PAL           3
-#define ATOM_TV_PALM          4
-#define ATOM_TV_PALCN         5
-#define ATOM_TV_PALN          6
-#define ATOM_TV_PAL60         7
-#define ATOM_TV_SECAM         8
-#define ATOM_TV_CV            16
-
-#define ATOM_DAC1_PS2         1
-#define ATOM_DAC1_CV          2
-#define ATOM_DAC1_NTSC        3
-#define ATOM_DAC1_PAL         4
-
-#define ATOM_DAC2_PS2         ATOM_DAC1_PS2
-#define ATOM_DAC2_CV          ATOM_DAC1_CV
-#define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC
-#define ATOM_DAC2_PAL         ATOM_DAC1_PAL
- 
-#define ATOM_PM_ON            0
-#define ATOM_PM_STANDBY       1
-#define ATOM_PM_SUSPEND       2
-#define ATOM_PM_OFF           3
-
-/* Bit0:{=0:single, =1:dual},
-   Bit1 {=0:666RGB, =1:888RGB},
-   Bit2:3:{Grey level}
-   Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
-
-#define ATOM_PANEL_MISC_DUAL               0x00000001
-#define ATOM_PANEL_MISC_888RGB             0x00000002
-#define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C
-#define ATOM_PANEL_MISC_FPDI               0x00000010
-#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
-#define ATOM_PANEL_MISC_SPATIAL            0x00000020
-#define ATOM_PANEL_MISC_TEMPORAL           0x00000040
-#define ATOM_PANEL_MISC_API_ENABLED        0x00000080
-
-
-#define MEMTYPE_DDR1              "DDR1"
-#define MEMTYPE_DDR2              "DDR2"
-#define MEMTYPE_DDR3              "DDR3"
-#define MEMTYPE_DDR4              "DDR4"
-
-#define ASIC_BUS_TYPE_PCI         "PCI"
-#define ASIC_BUS_TYPE_AGP         "AGP"
-#define ASIC_BUS_TYPE_PCIE        "PCI_EXPRESS"
-
-/* Maximum size of that FireGL flag string */
-
-#define ATOM_FIREGL_FLAG_STRING     "FGL"             //Flag used to enable FireGL Support
-#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING  3        //sizeof( ATOM_FIREGL_FLAG_STRING )
-
-#define ATOM_FAKE_DESKTOP_STRING    "DSK"             //Flag used to enable mobile ASIC on Desktop
-#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING  ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 
-
-#define ATOM_M54T_FLAG_STRING       "M54T"            //Flag used to enable M54T Support
-#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING    4        //sizeof( ATOM_M54T_FLAG_STRING )
-
-#define HW_ASSISTED_I2C_STATUS_FAILURE          2
-#define HW_ASSISTED_I2C_STATUS_SUCCESS          1
-
-#pragma pack(1)                                       /* BIOS data must use byte alignment */
-
-/*  Define offset to location of ROM header. */
-
-#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER		0x00000048L
-#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE				    0x00000002L
-
-#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE    0x94
-#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE   20    /* including the terminator 0x0! */
-#define	OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER		0x002f
-#define	OFFSET_TO_GET_ATOMBIOS_STRINGS_START		0x006e
-
-/* Common header for all ROM Data tables.
-  Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header. 
-  And the pointer actually points to this header. */
-
-typedef struct _ATOM_COMMON_TABLE_HEADER
-{
-  USHORT usStructureSize;
-  UCHAR  ucTableFormatRevision;   /*Change it when the Parser is not backward compatible */
-  UCHAR  ucTableContentRevision;  /*Change it only when the table needs to change but the firmware */
-                                  /*Image can't be updated, while Driver needs to carry the new table! */
-}ATOM_COMMON_TABLE_HEADER;
-
-/****************************************************************************/	
-// Structure stores the ROM header.
-/****************************************************************************/	
-typedef struct _ATOM_ROM_HEADER
-{
-  ATOM_COMMON_TABLE_HEADER		sHeader;
-  UCHAR	 uaFirmWareSignature[4];    /*Signature to distinguish between Atombios and non-atombios, 
-                                      atombios should init it as "ATOM", don't change the position */
-  USHORT usBiosRuntimeSegmentAddress;
-  USHORT usProtectedModeInfoOffset;
-  USHORT usConfigFilenameOffset;
-  USHORT usCRC_BlockOffset;
-  USHORT usBIOS_BootupMessageOffset;
-  USHORT usInt10Offset;
-  USHORT usPciBusDevInitCode;
-  USHORT usIoBaseAddress;
-  USHORT usSubsystemVendorID;
-  USHORT usSubsystemID;
-  USHORT usPCI_InfoOffset; 
-  USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
-  USHORT usMasterDataTableOffset;   /*Offset for SW to get all data table offsets, Don't change the position */
-  UCHAR  ucExtendedFunctionCode;
-  UCHAR  ucReserved;
-}ATOM_ROM_HEADER;
-
-/*==============================Command Table Portion==================================== */
-
-#ifdef	UEFI_BUILD
-	#define	UTEMP	USHORT
-	#define	USHORT	void*
-#endif
-
-/****************************************************************************/	
-// Structures used in Command.mtb 
-/****************************************************************************/	
-typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
-  USHORT ASIC_Init;                              //Function Table, used by various SW components,latest version 1.1
-  USHORT GetDisplaySurfaceSize;                  //Atomic Table,  Used by Bios when enabling HW ICON
-  USHORT ASIC_RegistersInit;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
-  USHORT VRAM_BlockVenderDetection;              //Atomic Table,  used only by Bios
-  USHORT DIGxEncoderControl;										 //Only used by Bios
-  USHORT MemoryControllerInit;                   //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
-  USHORT EnableCRTCMemReq;                       //Function Table,directly used by various SW components,latest version 2.1
-  USHORT MemoryParamAdjust; 										 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed
-  USHORT DVOEncoderControl;                      //Function Table,directly used by various SW components,latest version 1.2
-  USHORT GPIOPinControl;												 //Atomic Table,  only used by Bios
-  USHORT SetEngineClock;                         //Function Table,directly used by various SW components,latest version 1.1
-  USHORT SetMemoryClock;                         //Function Table,directly used by various SW components,latest version 1.1
-  USHORT SetPixelClock;                          //Function Table,directly used by various SW components,latest version 1.2  
-  USHORT EnableDispPowerGating;                  //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
-  USHORT ResetMemoryDLL;                         //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
-  USHORT ResetMemoryDevice;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
-  USHORT MemoryPLLInit;                          //Atomic Table,  used only by Bios
-  USHORT AdjustDisplayPll;											 //Atomic Table,  used by various SW componentes. 
-  USHORT AdjustMemoryController;                 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock                
-  USHORT EnableASIC_StaticPwrMgt;                //Atomic Table,  only used by Bios
-  USHORT SetUniphyInstance;                      //Atomic Table,  only used by Bios   
-  USHORT DAC_LoadDetection;                      //Atomic Table,  directly used by various SW components,latest version 1.2  
-  USHORT LVTMAEncoderControl;                    //Atomic Table,directly used by various SW components,latest version 1.3
-  USHORT HW_Misc_Operation;                      //Atomic Table,  directly used by various SW components,latest version 1.1 
-  USHORT DAC1EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1  
-  USHORT DAC2EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1 
-  USHORT DVOOutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1 
-  USHORT CV1OutputControl;                       //Atomic Table,  Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead 
-  USHORT GetConditionalGoldenSetting;            //Only used by Bios
-  USHORT TVEncoderControl;                       //Function Table,directly used by various SW components,latest version 1.1
-  USHORT PatchMCSetting;                         //only used by BIOS
-  USHORT MC_SEQ_Control;                         //only used by BIOS
-  USHORT Gfx_Harvesting;                         //Atomic Table,  Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting
-  USHORT EnableScaler;                           //Atomic Table,  used only by Bios
-  USHORT BlankCRTC;                              //Atomic Table,  directly used by various SW components,latest version 1.1 
-  USHORT EnableCRTC;                             //Atomic Table,  directly used by various SW components,latest version 1.1 
-  USHORT GetPixelClock;                          //Atomic Table,  directly used by various SW components,latest version 1.1 
-  USHORT EnableVGA_Render;                       //Function Table,directly used by various SW components,latest version 1.1
-  USHORT GetSCLKOverMCLKRatio;                   //Atomic Table,  only used by Bios
-  USHORT SetCRTC_Timing;                         //Atomic Table,  directly used by various SW components,latest version 1.1
-  USHORT SetCRTC_OverScan;                       //Atomic Table,  used by various SW components,latest version 1.1 
-  USHORT SetCRTC_Replication;                    //Atomic Table,  used only by Bios
-  USHORT SelectCRTC_Source;                      //Atomic Table,  directly used by various SW components,latest version 1.1 
-  USHORT EnableGraphSurfaces;                    //Atomic Table,  used only by Bios
-  USHORT UpdateCRTC_DoubleBufferRegisters;			 //Atomic Table,  used only by Bios
-  USHORT LUT_AutoFill;                           //Atomic Table,  only used by Bios
-  USHORT EnableHW_IconCursor;                    //Atomic Table,  only used by Bios
-  USHORT GetMemoryClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1 
-  USHORT GetEngineClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1 
-  USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
-  USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
-  USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
-  USHORT VRAM_BlockDetectionByStrap;             //Atomic Table,  used only by Bios
-  USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios    
-  USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
-  USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components 
-  USHORT ReadHWAssistedI2CStatus;                //Atomic Table,  indirectly used by various SW components
-  USHORT SpeedFanControl;                        //Function Table,indirectly used by various SW components,called from ASIC_Init
-  USHORT PowerConnectorDetection;                //Atomic Table,  directly used by various SW components,latest version 1.1
-  USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
-  USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
-  USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
-  USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
-  USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
-  USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
-  USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
-  USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
-  USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
-  USHORT DAC1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
-  USHORT DAC2OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
-  USHORT ComputeMemoryClockParam;                //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
-  USHORT ClockSource;                            //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
-  USHORT MemoryDeviceInit;                       //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
-  USHORT GetDispObjectInfo;                      //Atomic Table,  indirectly used by various SW components,called from EnableVGARender
-  USHORT DIG1EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
-  USHORT DIG2EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
-  USHORT DIG1TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
-  USHORT DIG2TransmitterControl;	               //Atomic Table,directly used by various SW components,latest version 1.1 
-  USHORT ProcessAuxChannelTransaction;					 //Function Table,only used by Bios
-  USHORT DPEncoderService;											 //Function Table,only used by Bios
-  USHORT GetVoltageInfo;                         //Function Table,only used by Bios since SI
-}ATOM_MASTER_LIST_OF_COMMAND_TABLES;   
-
-// For backward compatible 
-#define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
-#define DPTranslatorControl                      DIG2EncoderControl
-#define UNIPHYTransmitterControl			     DIG1TransmitterControl
-#define LVTMATransmitterControl				     DIG2TransmitterControl
-#define SetCRTC_DPM_State                        GetConditionalGoldenSetting
-#define ASIC_StaticPwrMgtStatusChange            SetUniphyInstance 
-#define HPDInterruptService                      ReadHWAssistedI2CStatus
-#define EnableVGA_Access                         GetSCLKOverMCLKRatio
-#define EnableYUV                                GetDispObjectInfo                         
-#define DynamicClockGating                       EnableDispPowerGating
-#define SetupHWAssistedI2CStatus                 ComputeMemoryClockParam
-
-#define TMDSAEncoderControl                      PatchMCSetting
-#define LVDSEncoderControl                       MC_SEQ_Control
-#define LCD1OutputControl                        HW_Misc_Operation
-#define TV1OutputControl                         Gfx_Harvesting
-
-typedef struct _ATOM_MASTER_COMMAND_TABLE
-{
-  ATOM_COMMON_TABLE_HEADER           sHeader;
-  ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
-}ATOM_MASTER_COMMAND_TABLE;
-
-/****************************************************************************/	
-// Structures used in every command table
-/****************************************************************************/	
-typedef struct _ATOM_TABLE_ATTRIBUTE
-{
-#if ATOM_BIG_ENDIAN
-  USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
-  USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword), 
-  USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword), 
-#else
-  USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword), 
-  USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword), 
-  USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
-#endif
-}ATOM_TABLE_ATTRIBUTE;
-
-typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
-{
-  ATOM_TABLE_ATTRIBUTE sbfAccess;
-  USHORT               susAccess;
-}ATOM_TABLE_ATTRIBUTE_ACCESS;
-
-/****************************************************************************/	
-// Common header for all command tables.
-// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 
-// And the pointer actually points to this header.
-/****************************************************************************/	
-typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
-{
-  ATOM_COMMON_TABLE_HEADER CommonHeader;
-  ATOM_TABLE_ATTRIBUTE     TableAttribute;	
-}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
-
-/****************************************************************************/	
-// Structures used by ComputeMemoryEnginePLLTable
-/****************************************************************************/	
-#define COMPUTE_MEMORY_PLL_PARAM        1
-#define COMPUTE_ENGINE_PLL_PARAM        2
-#define ADJUST_MC_SETTING_PARAM         3
-
-/****************************************************************************/	
-// Structures used by AdjustMemoryControllerTable
-/****************************************************************************/	
-typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
-{
-#if ATOM_BIG_ENDIAN
-  ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 
-  ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
-  ULONG ulClockFreq:24;
-#else
-  ULONG ulClockFreq:24;
-  ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
-  ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 
-#endif
-}ATOM_ADJUST_MEMORY_CLOCK_FREQ;
-#define POINTER_RETURN_FLAG             0x80
-
-typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
-{
-  ULONG   ulClock;        //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
-  UCHAR   ucAction;       //0:reserved //1:Memory //2:Engine  
-  UCHAR   ucReserved;     //may expand to return larger Fbdiv later
-  UCHAR   ucFbDiv;        //return value
-  UCHAR   ucPostDiv;      //return value
-}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
-
-typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
-{
-  ULONG   ulClock;        //When return, [23:0] return real clock 
-  UCHAR   ucAction;       //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
-  USHORT  usFbDiv;		    //return Feedback value to be written to register
-  UCHAR   ucPostDiv;      //return post div to be written to register
-}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
-#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
-
-
-#define SET_CLOCK_FREQ_MASK                     0x00FFFFFF  //Clock change tables only take bit [23:0] as the requested clock value
-#define USE_NON_BUS_CLOCK_MASK                  0x01000000  //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
-#define USE_MEMORY_SELF_REFRESH_MASK            0x02000000	//Only applicable to memory clock change, when set, using memory self refresh during clock transition
-#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04000000  //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
-#define FIRST_TIME_CHANGE_CLOCK									0x08000000	//Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
-#define SKIP_SW_PROGRAM_PLL											0x10000000	//Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
-#define USE_SS_ENABLED_PIXEL_CLOCK  USE_NON_BUS_CLOCK_MASK
-
-#define b3USE_NON_BUS_CLOCK_MASK                  0x01       //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
-#define b3USE_MEMORY_SELF_REFRESH                 0x02	     //Only applicable to memory clock change, when set, using memory self refresh during clock transition
-#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04       //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
-#define b3FIRST_TIME_CHANGE_CLOCK									0x08       //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
-#define b3SKIP_SW_PROGRAM_PLL											0x10			 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
-
-typedef struct _ATOM_COMPUTE_CLOCK_FREQ
-{
-#if ATOM_BIG_ENDIAN
-  ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
-  ULONG ulClockFreq:24;                       // in unit of 10kHz
-#else
-  ULONG ulClockFreq:24;                       // in unit of 10kHz
-  ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
-#endif
-}ATOM_COMPUTE_CLOCK_FREQ;
-
-typedef struct _ATOM_S_MPLL_FB_DIVIDER
-{
-  USHORT usFbDivFrac;  
-  USHORT usFbDiv;  
-}ATOM_S_MPLL_FB_DIVIDER;
-
-typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
-{
-  union
-  {
-    ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
-    ULONG ulClockParams;                      //ULONG access for BE
-    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
-  };
-  UCHAR   ucRefDiv;                           //Output Parameter      
-  UCHAR   ucPostDiv;                          //Output Parameter      
-  UCHAR   ucCntlFlag;                         //Output Parameter      
-  UCHAR   ucReserved;
-}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
-
-// ucCntlFlag
-#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN          1
-#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE            2
-#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE         4
-#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9						8
-
-
-// V4 are only used for APU which PLL outside GPU
-typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
-{
-#if ATOM_BIG_ENDIAN
-  ULONG  ucPostDiv:8;        //return parameter: post divider which is used to program to register directly
-  ULONG  ulClock:24;         //Input= target clock, output = actual clock 
-#else
-  ULONG  ulClock:24;         //Input= target clock, output = actual clock 
-  ULONG  ucPostDiv:8;        //return parameter: post divider which is used to program to register directly
-#endif
-}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
-
-typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
-{
-  union
-  {
-    ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
-    ULONG ulClockParams;                      //ULONG access for BE
-    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
-  };
-  UCHAR   ucRefDiv;                           //Output Parameter      
-  UCHAR   ucPostDiv;                          //Output Parameter      
-  union
-  {
-    UCHAR   ucCntlFlag;                       //Output Flags
-    UCHAR   ucInputFlag;                      //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
-  };
-  UCHAR   ucReserved;                       
-}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
-
-
-typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6
-{
-  ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
-  ULONG   ulReserved[2];
-}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6;
-
-//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
-#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK            0x0f
-#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK           0x00
-#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK                     0x01
-
-typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6
-{
-  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4  ulClock;         //Output Parameter: ucPostDiv=DFS divider
-  ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter: PLL FB divider
-  UCHAR   ucPllRefDiv;                      //Output Parameter: PLL ref divider      
-  UCHAR   ucPllPostDiv;                     //Output Parameter: PLL post divider      
-  UCHAR   ucPllCntlFlag;                    //Output Flags: control flag
-  UCHAR   ucReserved;                       
-}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6;
-
-//ucPllCntlFlag
-#define SPLL_CNTL_FLAG_VCO_MODE_MASK            0x03 
-
-
-// ucInputFlag
-#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN  1   // 1-StrobeMode, 0-PerformanceMode
-
-// use for ComputeMemoryClockParamTable
-typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
-{
-  union
-  {
-    ULONG  ulClock;         
-    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output:UPPER_WORD=FB_DIV_INTEGER,  LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
-  };
-  UCHAR   ucDllSpeed;                         //Output 
-  UCHAR   ucPostDiv;                          //Output
-  union{
-    UCHAR   ucInputFlag;                      //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
-    UCHAR   ucPllCntlFlag;                    //Output: 
-  };
-  UCHAR   ucBWCntl;                       
-}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
-
-// definition of ucInputFlag
-#define MPLL_INPUT_FLAG_STROBE_MODE_EN          0x01
-// definition of ucPllCntlFlag
-#define MPLL_CNTL_FLAG_VCO_MODE_MASK            0x03 
-#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL            0x04
-#define MPLL_CNTL_FLAG_QDR_ENABLE               0x08
-#define MPLL_CNTL_FLAG_AD_HALF_RATE             0x10
-
-//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
-#define MPLL_CNTL_FLAG_BYPASS_AD_PLL            0x04
-
-typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
-{
-  ATOM_COMPUTE_CLOCK_FREQ ulClock;
-  ULONG ulReserved[2];
-}DYNAMICE_MEMORY_SETTINGS_PARAMETER;
-
-typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
-{
-  ATOM_COMPUTE_CLOCK_FREQ ulClock;
-  ULONG ulMemoryClock;
-  ULONG ulReserved;
-}DYNAMICE_ENGINE_SETTINGS_PARAMETER;
-
-/****************************************************************************/	
-// Structures used by SetEngineClockTable
-/****************************************************************************/	
-typedef struct _SET_ENGINE_CLOCK_PARAMETERS
-{
-  ULONG ulTargetEngineClock;          //In 10Khz unit
-}SET_ENGINE_CLOCK_PARAMETERS;
-
-typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
-{
-  ULONG ulTargetEngineClock;          //In 10Khz unit
-  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
-}SET_ENGINE_CLOCK_PS_ALLOCATION;
-
-/****************************************************************************/	
-// Structures used by SetMemoryClockTable
-/****************************************************************************/	
-typedef struct _SET_MEMORY_CLOCK_PARAMETERS
-{
-  ULONG ulTargetMemoryClock;          //In 10Khz unit
-}SET_MEMORY_CLOCK_PARAMETERS;
-
-typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
-{
-  ULONG ulTargetMemoryClock;          //In 10Khz unit
-  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
-}SET_MEMORY_CLOCK_PS_ALLOCATION;
-
-/****************************************************************************/	
-// Structures used by ASIC_Init.ctb
-/****************************************************************************/	
-typedef struct _ASIC_INIT_PARAMETERS
-{
-  ULONG ulDefaultEngineClock;         //In 10Khz unit
-  ULONG ulDefaultMemoryClock;         //In 10Khz unit
-}ASIC_INIT_PARAMETERS;
-
-typedef struct _ASIC_INIT_PS_ALLOCATION
-{
-  ASIC_INIT_PARAMETERS sASICInitClocks;
-  SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
-}ASIC_INIT_PS_ALLOCATION;
-
-/****************************************************************************/	
-// Structure used by DynamicClockGatingTable.ctb
-/****************************************************************************/	
-typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 
-{
-  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
-  UCHAR ucPadding[3];
-}DYNAMIC_CLOCK_GATING_PARAMETERS;
-#define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS
-
-/****************************************************************************/	
-// Structure used by EnableDispPowerGatingTable.ctb
-/****************************************************************************/	
-typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 
-{
-  UCHAR ucDispPipeId;                 // ATOM_CRTC1, ATOM_CRTC2, ...
-  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
-  UCHAR ucPadding[2];
-}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
-
-/****************************************************************************/	
-// Structure used by EnableASIC_StaticPwrMgtTable.ctb
-/****************************************************************************/	
-typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
-{
-  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
-  UCHAR ucPadding[3];
-}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
-#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
-
-/****************************************************************************/	
-// Structures used by DAC_LoadDetectionTable.ctb
-/****************************************************************************/	
-typedef struct _DAC_LOAD_DETECTION_PARAMETERS
-{
-  USHORT usDeviceID;                  //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
-  UCHAR  ucDacType;                   //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
-  UCHAR  ucMisc;											//Valid only when table revision =1.3 and above
-}DAC_LOAD_DETECTION_PARAMETERS;
-
-// DAC_LOAD_DETECTION_PARAMETERS.ucMisc
-#define DAC_LOAD_MISC_YPrPb						0x01
-
-typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
-{
-  DAC_LOAD_DETECTION_PARAMETERS            sDacload;
-  ULONG                                    Reserved[2];// Don't set this one, allocation for EXT DAC
-}DAC_LOAD_DETECTION_PS_ALLOCATION;
-
-/****************************************************************************/	
-// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
-/****************************************************************************/	
-typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 
-{
-  USHORT usPixelClock;                // in 10KHz; for bios convenient
-  UCHAR  ucDacStandard;               // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
-  UCHAR  ucAction;                    // 0: turn off encoder
-                                      // 1: setup and turn on encoder
-                                      // 7: ATOM_ENCODER_INIT Initialize DAC
-}DAC_ENCODER_CONTROL_PARAMETERS;
-
-#define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS
-
-/****************************************************************************/	
-// Structures used by DIG1EncoderControlTable
-//                    DIG2EncoderControlTable
-//                    ExternalEncoderControlTable
-/****************************************************************************/	
-typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
-{
-  USHORT usPixelClock;		// in 10KHz; for bios convenient
-  UCHAR  ucConfig;		  
-                            // [2] Link Select:
-                            // =0: PHY linkA if bfLane<3
-                            // =1: PHY linkB if bfLanes<3
-                            // =0: PHY linkA+B if bfLanes=3
-                            // [3] Transmitter Sel
-                            // =0: UNIPHY or PCIEPHY
-                            // =1: LVTMA 					
-  UCHAR ucAction;           // =0: turn off encoder					
-                            // =1: turn on encoder			
-  UCHAR ucEncoderMode;
-                            // =0: DP   encoder      
-                            // =1: LVDS encoder          
-                            // =2: DVI  encoder  
-                            // =3: HDMI encoder
-                            // =4: SDVO encoder
-  UCHAR ucLaneNum;          // how many lanes to enable
-  UCHAR ucReserved[2];
-}DIG_ENCODER_CONTROL_PARAMETERS;
-#define DIG_ENCODER_CONTROL_PS_ALLOCATION			  DIG_ENCODER_CONTROL_PARAMETERS
-#define EXTERNAL_ENCODER_CONTROL_PARAMETER			DIG_ENCODER_CONTROL_PARAMETERS
-
-//ucConfig
-#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK				0x01
-#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ		0x00
-#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ		0x01
-#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ		0x02
-#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK				  0x04
-#define ATOM_ENCODER_CONFIG_LINKA								  0x00
-#define ATOM_ENCODER_CONFIG_LINKB								  0x04
-#define ATOM_ENCODER_CONFIG_LINKA_B							  ATOM_TRANSMITTER_CONFIG_LINKA
-#define ATOM_ENCODER_CONFIG_LINKB_A							  ATOM_ENCODER_CONFIG_LINKB
-#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK	0x08
-#define ATOM_ENCODER_CONFIG_UNIPHY							  0x00
-#define ATOM_ENCODER_CONFIG_LVTMA								  0x08
-#define ATOM_ENCODER_CONFIG_TRANSMITTER1				  0x00
-#define ATOM_ENCODER_CONFIG_TRANSMITTER2				  0x08
-#define ATOM_ENCODER_CONFIG_DIGB								  0x80			// VBIOS Internal use, outside SW should set this bit=0
-// ucAction
-// ATOM_ENABLE:  Enable Encoder
-// ATOM_DISABLE: Disable Encoder
-
-//ucEncoderMode
-#define ATOM_ENCODER_MODE_DP											0
-#define ATOM_ENCODER_MODE_LVDS										1
-#define ATOM_ENCODER_MODE_DVI											2
-#define ATOM_ENCODER_MODE_HDMI										3
-#define ATOM_ENCODER_MODE_SDVO										4
-#define ATOM_ENCODER_MODE_DP_AUDIO                5
-#define ATOM_ENCODER_MODE_TV											13
-#define ATOM_ENCODER_MODE_CV											14
-#define ATOM_ENCODER_MODE_CRT											15
-#define ATOM_ENCODER_MODE_DVO											16
-#define ATOM_ENCODER_MODE_DP_SST                  ATOM_ENCODER_MODE_DP    // For DP1.2
-#define ATOM_ENCODER_MODE_DP_MST                  5                       // For DP1.2
-
-typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
-{
-#if ATOM_BIG_ENDIAN
-    UCHAR ucReserved1:2;
-    UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
-    UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
-    UCHAR ucReserved:1;
-    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
-#else
-    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
-    UCHAR ucReserved:1;
-    UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
-    UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
-    UCHAR ucReserved1:2;
-#endif
-}ATOM_DIG_ENCODER_CONFIG_V2;
-
-
-typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
-{
-  USHORT usPixelClock;      // in 10KHz; for bios convenient
-  ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
-  UCHAR ucAction;                                       
-  UCHAR ucEncoderMode;
-                            // =0: DP   encoder      
-                            // =1: LVDS encoder          
-                            // =2: DVI  encoder  
-                            // =3: HDMI encoder
-                            // =4: SDVO encoder
-  UCHAR ucLaneNum;          // how many lanes to enable
-  UCHAR ucStatus;           // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
-  UCHAR ucReserved;
-}DIG_ENCODER_CONTROL_PARAMETERS_V2;
-
-//ucConfig
-#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK				0x01
-#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ		  0x00
-#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ		  0x01
-#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK				  0x04
-#define ATOM_ENCODER_CONFIG_V2_LINKA								  0x00
-#define ATOM_ENCODER_CONFIG_V2_LINKB								  0x04
-#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK	  0x18
-#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1				    0x00
-#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2				    0x08
-#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3				    0x10
-
-// ucAction:
-// ATOM_DISABLE
-// ATOM_ENABLE
-#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       0x08
-#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    0x09
-#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    0x0a
-#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3    0x13
-#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    0x0b
-#define ATOM_ENCODER_CMD_DP_VIDEO_OFF                 0x0c
-#define ATOM_ENCODER_CMD_DP_VIDEO_ON                  0x0d
-#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS    0x0e
-#define ATOM_ENCODER_CMD_SETUP                        0x0f
-#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE             0x10
-
-// ucStatus
-#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE    0x10
-#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE  0x00
-
-//ucTableFormatRevision=1
-//ucTableContentRevision=3
-// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
-typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
-{
-#if ATOM_BIG_ENDIAN
-    UCHAR ucReserved1:1;
-    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
-    UCHAR ucReserved:3;
-    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
-#else
-    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
-    UCHAR ucReserved:3;
-    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
-    UCHAR ucReserved1:1;
-#endif
-}ATOM_DIG_ENCODER_CONFIG_V3;
-
-#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK				0x03
-#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ		  0x00
-#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ		  0x01
-#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL					  0x70
-#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER					  0x00
-#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER					  0x10
-#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER					  0x20
-#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER					  0x30
-#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER					  0x40
-#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER					  0x50
-
-typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
-{
-  USHORT usPixelClock;      // in 10KHz; for bios convenient
-  ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
-  UCHAR ucAction;                              
-  union {
-    UCHAR ucEncoderMode;
-                            // =0: DP   encoder      
-                            // =1: LVDS encoder          
-                            // =2: DVI  encoder  
-                            // =3: HDMI encoder
-                            // =4: SDVO encoder
-                            // =5: DP audio
-    UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
-	                    // =0:     external DP
-	                    // =1:     internal DP2
-	                    // =0x11:  internal DP1 for NutMeg/Travis DP translator
-  };
-  UCHAR ucLaneNum;          // how many lanes to enable
-  UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
-  UCHAR ucReserved;
-}DIG_ENCODER_CONTROL_PARAMETERS_V3;
-
-//ucTableFormatRevision=1
-//ucTableContentRevision=4
-// start from NI           
-// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
-typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
-{
-#if ATOM_BIG_ENDIAN
-    UCHAR ucReserved1:1;
-    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
-    UCHAR ucReserved:2;
-    UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
-#else
-    UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
-    UCHAR ucReserved:2;
-    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
-    UCHAR ucReserved1:1;
-#endif
-}ATOM_DIG_ENCODER_CONFIG_V4;
-
-#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK				0x03
-#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ		  0x00
-#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ		  0x01
-#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ		  0x02
-#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ		  0x03
-#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL					  0x70
-#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER					  0x00
-#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER					  0x10
-#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER					  0x20
-#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER					  0x30
-#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER					  0x40
-#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER					  0x50
-#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER					  0x60
-
-typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
-{
-  USHORT usPixelClock;      // in 10KHz; for bios convenient
-  union{
-  ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
-  UCHAR ucConfig;
-  };
-  UCHAR ucAction;                              
-  union {
-    UCHAR ucEncoderMode;
-                            // =0: DP   encoder      
-                            // =1: LVDS encoder          
-                            // =2: DVI  encoder  
-                            // =3: HDMI encoder
-                            // =4: SDVO encoder
-                            // =5: DP audio
-    UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
-	                    // =0:     external DP
-	                    // =1:     internal DP2
-	                    // =0x11:  internal DP1 for NutMeg/Travis DP translator
-  };
-  UCHAR ucLaneNum;          // how many lanes to enable
-  UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
-  UCHAR ucHPD_ID;           // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
-}DIG_ENCODER_CONTROL_PARAMETERS_V4;
-
-// define ucBitPerColor: 
-#define PANEL_BPC_UNDEFINE                               0x00
-#define PANEL_6BIT_PER_COLOR                             0x01 
-#define PANEL_8BIT_PER_COLOR                             0x02
-#define PANEL_10BIT_PER_COLOR                            0x03
-#define PANEL_12BIT_PER_COLOR                            0x04
-#define PANEL_16BIT_PER_COLOR                            0x05
-
-//define ucPanelMode
-#define DP_PANEL_MODE_EXTERNAL_DP_MODE                   0x00
-#define DP_PANEL_MODE_INTERNAL_DP2_MODE                  0x01
-#define DP_PANEL_MODE_INTERNAL_DP1_MODE                  0x11
-
-/****************************************************************************/	
-// Structures used by UNIPHYTransmitterControlTable
-//                    LVTMATransmitterControlTable
-//                    DVOOutputControlTable
-/****************************************************************************/	
-typedef struct _ATOM_DP_VS_MODE
-{
-  UCHAR ucLaneSel;
-  UCHAR ucLaneSet;
-}ATOM_DP_VS_MODE;
-
-typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
-{
-	union
-	{
-  USHORT usPixelClock;		// in 10KHz; for bios convenient
-	USHORT usInitInfo;			// when init uniphy,lower 8bit is used for connector type defined in objectid.h
-  ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
-	};
-  UCHAR ucConfig;
-													// [0]=0: 4 lane Link,      
-													//    =1: 8 lane Link ( Dual Links TMDS ) 
-                          // [1]=0: InCoherent mode   
-													//    =1: Coherent Mode										
-													// [2] Link Select:
-  												// =0: PHY linkA   if bfLane<3
-													// =1: PHY linkB   if bfLanes<3
-		  										// =0: PHY linkA+B if bfLanes=3		
-                          // [5:4]PCIE lane Sel
-                          // =0: lane 0~3 or 0~7
-                          // =1: lane 4~7
-                          // =2: lane 8~11 or 8~15
-                          // =3: lane 12~15 
-	UCHAR ucAction;				  // =0: turn off encoder					
-	                        // =1: turn on encoder			
-  UCHAR ucReserved[4];
-}DIG_TRANSMITTER_CONTROL_PARAMETERS;
-
-#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION		DIG_TRANSMITTER_CONTROL_PARAMETERS					
-
-//ucInitInfo
-#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK	0x00ff			
-
-//ucConfig 
-#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK			0x01
-#define ATOM_TRANSMITTER_CONFIG_COHERENT				0x02
-#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK		0x04
-#define ATOM_TRANSMITTER_CONFIG_LINKA						0x00
-#define ATOM_TRANSMITTER_CONFIG_LINKB						0x04
-#define ATOM_TRANSMITTER_CONFIG_LINKA_B					0x00			
-#define ATOM_TRANSMITTER_CONFIG_LINKB_A					0x04
-
-#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK	0x08			// only used when ATOM_TRANSMITTER_ACTION_ENABLE
-#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER		0x00				// only used when ATOM_TRANSMITTER_ACTION_ENABLE
-#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER		0x08				// only used when ATOM_TRANSMITTER_ACTION_ENABLE
-
-#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK			0x30
-#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL			0x00
-#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE			0x20
-#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN		0x30
-#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK		0xc0
-#define ATOM_TRANSMITTER_CONFIG_LANE_0_3				0x00
-#define ATOM_TRANSMITTER_CONFIG_LANE_0_7				0x00
-#define ATOM_TRANSMITTER_CONFIG_LANE_4_7				0x40
-#define ATOM_TRANSMITTER_CONFIG_LANE_8_11				0x80
-#define ATOM_TRANSMITTER_CONFIG_LANE_8_15				0x80
-#define ATOM_TRANSMITTER_CONFIG_LANE_12_15			0xc0
-
-//ucAction
-#define ATOM_TRANSMITTER_ACTION_DISABLE					       0
-#define ATOM_TRANSMITTER_ACTION_ENABLE					       1
-#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF				       2
-#define ATOM_TRANSMITTER_ACTION_LCD_BLON				       3
-#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4
-#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START		 5
-#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP			 6
-#define ATOM_TRANSMITTER_ACTION_INIT						       7
-#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT	       8
-#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT		       9
-#define ATOM_TRANSMITTER_ACTION_SETUP						       10
-#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11
-#define ATOM_TRANSMITTER_ACTION_POWER_ON               12
-#define ATOM_TRANSMITTER_ACTION_POWER_OFF              13
-
-// Following are used for DigTransmitterControlTable ver1.2
-typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
-{
-#if ATOM_BIG_ENDIAN
-  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
-                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
-                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
-  UCHAR ucReserved:1;               
-  UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
-  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
-  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
-                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
-
-  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
-  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
-#else
-  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
-  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
-  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
-                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
-  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
-  UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
-  UCHAR ucReserved:1;               
-  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
-                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
-                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
-#endif
-}ATOM_DIG_TRANSMITTER_CONFIG_V2;
-
-//ucConfig 
-//Bit0
-#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR			0x01
-
-//Bit1
-#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT				          0x02
-
-//Bit2
-#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK		        0x04
-#define ATOM_TRANSMITTER_CONFIG_V2_LINKA  			            0x00
-#define ATOM_TRANSMITTER_CONFIG_V2_LINKB				            0x04
-
-// Bit3
-#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK	        0x08
-#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER		          0x00				// only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
-#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER		          0x08				// only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
-
-// Bit4
-#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR			        0x10
-
-// Bit7:6
-#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK     0xC0
-#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1           	0x00	//AB
-#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2           	0x40	//CD
-#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3           	0x80	//EF
-
-typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
-{
-	union
-	{
-  USHORT usPixelClock;		// in 10KHz; for bios convenient
-	USHORT usInitInfo;			// when init uniphy,lower 8bit is used for connector type defined in objectid.h
-  ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
-	};
-  ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
-	UCHAR ucAction;				  // define as ATOM_TRANSMITER_ACTION_XXX
-  UCHAR ucReserved[4];
-}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
-
-typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
-{
-#if ATOM_BIG_ENDIAN
-  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
-                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
-                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
-  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
-  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
-  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
-                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
-  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
-  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
-#else
-  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
-  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
-  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
-                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
-  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
-  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
-  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
-                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
-                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
-#endif
-}ATOM_DIG_TRANSMITTER_CONFIG_V3;
-
-
-typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
-{
-	union
-	{
-    USHORT usPixelClock;		// in 10KHz; for bios convenient
-	  USHORT usInitInfo;			// when init uniphy,lower 8bit is used for connector type defined in objectid.h
-    ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
-	};
-  ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
-	UCHAR ucAction;				    // define as ATOM_TRANSMITER_ACTION_XXX
-  UCHAR ucLaneNum;
-  UCHAR ucReserved[3];
-}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
-
-//ucConfig 
-//Bit0
-#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR			0x01
-
-//Bit1
-#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT				          0x02
-
-//Bit2
-#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK		        0x04
-#define ATOM_TRANSMITTER_CONFIG_V3_LINKA  			            0x00
-#define ATOM_TRANSMITTER_CONFIG_V3_LINKB				            0x04
-
-// Bit3
-#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK	        0x08
-#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER		          0x00
-#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER		          0x08
-
-// Bit5:4
-#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 	        0x30
-#define ATOM_TRASMITTER_CONFIG_V3_P1PLL          		        0x00
-#define ATOM_TRASMITTER_CONFIG_V3_P2PLL		                  0x10
-#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT            0x20
-
-// Bit7:6
-#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK     0xC0
-#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1           	0x00	//AB
-#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2           	0x40	//CD
-#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3           	0x80	//EF
-
-
-/****************************************************************************/	
-// Structures used by UNIPHYTransmitterControlTable V1.4
-// ASIC Families: NI
-// ucTableFormatRevision=1
-// ucTableContentRevision=4
-/****************************************************************************/	
-typedef struct _ATOM_DP_VS_MODE_V4
-{
-  UCHAR ucLaneSel;
- 	union
- 	{  
- 	  UCHAR ucLaneSet;
- 	  struct {
-#if ATOM_BIG_ENDIAN
- 		  UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
- 		  UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
- 		  UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
-#else
- 		  UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
- 		  UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
- 		  UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
-#endif
- 		};
- 	}; 
-}ATOM_DP_VS_MODE_V4;
- 
-typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
-{
-#if ATOM_BIG_ENDIAN
-  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
-                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
-                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
-  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
-  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
-  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
-                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
-  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
-  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
-#else
-  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
-  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
-  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
-                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
-  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
-  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
-  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
-                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
-                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
-#endif
-}ATOM_DIG_TRANSMITTER_CONFIG_V4;
-
-typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
-{
-  union
-  {
-    USHORT usPixelClock;		// in 10KHz; for bios convenient
-    USHORT usInitInfo;			// when init uniphy,lower 8bit is used for connector type defined in objectid.h
-    ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode     Redefined comparing to previous version
-  };
-  union
-  {
-  ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
-  UCHAR ucConfig;
-  };
-  UCHAR ucAction;				    // define as ATOM_TRANSMITER_ACTION_XXX	                        
-  UCHAR ucLaneNum;
-  UCHAR ucReserved[3];
-}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
-
-//ucConfig 
-//Bit0
-#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR			0x01
-//Bit1
-#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT				          0x02
-//Bit2
-#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK		        0x04
-#define ATOM_TRANSMITTER_CONFIG_V4_LINKA  			            0x00			
-#define ATOM_TRANSMITTER_CONFIG_V4_LINKB				            0x04
-// Bit3
-#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK	        0x08
-#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER		          0x00				 
-#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER		          0x08				
-// Bit5:4
-#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 	        0x30
-#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL         		        0x00
-#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL		                0x10
-#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL		                0x20   // New in _V4
-#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT           0x30   // Changed comparing to V3
-// Bit7:6
-#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK     0xC0
-#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1           	0x00	//AB
-#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2           	0x40	//CD
-#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3           	0x80	//EF
-
-
-typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
-{
-#if ATOM_BIG_ENDIAN
-  UCHAR ucReservd1:1;
-  UCHAR ucHPDSel:3;
-  UCHAR ucPhyClkSrcId:2;            
-  UCHAR ucCoherentMode:1;            
-  UCHAR ucReserved:1;
-#else
-  UCHAR ucReserved:1;
-  UCHAR ucCoherentMode:1;            
-  UCHAR ucPhyClkSrcId:2;            
-  UCHAR ucHPDSel:3;
-  UCHAR ucReservd1:1;
-#endif
-}ATOM_DIG_TRANSMITTER_CONFIG_V5;
-
-typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
-{
-  USHORT usSymClock;		        // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock,  (HDMI deep color), =pixel clock * deep_color_ratio
-  UCHAR  ucPhyId;                   // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
-  UCHAR  ucAction;				    // define as ATOM_TRANSMITER_ACTION_xxx
-  UCHAR  ucLaneNum;                 // indicate lane number 1-8
-  UCHAR  ucConnObjId;               // Connector Object Id defined in ObjectId.h
-  UCHAR  ucDigMode;                 // indicate DIG mode
-  union{
-  ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
-  UCHAR ucConfig;
-  };
-  UCHAR  ucDigEncoderSel;           // indicate DIG front end encoder 
-  UCHAR  ucDPLaneSet;
-  UCHAR  ucReserved;
-  UCHAR  ucReserved1;
-}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
-
-//ucPhyId
-#define ATOM_PHY_ID_UNIPHYA                                 0  
-#define ATOM_PHY_ID_UNIPHYB                                 1
-#define ATOM_PHY_ID_UNIPHYC                                 2
-#define ATOM_PHY_ID_UNIPHYD                                 3
-#define ATOM_PHY_ID_UNIPHYE                                 4
-#define ATOM_PHY_ID_UNIPHYF                                 5
-#define ATOM_PHY_ID_UNIPHYG                                 6
-
-// ucDigEncoderSel
-#define ATOM_TRANMSITTER_V5__DIGA_SEL                       0x01
-#define ATOM_TRANMSITTER_V5__DIGB_SEL                       0x02
-#define ATOM_TRANMSITTER_V5__DIGC_SEL                       0x04
-#define ATOM_TRANMSITTER_V5__DIGD_SEL                       0x08
-#define ATOM_TRANMSITTER_V5__DIGE_SEL                       0x10
-#define ATOM_TRANMSITTER_V5__DIGF_SEL                       0x20
-#define ATOM_TRANMSITTER_V5__DIGG_SEL                       0x40
-
-// ucDigMode
-#define ATOM_TRANSMITTER_DIGMODE_V5_DP                      0
-#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS                    1
-#define ATOM_TRANSMITTER_DIGMODE_V5_DVI                     2
-#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI                    3
-#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO                    4
-#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST                  5
-
-// ucDPLaneSet
-#define DP_LANE_SET__0DB_0_4V                               0x00
-#define DP_LANE_SET__0DB_0_6V                               0x01
-#define DP_LANE_SET__0DB_0_8V                               0x02
-#define DP_LANE_SET__0DB_1_2V                               0x03
-#define DP_LANE_SET__3_5DB_0_4V                             0x08  
-#define DP_LANE_SET__3_5DB_0_6V                             0x09
-#define DP_LANE_SET__3_5DB_0_8V                             0x0a
-#define DP_LANE_SET__6DB_0_4V                               0x10
-#define DP_LANE_SET__6DB_0_6V                               0x11
-#define DP_LANE_SET__9_5DB_0_4V                             0x18  
-
-// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
-// Bit1
-#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT				          0x02
-
-// Bit3:2
-#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 	        0x0c
-#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT		    0x02
-
-#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL         		        0x00
-#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL		                0x04
-#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL		                0x08   
-#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT           0x0c
-// Bit6:4
-#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK		          0x70
-#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT		      0x04
-
-#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL				        0x00
-#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL				          0x10
-#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL				          0x20
-#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL				          0x30
-#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL				          0x40
-#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL				          0x50
-#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL				          0x60
-
-#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5            DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
-
-
-/****************************************************************************/	
-// Structures used by ExternalEncoderControlTable V1.3
-// ASIC Families: Evergreen, Llano, NI
-// ucTableFormatRevision=1
-// ucTableContentRevision=3
-/****************************************************************************/	
-
-typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
-{
-  union{
-  USHORT usPixelClock;      // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 
-  USHORT usConnectorId;     // connector id, valid when ucAction = INIT
-  };
-  UCHAR  ucConfig;          // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT  
-  UCHAR  ucAction;          // 
-  UCHAR  ucEncoderMode;     // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
-  UCHAR  ucLaneNum;         // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT  
-  UCHAR  ucBitPerColor;     // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
-  UCHAR  ucReserved;        
-}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
-
-// ucAction
-#define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT         0x00
-#define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT          0x01
-#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT           0x07
-#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP          0x0f
-#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF   0x10
-#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING       0x11
-#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION      0x12
-#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP              0x14
-
-// ucConfig
-#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK				0x03
-#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ		  0x00
-#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ		  0x01
-#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ		  0x02
-#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK		    0x70
-#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1		            0x00
-#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2		            0x10
-#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3		            0x20
-
-typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
-{
-  EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
-  ULONG ulReserved[2];
-}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
-
-
-/****************************************************************************/	
-// Structures used by DAC1OuputControlTable
-//                    DAC2OuputControlTable
-//                    LVTMAOutputControlTable  (Before DEC30)
-//                    TMDSAOutputControlTable  (Before DEC30)
-/****************************************************************************/	
-typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-{
-  UCHAR  ucAction;                    // Possible input:ATOM_ENABLE||ATOMDISABLE
-                                      // When the display is LCD, in addition to above:
-                                      // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
-                                      // ATOM_LCD_SELFTEST_STOP
-                                      
-  UCHAR  aucPadding[3];               // padding to DWORD aligned
-}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
-
-#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-
-
-#define CRT1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 
-#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define CRT2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 
-#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define CV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define TV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define DFP1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define DFP2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define LCD1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define DVO_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
-#define DVO_OUTPUT_CONTROL_PARAMETERS_V3	 DIG_TRANSMITTER_CONTROL_PARAMETERS
-
-/****************************************************************************/	
-// Structures used by BlankCRTCTable
-/****************************************************************************/	
-typedef struct _BLANK_CRTC_PARAMETERS
-{
-  UCHAR  ucCRTC;                    	// ATOM_CRTC1 or ATOM_CRTC2
-  UCHAR  ucBlanking;                  // ATOM_BLANKING or ATOM_BLANKINGOFF
-  USHORT usBlackColorRCr;
-  USHORT usBlackColorGY;
-  USHORT usBlackColorBCb;
-}BLANK_CRTC_PARAMETERS;
-#define BLANK_CRTC_PS_ALLOCATION    BLANK_CRTC_PARAMETERS
-
-/****************************************************************************/	
-// Structures used by EnableCRTCTable
-//                    EnableCRTCMemReqTable
-//                    UpdateCRTC_DoubleBufferRegistersTable
-/****************************************************************************/	
-typedef struct _ENABLE_CRTC_PARAMETERS
-{
-  UCHAR ucCRTC;                    	  // ATOM_CRTC1 or ATOM_CRTC2
-  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE 
-  UCHAR ucPadding[2];
-}ENABLE_CRTC_PARAMETERS;
-#define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS
-
-/****************************************************************************/	
-// Structures used by SetCRTC_OverScanTable
-/****************************************************************************/	
-typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
-{
-  USHORT usOverscanRight;             // right
-  USHORT usOverscanLeft;              // left
-  USHORT usOverscanBottom;            // bottom
-  USHORT usOverscanTop;               // top
-  UCHAR  ucCRTC;                      // ATOM_CRTC1 or ATOM_CRTC2
-  UCHAR  ucPadding[3];
-}SET_CRTC_OVERSCAN_PARAMETERS;
-#define SET_CRTC_OVERSCAN_PS_ALLOCATION  SET_CRTC_OVERSCAN_PARAMETERS
-
-/****************************************************************************/	
-// Structures used by SetCRTC_ReplicationTable
-/****************************************************************************/	
-typedef struct _SET_CRTC_REPLICATION_PARAMETERS
-{
-  UCHAR ucH_Replication;              // horizontal replication
-  UCHAR ucV_Replication;              // vertical replication
-  UCHAR usCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
-  UCHAR ucPadding;
-}SET_CRTC_REPLICATION_PARAMETERS;
-#define SET_CRTC_REPLICATION_PS_ALLOCATION  SET_CRTC_REPLICATION_PARAMETERS
-
-/****************************************************************************/	
-// Structures used by SelectCRTC_SourceTable
-/****************************************************************************/	
-typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
-{
-  UCHAR ucCRTC;                    	  // ATOM_CRTC1 or ATOM_CRTC2
-  UCHAR ucDevice;                     // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
-  UCHAR ucPadding[2];
-}SELECT_CRTC_SOURCE_PARAMETERS;
-#define SELECT_CRTC_SOURCE_PS_ALLOCATION  SELECT_CRTC_SOURCE_PARAMETERS
-
-typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
-{
-  UCHAR ucCRTC;                    	  // ATOM_CRTC1 or ATOM_CRTC2
-  UCHAR ucEncoderID;                  // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
-  UCHAR ucEncodeMode;									// Encoding mode, only valid when using DIG1/DIG2/DVO
-  UCHAR ucPadding;
-}SELECT_CRTC_SOURCE_PARAMETERS_V2;
-
-//ucEncoderID
-//#define ASIC_INT_DAC1_ENCODER_ID    						0x00 
-//#define ASIC_INT_TV_ENCODER_ID									0x02
-//#define ASIC_INT_DIG1_ENCODER_ID								0x03
-//#define ASIC_INT_DAC2_ENCODER_ID								0x04
-//#define ASIC_EXT_TV_ENCODER_ID									0x06
-//#define ASIC_INT_DVO_ENCODER_ID									0x07
-//#define ASIC_INT_DIG2_ENCODER_ID								0x09
-//#define ASIC_EXT_DIG_ENCODER_ID									0x05
-
-//ucEncodeMode
-//#define ATOM_ENCODER_MODE_DP										0
-//#define ATOM_ENCODER_MODE_LVDS									1
-//#define ATOM_ENCODER_MODE_DVI										2
-//#define ATOM_ENCODER_MODE_HDMI									3
-//#define ATOM_ENCODER_MODE_SDVO									4
-//#define ATOM_ENCODER_MODE_TV										13
-//#define ATOM_ENCODER_MODE_CV										14
-//#define ATOM_ENCODER_MODE_CRT										15
-
-/****************************************************************************/	
-// Structures used by SetPixelClockTable
-//                    GetPixelClockTable 
-/****************************************************************************/	
-//Major revision=1., Minor revision=1
-typedef struct _PIXEL_CLOCK_PARAMETERS
-{
-  USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
-                                      // 0 means disable PPLL
-  USHORT usRefDiv;                    // Reference divider
-  USHORT usFbDiv;                     // feedback divider
-  UCHAR  ucPostDiv;                   // post divider	
-  UCHAR  ucFracFbDiv;                 // fractional feedback divider
-  UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
-  UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
-  UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
-  UCHAR  ucPadding;
-}PIXEL_CLOCK_PARAMETERS;
-
-//Major revision=1., Minor revision=2, add ucMiscIfno
-//ucMiscInfo:
-#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
-#define MISC_DEVICE_INDEX_MASK        0xF0
-#define MISC_DEVICE_INDEX_SHIFT       4
-
-typedef struct _PIXEL_CLOCK_PARAMETERS_V2
-{
-  USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
-                                      // 0 means disable PPLL
-  USHORT usRefDiv;                    // Reference divider
-  USHORT usFbDiv;                     // feedback divider
-  UCHAR  ucPostDiv;                   // post divider	
-  UCHAR  ucFracFbDiv;                 // fractional feedback divider
-  UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
-  UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
-  UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
-  UCHAR  ucMiscInfo;                  // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
-}PIXEL_CLOCK_PARAMETERS_V2;
-
-//Major revision=1., Minor revision=3, structure/definition change
-//ucEncoderMode:
-//ATOM_ENCODER_MODE_DP
-//ATOM_ENOCDER_MODE_LVDS
-//ATOM_ENOCDER_MODE_DVI
-//ATOM_ENOCDER_MODE_HDMI
-//ATOM_ENOCDER_MODE_SDVO
-//ATOM_ENCODER_MODE_TV										13
-//ATOM_ENCODER_MODE_CV										14
-//ATOM_ENCODER_MODE_CRT										15
-
-//ucDVOConfig
-//#define DVO_ENCODER_CONFIG_RATE_SEL							0x01
-//#define DVO_ENCODER_CONFIG_DDR_SPEED						0x00
-//#define DVO_ENCODER_CONFIG_SDR_SPEED						0x01
-//#define DVO_ENCODER_CONFIG_OUTPUT_SEL						0x0c
-//#define DVO_ENCODER_CONFIG_LOW12BIT							0x00
-//#define DVO_ENCODER_CONFIG_UPPER12BIT						0x04
-//#define DVO_ENCODER_CONFIG_24BIT								0x08
-
-//ucMiscInfo: also changed, see below
-#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL						0x01
-#define PIXEL_CLOCK_MISC_VGA_MODE										0x02
-#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK							0x04
-#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1							0x00
-#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2							0x04
-#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK			0x08
-#define PIXEL_CLOCK_MISC_REF_DIV_SRC                    0x10
-// V1.4 for RoadRunner
-#define PIXEL_CLOCK_V4_MISC_SS_ENABLE               0x10
-#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE           0x20
-
-
-typedef struct _PIXEL_CLOCK_PARAMETERS_V3
-{
-  USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
-                                      // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
-  USHORT usRefDiv;                    // Reference divider
-  USHORT usFbDiv;                     // feedback divider
-  UCHAR  ucPostDiv;                   // post divider	
-  UCHAR  ucFracFbDiv;                 // fractional feedback divider
-  UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
-  UCHAR  ucTransmitterId;             // graphic encoder id defined in objectId.h
-	union
-	{
-  UCHAR  ucEncoderMode;               // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
-	UCHAR  ucDVOConfig;									// when use DVO, need to know SDR/DDR, 12bit or 24bit
-	};
-  UCHAR  ucMiscInfo;                  // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
-                                      // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
-                                      // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
-}PIXEL_CLOCK_PARAMETERS_V3;
-
-#define PIXEL_CLOCK_PARAMETERS_LAST			PIXEL_CLOCK_PARAMETERS_V2
-#define GET_PIXEL_CLOCK_PS_ALLOCATION		PIXEL_CLOCK_PARAMETERS_LAST
-
-typedef struct _PIXEL_CLOCK_PARAMETERS_V5
-{
-  UCHAR  ucCRTC;             // ATOM_CRTC1~6, indicate the CRTC controller to 
-                             // drive the pixel clock. not used for DCPLL case.
-  union{
-  UCHAR  ucReserved;
-  UCHAR  ucFracFbDiv;        // [gphan] temporary to prevent build problem.  remove it after driver code is changed.
-  };
-  USHORT usPixelClock;       // target the pixel clock to drive the CRTC timing
-                             // 0 means disable PPLL/DCPLL. 
-  USHORT usFbDiv;            // feedback divider integer part. 
-  UCHAR  ucPostDiv;          // post divider. 
-  UCHAR  ucRefDiv;           // Reference divider
-  UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
-  UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h, 
-                             // indicate which graphic encoder will be used. 
-  UCHAR  ucEncoderMode;      // Encoder mode: 
-  UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL 
-                             // bit[1]= when VGA timing is used. 
-                             // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
-                             // bit[4]= RefClock source for PPLL. 
-                             // =0: XTLAIN( default mode )
-	                           // =1: other external clock source, which is pre-defined
-                             //     by VBIOS depend on the feature required.
-                             // bit[7:5]: reserved.
-  ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
-
-}PIXEL_CLOCK_PARAMETERS_V5;
-
-#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL					0x01
-#define PIXEL_CLOCK_V5_MISC_VGA_MODE								0x02
-#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK           0x0c
-#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP              0x00
-#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP              0x04
-#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP              0x08
-#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC             0x10
-
-typedef struct _CRTC_PIXEL_CLOCK_FREQ
-{
-#if ATOM_BIG_ENDIAN
-  ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to 
-                              // drive the pixel clock. not used for DCPLL case.
-  ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing. 
-                              // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
-#else
-  ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing. 
-                              // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
-  ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to 
-                              // drive the pixel clock. not used for DCPLL case.
-#endif
-}CRTC_PIXEL_CLOCK_FREQ;
-
-typedef struct _PIXEL_CLOCK_PARAMETERS_V6
-{
-  union{
-    CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;    // pixel clock and CRTC id frequency 
-    ULONG ulDispEngClkFreq;                  // dispclk frequency
-  };
-  USHORT usFbDiv;            // feedback divider integer part. 
-  UCHAR  ucPostDiv;          // post divider. 
-  UCHAR  ucRefDiv;           // Reference divider
-  UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
-  UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h, 
-                             // indicate which graphic encoder will be used. 
-  UCHAR  ucEncoderMode;      // Encoder mode: 
-  UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL 
-                             // bit[1]= when VGA timing is used. 
-                             // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
-                             // bit[4]= RefClock source for PPLL. 
-                             // =0: XTLAIN( default mode )
-	                           // =1: other external clock source, which is pre-defined                                            
-                             //     by VBIOS depend on the feature required.
-                             // bit[7:5]: reserved.
-  ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
-
-}PIXEL_CLOCK_PARAMETERS_V6;
-
-#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL					0x01
-#define PIXEL_CLOCK_V6_MISC_VGA_MODE								0x02
-#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK           0x0c
-#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP              0x00
-#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP              0x04
-#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6           0x08    //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
-#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP              0x08
-#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6           0x04    //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
-#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP              0x0c
-#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC             0x10
-#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK            0x40
-
-typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
-{
-  PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
-}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
-
-typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
-{
-  UCHAR  ucStatus;
-  UCHAR  ucRefDivSrc;                 // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
-  UCHAR  ucReserved[2];
-}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
-
-typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
-{
-  PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
-}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
-
-/****************************************************************************/	
-// Structures used by AdjustDisplayPllTable
-/****************************************************************************/	
-typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
-{
-	USHORT usPixelClock;
-	UCHAR ucTransmitterID;
-	UCHAR ucEncodeMode;
-	union
-	{
-		UCHAR ucDVOConfig;									//if DVO, need passing link rate and output 12bitlow or 24bit
-		UCHAR ucConfig;											//if none DVO, not defined yet
-	};
-	UCHAR ucReserved[3];
-}ADJUST_DISPLAY_PLL_PARAMETERS;
-
-#define ADJUST_DISPLAY_CONFIG_SS_ENABLE       0x10
-#define ADJUST_DISPLAY_PLL_PS_ALLOCATION			ADJUST_DISPLAY_PLL_PARAMETERS
-
-typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
-{
-	USHORT usPixelClock;                    // target pixel clock
-	UCHAR ucTransmitterID;                  // GPU transmitter id defined in objectid.h
-	UCHAR ucEncodeMode;                     // encoder mode: CRT, LVDS, DP, TMDS or HDMI
-  UCHAR ucDispPllConfig;                 // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
-  UCHAR ucExtTransmitterID;               // external encoder id.
-	UCHAR ucReserved[2];
-}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
-
-// usDispPllConfig v1.2 for RoadRunner
-#define DISPPLL_CONFIG_DVO_RATE_SEL                0x0001     // need only when ucTransmitterID = DVO
-#define DISPPLL_CONFIG_DVO_DDR_SPEED               0x0000     // need only when ucTransmitterID = DVO
-#define DISPPLL_CONFIG_DVO_SDR_SPEED               0x0001     // need only when ucTransmitterID = DVO
-#define DISPPLL_CONFIG_DVO_OUTPUT_SEL              0x000c     // need only when ucTransmitterID = DVO
-#define DISPPLL_CONFIG_DVO_LOW12BIT                0x0000     // need only when ucTransmitterID = DVO
-#define DISPPLL_CONFIG_DVO_UPPER12BIT              0x0004     // need only when ucTransmitterID = DVO
-#define DISPPLL_CONFIG_DVO_24BIT                   0x0008     // need only when ucTransmitterID = DVO
-#define DISPPLL_CONFIG_SS_ENABLE                   0x0010     // Only used when ucEncoderMode = DP or LVDS
-#define DISPPLL_CONFIG_COHERENT_MODE               0x0020     // Only used when ucEncoderMode = TMDS or HDMI
-#define DISPPLL_CONFIG_DUAL_LINK                   0x0040     // Only used when ucEncoderMode = TMDS or LVDS
-
-
-typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
-{
-  ULONG ulDispPllFreq;                 // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
-  UCHAR ucRefDiv;                      // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
-  UCHAR ucPostDiv;                     // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
-  UCHAR ucReserved[2];  
-}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
-
-typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
-{
-  union 
-  {
-    ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3  sInput;
-    ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
-  };
-} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
-
-/****************************************************************************/	
-// Structures used by EnableYUVTable
-/****************************************************************************/	
-typedef struct _ENABLE_YUV_PARAMETERS
-{
-  UCHAR ucEnable;                     // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
-  UCHAR ucCRTC;                       // Which CRTC needs this YUV or RGB format
-  UCHAR ucPadding[2];
-}ENABLE_YUV_PARAMETERS;
-#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
-
-/****************************************************************************/	
-// Structures used by GetMemoryClockTable
-/****************************************************************************/	
-typedef struct _GET_MEMORY_CLOCK_PARAMETERS
-{
-  ULONG ulReturnMemoryClock;          // current memory speed in 10KHz unit
-} GET_MEMORY_CLOCK_PARAMETERS;
-#define GET_MEMORY_CLOCK_PS_ALLOCATION  GET_MEMORY_CLOCK_PARAMETERS
-
-/****************************************************************************/	
-// Structures used by GetEngineClockTable
-/****************************************************************************/	
-typedef struct _GET_ENGINE_CLOCK_PARAMETERS
-{
-  ULONG ulReturnEngineClock;          // current engine speed in 10KHz unit
-} GET_ENGINE_CLOCK_PARAMETERS;
-#define GET_ENGINE_CLOCK_PS_ALLOCATION  GET_ENGINE_CLOCK_PARAMETERS
-
-/****************************************************************************/	
-// Following Structures and constant may be obsolete
-/****************************************************************************/	
-//Maxium 8 bytes,the data read in will be placed in the parameter space.
-//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
-typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
-{
-  USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
-  USHORT    usVRAMAddress;      //Address in Frame Buffer where to pace raw EDID
-  USHORT    usStatus;           //When use output: lower byte EDID checksum, high byte hardware status
-                                //WHen use input:  lower byte as 'byte to read':currently limited to 128byte or 1byte
-  UCHAR     ucSlaveAddr;        //Read from which slave
-  UCHAR     ucLineNumber;       //Read from which HW assisted line
-}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
-#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION  READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
-
-
-#define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE                  0
-#define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES              1
-#define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK       2
-#define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK  3
-#define  ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK       4
-
-typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
-{
-  USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
-  USHORT    usByteOffset;       //Write to which byte
-                                //Upper portion of usByteOffset is Format of data 
-                                //1bytePS+offsetPS
-                                //2bytesPS+offsetPS
-                                //blockID+offsetPS
-                                //blockID+offsetID
-                                //blockID+counterID+offsetID
-  UCHAR     ucData;             //PS data1
-  UCHAR     ucStatus;           //Status byte 1=success, 2=failure, Also is used as PS data2
-  UCHAR     ucSlaveAddr;        //Write to which slave
-  UCHAR     ucLineNumber;       //Write from which HW assisted line
-}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
-
-#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION  WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
-
-typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
-{
-  USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
-  UCHAR     ucSlaveAddr;        //Write to which slave
-  UCHAR     ucLineNumber;       //Write from which HW assisted line
-}SET_UP_HW_I2C_DATA_PARAMETERS;
-
-
-/**************************************************************************/
-#define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
-
-
-/****************************************************************************/	
-// Structures used by PowerConnectorDetectionTable
-/****************************************************************************/	
-typedef struct	_POWER_CONNECTOR_DETECTION_PARAMETERS
-{
-  UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
-	UCHAR   ucPwrBehaviorId;							
-	USHORT	usPwrBudget;								 //how much power currently boot to in unit of watt
-}POWER_CONNECTOR_DETECTION_PARAMETERS;
-
-typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
-{                               
-  UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
-	UCHAR   ucReserved;
-	USHORT	usPwrBudget;								 //how much power currently boot to in unit of watt
-  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved;
-}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
-
-/****************************LVDS SS Command Table Definitions**********************/
-
-/****************************************************************************/	
-// Structures used by EnableSpreadSpectrumOnPPLLTable
-/****************************************************************************/	
-typedef struct	_ENABLE_LVDS_SS_PARAMETERS
-{
-  USHORT  usSpreadSpectrumPercentage;       
-  UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
-  UCHAR   ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
-  UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
-  UCHAR   ucPadding[3];
-}ENABLE_LVDS_SS_PARAMETERS;
-
-//ucTableFormatRevision=1,ucTableContentRevision=2
-typedef struct	_ENABLE_LVDS_SS_PARAMETERS_V2
-{
-  USHORT  usSpreadSpectrumPercentage;       
-  UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
-  UCHAR   ucSpreadSpectrumStep;           //
-  UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
-  UCHAR   ucSpreadSpectrumDelay;
-  UCHAR   ucSpreadSpectrumRange;
-  UCHAR   ucPadding;
-}ENABLE_LVDS_SS_PARAMETERS_V2;
-
-//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
-typedef struct	_ENABLE_SPREAD_SPECTRUM_ON_PPLL
-{
-  USHORT  usSpreadSpectrumPercentage;
-  UCHAR   ucSpreadSpectrumType;           // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
-  UCHAR   ucSpreadSpectrumStep;           //
-  UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
-  UCHAR   ucSpreadSpectrumDelay;
-  UCHAR   ucSpreadSpectrumRange;
-  UCHAR   ucPpll;												  // ATOM_PPLL1/ATOM_PPLL2
-}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
-
-typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
-{
-  USHORT  usSpreadSpectrumPercentage;
-  UCHAR   ucSpreadSpectrumType;	        // Bit[0]: 0-Down Spread,1-Center Spread. 
-                                        // Bit[1]: 1-Ext. 0-Int. 
-                                        // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
-                                        // Bits[7:4] reserved
-  UCHAR   ucEnable;	                    // ATOM_ENABLE or ATOM_DISABLE
-  USHORT  usSpreadSpectrumAmount;      	// Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]    
-  USHORT  usSpreadSpectrumStep;	        // SS_STEP_SIZE_DSFRAC
-}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
-
-#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD      0x00
-#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD    0x01
-#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD       0x02
-#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK    0x0c
-#define ATOM_PPLL_SS_TYPE_V2_P1PLL            0x00
-#define ATOM_PPLL_SS_TYPE_V2_P2PLL            0x04
-#define ATOM_PPLL_SS_TYPE_V2_DCPLL            0x08
-#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK     0x00FF
-#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT    0
-#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK     0x0F00
-#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT    8
-
-// Used by DCE5.0
- typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
-{
-  USHORT  usSpreadSpectrumAmountFrac;   // SS_AMOUNT_DSFRAC New in DCE5.0
-  UCHAR   ucSpreadSpectrumType;	        // Bit[0]: 0-Down Spread,1-Center Spread. 
-                                        // Bit[1]: 1-Ext. 0-Int. 
-                                        // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
-                                        // Bits[7:4] reserved
-  UCHAR   ucEnable;	                    // ATOM_ENABLE or ATOM_DISABLE
-  USHORT  usSpreadSpectrumAmount;      	// Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]    
-  USHORT  usSpreadSpectrumStep;	        // SS_STEP_SIZE_DSFRAC
-}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
-    
-#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD      0x00
-#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD    0x01
-#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD       0x02
-#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK    0x0c
-#define ATOM_PPLL_SS_TYPE_V3_P1PLL            0x00
-#define ATOM_PPLL_SS_TYPE_V3_P2PLL            0x04
-#define ATOM_PPLL_SS_TYPE_V3_DCPLL            0x08
-#define ATOM_PPLL_SS_TYPE_V3_P0PLL            ATOM_PPLL_SS_TYPE_V3_DCPLL
-#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK     0x00FF
-#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT    0
-#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK     0x0F00
-#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT    8
-
-#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION  ENABLE_SPREAD_SPECTRUM_ON_PPLL
-
-/**************************************************************************/
-
-typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
-{
-  PIXEL_CLOCK_PARAMETERS sPCLKInput;
-  ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 
-}SET_PIXEL_CLOCK_PS_ALLOCATION;
-
-#define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION
-
-/****************************************************************************/	
-// Structures used by ###
-/****************************************************************************/	
-typedef struct	_MEMORY_TRAINING_PARAMETERS
-{
-  ULONG ulTargetMemoryClock;          //In 10Khz unit
-}MEMORY_TRAINING_PARAMETERS;
-#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
-
-
-/****************************LVDS and other encoder command table definitions **********************/
-
-
-/****************************************************************************/	
-// Structures used by LVDSEncoderControlTable   (Before DCE30)
-//                    LVTMAEncoderControlTable  (Before DCE30)
-//                    TMDSAEncoderControlTable  (Before DCE30)
-/****************************************************************************/	
-typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
-{
-  USHORT usPixelClock;  // in 10KHz; for bios convenient
-  UCHAR  ucMisc;        // bit0=0: Enable single link
-                        //     =1: Enable dual link
-                        // Bit1=0: 666RGB
-                        //     =1: 888RGB
-  UCHAR  ucAction;      // 0: turn off encoder
-                        // 1: setup and turn on encoder
-}LVDS_ENCODER_CONTROL_PARAMETERS;
-
-#define LVDS_ENCODER_CONTROL_PS_ALLOCATION  LVDS_ENCODER_CONTROL_PARAMETERS
-   
-#define TMDS1_ENCODER_CONTROL_PARAMETERS    LVDS_ENCODER_CONTROL_PARAMETERS
-#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
-
-#define TMDS2_ENCODER_CONTROL_PARAMETERS    TMDS1_ENCODER_CONTROL_PARAMETERS
-#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
-
-
-//ucTableFormatRevision=1,ucTableContentRevision=2
-typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
-{
-  USHORT usPixelClock;  // in 10KHz; for bios convenient
-  UCHAR  ucMisc;        // see PANEL_ENCODER_MISC_xx defintions below
-  UCHAR  ucAction;      // 0: turn off encoder
-                        // 1: setup and turn on encoder
-  UCHAR  ucTruncate;    // bit0=0: Disable truncate
-                        //     =1: Enable truncate
-                        // bit4=0: 666RGB
-                        //     =1: 888RGB
-  UCHAR  ucSpatial;     // bit0=0: Disable spatial dithering
-                        //     =1: Enable spatial dithering
-                        // bit4=0: 666RGB
-                        //     =1: 888RGB
-  UCHAR  ucTemporal;    // bit0=0: Disable temporal dithering
-                        //     =1: Enable temporal dithering
-                        // bit4=0: 666RGB
-                        //     =1: 888RGB
-                        // bit5=0: Gray level 2
-                        //     =1: Gray level 4
-  UCHAR  ucFRC;         // bit4=0: 25FRC_SEL pattern E
-                        //     =1: 25FRC_SEL pattern F
-                        // bit6:5=0: 50FRC_SEL pattern A
-                        //       =1: 50FRC_SEL pattern B
-                        //       =2: 50FRC_SEL pattern C
-                        //       =3: 50FRC_SEL pattern D
-                        // bit7=0: 75FRC_SEL pattern E
-                        //     =1: 75FRC_SEL pattern F
-}LVDS_ENCODER_CONTROL_PARAMETERS_V2;
-
-#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
-   
-#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2    LVDS_ENCODER_CONTROL_PARAMETERS_V2
-#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
-  
-#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2    TMDS1_ENCODER_CONTROL_PARAMETERS_V2
-#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
-
-#define LVDS_ENCODER_CONTROL_PARAMETERS_V3     LVDS_ENCODER_CONTROL_PARAMETERS_V2
-#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3  LVDS_ENCODER_CONTROL_PARAMETERS_V3
-
-#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
-#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
-
-#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
-#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
-
-/****************************************************************************/	
-// Structures used by ###
-/****************************************************************************/	
-typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
-{                               
-  UCHAR    ucEnable;            // Enable or Disable External TMDS encoder
-  UCHAR    ucMisc;              // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
-  UCHAR    ucPadding[2];
-}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
-
-typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
-{                               
-  ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS    sXTmdsEncoder;
-  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION   sReserved;     //Caller doesn't need to init this portion
-}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
-
-#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
-
-typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
-{                               
-  ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2    sXTmdsEncoder;
-  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
-}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
-
-typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
-{
-  DIG_ENCODER_CONTROL_PARAMETERS            sDigEncoder;
-  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
-}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
-
-/****************************************************************************/	
-// Structures used by DVOEncoderControlTable
-/****************************************************************************/	
-//ucTableFormatRevision=1,ucTableContentRevision=3
-
-//ucDVOConfig:
-#define DVO_ENCODER_CONFIG_RATE_SEL							0x01
-#define DVO_ENCODER_CONFIG_DDR_SPEED						0x00
-#define DVO_ENCODER_CONFIG_SDR_SPEED						0x01
-#define DVO_ENCODER_CONFIG_OUTPUT_SEL						0x0c
-#define DVO_ENCODER_CONFIG_LOW12BIT							0x00
-#define DVO_ENCODER_CONFIG_UPPER12BIT						0x04
-#define DVO_ENCODER_CONFIG_24BIT								0x08
-
-typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
-{
-  USHORT usPixelClock; 
-  UCHAR  ucDVOConfig;
-  UCHAR  ucAction;														//ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
-  UCHAR  ucReseved[4];
-}DVO_ENCODER_CONTROL_PARAMETERS_V3;
-#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3	DVO_ENCODER_CONTROL_PARAMETERS_V3
-
-typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4
-{
-  USHORT usPixelClock; 
-  UCHAR  ucDVOConfig;
-  UCHAR  ucAction;														//ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
-  UCHAR  ucBitPerColor;                       //please refer to definition of PANEL_xBIT_PER_COLOR
-  UCHAR  ucReseved[3];
-}DVO_ENCODER_CONTROL_PARAMETERS_V1_4;
-#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4	DVO_ENCODER_CONTROL_PARAMETERS_V1_4
-
-
-//ucTableFormatRevision=1
-//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 
-// bit1=0: non-coherent mode
-//     =1: coherent mode
-
-//==========================================================================================
-//Only change is here next time when changing encoder parameter definitions again!
-#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST     LVDS_ENCODER_CONTROL_PARAMETERS_V3
-#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST  LVDS_ENCODER_CONTROL_PARAMETERS_LAST
-
-#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
-#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
-
-#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
-#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
-
-#define DVO_ENCODER_CONTROL_PARAMETERS_LAST      DVO_ENCODER_CONTROL_PARAMETERS
-#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION
-
-//==========================================================================================
-#define PANEL_ENCODER_MISC_DUAL                0x01
-#define PANEL_ENCODER_MISC_COHERENT            0x02
-#define	PANEL_ENCODER_MISC_TMDS_LINKB					 0x04
-#define	PANEL_ENCODER_MISC_HDMI_TYPE					 0x08
-
-#define PANEL_ENCODER_ACTION_DISABLE           ATOM_DISABLE
-#define PANEL_ENCODER_ACTION_ENABLE            ATOM_ENABLE
-#define PANEL_ENCODER_ACTION_COHERENTSEQ       (ATOM_ENABLE+1)
-
-#define PANEL_ENCODER_TRUNCATE_EN              0x01
-#define PANEL_ENCODER_TRUNCATE_DEPTH           0x10
-#define PANEL_ENCODER_SPATIAL_DITHER_EN        0x01
-#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH     0x10
-#define PANEL_ENCODER_TEMPORAL_DITHER_EN       0x01
-#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH    0x10
-#define PANEL_ENCODER_TEMPORAL_LEVEL_4         0x20
-#define PANEL_ENCODER_25FRC_MASK               0x10
-#define PANEL_ENCODER_25FRC_E                  0x00
-#define PANEL_ENCODER_25FRC_F                  0x10
-#define PANEL_ENCODER_50FRC_MASK               0x60
-#define PANEL_ENCODER_50FRC_A                  0x00
-#define PANEL_ENCODER_50FRC_B                  0x20
-#define PANEL_ENCODER_50FRC_C                  0x40
-#define PANEL_ENCODER_50FRC_D                  0x60
-#define PANEL_ENCODER_75FRC_MASK               0x80
-#define PANEL_ENCODER_75FRC_E                  0x00
-#define PANEL_ENCODER_75FRC_F                  0x80
-
-/****************************************************************************/	
-// Structures used by SetVoltageTable
-/****************************************************************************/	
-#define SET_VOLTAGE_TYPE_ASIC_VDDC             1
-#define SET_VOLTAGE_TYPE_ASIC_MVDDC            2
-#define SET_VOLTAGE_TYPE_ASIC_MVDDQ            3
-#define SET_VOLTAGE_TYPE_ASIC_VDDCI            4
-#define SET_VOLTAGE_INIT_MODE                  5
-#define SET_VOLTAGE_GET_MAX_VOLTAGE            6					//Gets the Max. voltage for the soldered Asic
-
-#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE       0x1
-#define SET_ASIC_VOLTAGE_MODE_SOURCE_A         0x2
-#define SET_ASIC_VOLTAGE_MODE_SOURCE_B         0x4
-
-#define	SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE      0x0
-#define	SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL      0x1
-#define	SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK     0x2
-
-typedef struct	_SET_VOLTAGE_PARAMETERS
-{
-  UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
-  UCHAR    ucVoltageMode;               // To set all, to set source A or source B or ...
-  UCHAR    ucVoltageIndex;              // An index to tell which voltage level
-  UCHAR    ucReserved;          
-}SET_VOLTAGE_PARAMETERS;
-
-typedef struct	_SET_VOLTAGE_PARAMETERS_V2
-{
-  UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
-  UCHAR    ucVoltageMode;               // Not used, maybe use for state machine for differen power mode
-  USHORT   usVoltageLevel;              // real voltage level
-}SET_VOLTAGE_PARAMETERS_V2;
-
-// used by both SetVoltageTable v1.3 and v1.4
-typedef struct	_SET_VOLTAGE_PARAMETERS_V1_3
-{
-  UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
-  UCHAR    ucVoltageMode;               // Indicate action: Set voltage level
-  USHORT   usVoltageLevel;              // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
-}SET_VOLTAGE_PARAMETERS_V1_3;
-
-//ucVoltageType
-#define VOLTAGE_TYPE_VDDC                    1
-#define VOLTAGE_TYPE_MVDDC                   2
-#define VOLTAGE_TYPE_MVDDQ                   3
-#define VOLTAGE_TYPE_VDDCI                   4
-
-//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
-#define ATOM_SET_VOLTAGE                     0        //Set voltage Level
-#define ATOM_INIT_VOLTAGE_REGULATOR          3        //Init Regulator
-#define ATOM_SET_VOLTAGE_PHASE               4        //Set Vregulator Phase, only for SVID/PVID regulator
-#define ATOM_GET_MAX_VOLTAGE                 6        //Get Max Voltage, not used from SetVoltageTable v1.3
-#define ATOM_GET_VOLTAGE_LEVEL               6        //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4
-#define ATOM_GET_LEAKAGE_ID                  8        //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 
-
-// define vitual voltage id in usVoltageLevel
-#define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
-#define ATOM_VIRTUAL_VOLTAGE_ID1             0xff02
-#define ATOM_VIRTUAL_VOLTAGE_ID2             0xff03
-#define ATOM_VIRTUAL_VOLTAGE_ID3             0xff04
-#define ATOM_VIRTUAL_VOLTAGE_ID4             0xff05
-#define ATOM_VIRTUAL_VOLTAGE_ID5             0xff06
-#define ATOM_VIRTUAL_VOLTAGE_ID6             0xff07
-#define ATOM_VIRTUAL_VOLTAGE_ID7             0xff08
-
-typedef struct _SET_VOLTAGE_PS_ALLOCATION
-{
-  SET_VOLTAGE_PARAMETERS sASICSetVoltage;
-  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
-}SET_VOLTAGE_PS_ALLOCATION;
-
-// New Added from SI for GetVoltageInfoTable, input parameter structure
-typedef struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
-{
-  UCHAR    ucVoltageType;               // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
-  UCHAR    ucVoltageMode;               // Input: Indicate action: Get voltage info
-  USHORT   usVoltageLevel;              // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 
-  ULONG    ulReserved;
-}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
-
-// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
-typedef struct  _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
-{
-  ULONG    ulVotlageGpioState;
-  ULONG    ulVoltageGPioMask;
-}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
-
-// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
-typedef struct  _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
-{
-  USHORT   usVoltageLevel;
-  USHORT   usVoltageId;                                  // Voltage Id programmed in Voltage Regulator
-  ULONG    ulReseved;
-}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
-
-
-// GetVoltageInfo v1.1 ucVoltageMode
-#define	ATOM_GET_VOLTAGE_VID                0x00
-#define ATOM_GET_VOTLAGE_INIT_SEQ           0x03
-#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID   0x04
-#define ATOM_GET_VOLTAGE_SVID2              0x07        //Get SVI2 Regulator Info
-
-// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
-#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
-// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
-#define	ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
-
-#define	ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
-#define	ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
-
-// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
-typedef struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
-{
-  UCHAR    ucVoltageType;               // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
-  UCHAR    ucVoltageMode;               // Input: Indicate action: Get voltage info
-  USHORT   usVoltageLevel;              // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 
-  ULONG    ulSCLKFreq;                  // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
-}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;
-
-// New in GetVoltageInfo v1.2 ucVoltageMode
-#define ATOM_GET_VOLTAGE_EVV_VOLTAGE        0x09        
-
-// New Added from CI Hawaii for EVV feature 
-typedef struct  _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
-{
-  USHORT   usVoltageLevel;                               // real voltage level in unit of mv
-  USHORT   usVoltageId;                                  // Voltage Id programmed in Voltage Regulator
-  ULONG    ulReseved;
-}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;
-
-/****************************************************************************/	
-// Structures used by TVEncoderControlTable
-/****************************************************************************/	
-typedef struct _TV_ENCODER_CONTROL_PARAMETERS
-{
-  USHORT usPixelClock;                // in 10KHz; for bios convenient
-  UCHAR  ucTvStandard;                // See definition "ATOM_TV_NTSC ..."
-  UCHAR  ucAction;                    // 0: turn off encoder
-                                      // 1: setup and turn on encoder
-}TV_ENCODER_CONTROL_PARAMETERS;
-
-typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
-{
-  TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;          
-  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved; // Don't set this one
-}TV_ENCODER_CONTROL_PS_ALLOCATION;
-
-//==============================Data Table Portion====================================
-
-/****************************************************************************/	
-// Structure used in Data.mtb
-/****************************************************************************/	
-typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
-{
-  USHORT        UtilityPipeLine;	        // Offest for the utility to get parser info,Don't change this position!
-  USHORT        MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 
-  USHORT        MultimediaConfigInfo;     // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
-  USHORT        StandardVESA_Timing;      // Only used by Bios
-  USHORT        FirmwareInfo;             // Shared by various SW components,latest version 1.4
-  USHORT        PaletteData;              // Only used by BIOS
-  USHORT        LCD_Info;                 // Shared by various SW components,latest version 1.3, was called LVDS_Info 
-  USHORT        DIGTransmitterInfo;       // Internal used by VBIOS only version 3.1
-  USHORT        AnalogTV_Info;            // Shared by various SW components,latest version 1.1 
-  USHORT        SupportedDevicesInfo;     // Will be obsolete from R600
-  USHORT        GPIO_I2C_Info;            // Shared by various SW components,latest version 1.2 will be used from R600           
-  USHORT        VRAM_UsageByFirmware;     // Shared by various SW components,latest version 1.3 will be used from R600
-  USHORT        GPIO_Pin_LUT;             // Shared by various SW components,latest version 1.1
-  USHORT        VESA_ToInternalModeLUT;   // Only used by Bios
-  USHORT        ComponentVideoInfo;       // Shared by various SW components,latest version 2.1 will be used from R600
-  USHORT        PowerPlayInfo;            // Shared by various SW components,latest version 2.1,new design from R600
-  USHORT        CompassionateData;        // Will be obsolete from R600
-  USHORT        SaveRestoreInfo;          // Only used by Bios
-  USHORT        PPLL_SS_Info;             // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
-  USHORT        OemInfo;                  // Defined and used by external SW, should be obsolete soon
-  USHORT        XTMDS_Info;               // Will be obsolete from R600
-  USHORT        MclkSS_Info;              // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
-  USHORT        Object_Header;            // Shared by various SW components,latest version 1.1
-  USHORT        IndirectIOAccess;         // Only used by Bios,this table position can't change at all!!
-  USHORT        MC_InitParameter;         // Only used by command table
-  USHORT        ASIC_VDDC_Info;						// Will be obsolete from R600
-  USHORT        ASIC_InternalSS_Info;			// New tabel name from R600, used to be called "ASIC_MVDDC_Info"
-  USHORT        TV_VideoMode;							// Only used by command table
-  USHORT        VRAM_Info;								// Only used by command table, latest version 1.3
-  USHORT        MemoryTrainingInfo;				// Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
-  USHORT        IntegratedSystemInfo;			// Shared by various SW components
-  USHORT        ASIC_ProfilingInfo;				// New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
-  USHORT        VoltageObjectInfo;				// Shared by various SW components, latest version 1.1
-	USHORT				PowerSourceInfo;					// Shared by various SW components, latest versoin 1.1
-}ATOM_MASTER_LIST_OF_DATA_TABLES;
-
-typedef struct _ATOM_MASTER_DATA_TABLE
-{ 
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  ATOM_MASTER_LIST_OF_DATA_TABLES   ListOfDataTables;
-}ATOM_MASTER_DATA_TABLE;
-
-// For backward compatible 
-#define LVDS_Info                LCD_Info
-#define DAC_Info                 PaletteData
-#define TMDS_Info                DIGTransmitterInfo
-
-/****************************************************************************/	
-// Structure used in MultimediaCapabilityInfoTable
-/****************************************************************************/	
-typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  ULONG                    ulSignature;      // HW info table signature string "$ATI"
-  UCHAR                    ucI2C_Type;       // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
-  UCHAR                    ucTV_OutInfo;     // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
-  UCHAR                    ucVideoPortInfo;  // Provides the video port capabilities
-  UCHAR                    ucHostPortInfo;   // Provides host port configuration information
-}ATOM_MULTIMEDIA_CAPABILITY_INFO;
-
-/****************************************************************************/	
-// Structure used in MultimediaConfigInfoTable
-/****************************************************************************/	
-typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;
-  ULONG                    ulSignature;      // MM info table signature sting "$MMT"
-  UCHAR                    ucTunerInfo;      // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
-  UCHAR                    ucAudioChipInfo;  // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
-  UCHAR                    ucProductID;      // Defines as OEM ID or ATI board ID dependent on product type setting
-  UCHAR                    ucMiscInfo1;      // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
-  UCHAR                    ucMiscInfo2;      // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
-  UCHAR                    ucMiscInfo3;      // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
-  UCHAR                    ucMiscInfo4;      // Video Decoder Host Config (2:0) reserved (7:3)
-  UCHAR                    ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
-  UCHAR                    ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
-  UCHAR                    ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
-  UCHAR                    ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
-  UCHAR                    ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
-}ATOM_MULTIMEDIA_CONFIG_INFO;
-
-
-/****************************************************************************/	
-// Structures used in FirmwareInfoTable
-/****************************************************************************/	
-
-// usBIOSCapability Definition:
-// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 
-// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 
-// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 
-// Others: Reserved
-#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED         0x0001
-#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT            0x0002
-#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT     0x0004
-#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT      0x0008		// (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 
-#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT      0x0010		// (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 
-#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU         0x0020
-#define ATOM_BIOS_INFO_WMI_SUPPORT                  0x0040
-#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080
-#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT          0x0100
-#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK        0x1E00
-#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
-#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE  0x4000
-#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT  0x0008		// (valid from v2.1 ): =1: memclk ss enable with external ss chip
-#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT  0x0010		// (valid from v2.1 ): =1: engclk ss enable with external ss chip
-
-#ifndef _H2INC
-
-//Please don't add or expand this bitfield structure below, this one will retire soon.!
-typedef struct _ATOM_FIRMWARE_CAPABILITY
-{
-#if ATOM_BIG_ENDIAN
-  USHORT Reserved:1;
-  USHORT SCL2Redefined:1;
-  USHORT PostWithoutModeSet:1;
-  USHORT HyperMemory_Size:4;
-  USHORT HyperMemory_Support:1;
-  USHORT PPMode_Assigned:1;
-  USHORT WMI_SUPPORT:1;
-  USHORT GPUControlsBL:1;
-  USHORT EngineClockSS_Support:1;
-  USHORT MemoryClockSS_Support:1;
-  USHORT ExtendedDesktopSupport:1;
-  USHORT DualCRTC_Support:1;
-  USHORT FirmwarePosted:1;
-#else
-  USHORT FirmwarePosted:1;
-  USHORT DualCRTC_Support:1;
-  USHORT ExtendedDesktopSupport:1;
-  USHORT MemoryClockSS_Support:1;
-  USHORT EngineClockSS_Support:1;
-  USHORT GPUControlsBL:1;
-  USHORT WMI_SUPPORT:1;
-  USHORT PPMode_Assigned:1;
-  USHORT HyperMemory_Support:1;
-  USHORT HyperMemory_Size:4;
-  USHORT PostWithoutModeSet:1;
-  USHORT SCL2Redefined:1;
-  USHORT Reserved:1;
-#endif
-}ATOM_FIRMWARE_CAPABILITY;
-
-typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
-{
-  ATOM_FIRMWARE_CAPABILITY sbfAccess;
-  USHORT                   susAccess;
-}ATOM_FIRMWARE_CAPABILITY_ACCESS;
-
-#else
-
-typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
-{
-  USHORT                   susAccess;
-}ATOM_FIRMWARE_CAPABILITY_ACCESS;
-
-#endif
-
-typedef struct _ATOM_FIRMWARE_INFO
-{
-  ATOM_COMMON_TABLE_HEADER        sHeader; 
-  ULONG                           ulFirmwareRevision;
-  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
-  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
-  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
-  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
-  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
-  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
-  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
-  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
-  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
-  UCHAR                           ucASICMaxTemperature;
-  UCHAR                           ucPadding[3];               //Don't use them
-  ULONG                           aulReservedForBIOS[3];      //Don't use them
-  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
-  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
-  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
-  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit, the definitions above can't change!!!
-  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
-  USHORT                          usReferenceClock;           //In 10Khz unit	
-  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
-  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
-  UCHAR                           ucDesign_ID;                //Indicate what is the board design
-  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
-}ATOM_FIRMWARE_INFO;
-
-typedef struct _ATOM_FIRMWARE_INFO_V1_2
-{
-  ATOM_COMMON_TABLE_HEADER        sHeader; 
-  ULONG                           ulFirmwareRevision;
-  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
-  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
-  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
-  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
-  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
-  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
-  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
-  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
-  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
-  UCHAR                           ucASICMaxTemperature;
-  UCHAR                           ucMinAllowedBL_Level;
-  UCHAR                           ucPadding[2];               //Don't use them
-  ULONG                           aulReservedForBIOS[2];      //Don't use them
-  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
-  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
-  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
-  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
-  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
-  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
-  USHORT                          usReferenceClock;           //In 10Khz unit	
-  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
-  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
-  UCHAR                           ucDesign_ID;                //Indicate what is the board design
-  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
-}ATOM_FIRMWARE_INFO_V1_2;
-
-typedef struct _ATOM_FIRMWARE_INFO_V1_3
-{
-  ATOM_COMMON_TABLE_HEADER        sHeader; 
-  ULONG                           ulFirmwareRevision;
-  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
-  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
-  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
-  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
-  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
-  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
-  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
-  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
-  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
-  UCHAR                           ucASICMaxTemperature;
-  UCHAR                           ucMinAllowedBL_Level;
-  UCHAR                           ucPadding[2];               //Don't use them
-  ULONG                           aulReservedForBIOS;         //Don't use them
-  ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
-  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
-  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
-  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
-  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
-  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
-  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
-  USHORT                          usReferenceClock;           //In 10Khz unit	
-  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
-  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
-  UCHAR                           ucDesign_ID;                //Indicate what is the board design
-  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
-}ATOM_FIRMWARE_INFO_V1_3;
-
-typedef struct _ATOM_FIRMWARE_INFO_V1_4
-{
-  ATOM_COMMON_TABLE_HEADER        sHeader; 
-  ULONG                           ulFirmwareRevision;
-  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
-  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
-  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
-  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
-  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
-  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
-  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
-  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
-  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
-  UCHAR                           ucASICMaxTemperature;
-  UCHAR                           ucMinAllowedBL_Level;
-  USHORT                          usBootUpVDDCVoltage;        //In MV unit
-  USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
-  USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
-  ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
-  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
-  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
-  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
-  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
-  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
-  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
-  USHORT                          usReferenceClock;           //In 10Khz unit	
-  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
-  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
-  UCHAR                           ucDesign_ID;                //Indicate what is the board design
-  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
-}ATOM_FIRMWARE_INFO_V1_4;
-
-//the structure below to be used from Cypress
-typedef struct _ATOM_FIRMWARE_INFO_V2_1
-{
-  ATOM_COMMON_TABLE_HEADER        sHeader; 
-  ULONG                           ulFirmwareRevision;
-  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
-  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
-  ULONG                           ulReserved1;
-  ULONG                           ulReserved2;
-  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
-  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
-  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
-  ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock
-  ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit
-  UCHAR                           ucReserved1;                //Was ucASICMaxTemperature;
-  UCHAR                           ucMinAllowedBL_Level;
-  USHORT                          usBootUpVDDCVoltage;        //In MV unit
-  USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
-  USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
-  ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
-  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
-  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
-  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
-  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
-  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
-  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
-  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
-  USHORT                          usCoreReferenceClock;       //In 10Khz unit	
-  USHORT                          usMemoryReferenceClock;     //In 10Khz unit	
-  USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
-  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
-  UCHAR                           ucReserved4[3];
-}ATOM_FIRMWARE_INFO_V2_1;
-
-//the structure below to be used from NI
-//ucTableFormatRevision=2
-//ucTableContentRevision=2
-typedef struct _ATOM_FIRMWARE_INFO_V2_2
-{
-  ATOM_COMMON_TABLE_HEADER        sHeader; 
-  ULONG                           ulFirmwareRevision;
-  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
-  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
-  ULONG                           ulSPLL_OutputFreq;          //In 10Khz unit  
-  ULONG                           ulGPUPLL_OutputFreq;        //In 10Khz unit
-  ULONG                           ulReserved1;                //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
-  ULONG                           ulReserved2;                //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
-  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
-  ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock  ?
-  ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.          
-  UCHAR                           ucReserved3;                //Was ucASICMaxTemperature;
-  UCHAR                           ucMinAllowedBL_Level;
-  USHORT                          usBootUpVDDCVoltage;        //In MV unit
-  USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
-  USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
-  ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
-  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
-  UCHAR                           ucRemoteDisplayConfig;
-  UCHAR                           ucReserved5[3];             //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
-  ULONG                           ulReserved6;                //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
-  ULONG                           ulReserved7;                //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
-  USHORT                          usReserved11;               //Was usMaxPixelClock;  //In 10Khz unit, Max.  Pclk used only for DAC
-  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
-  USHORT                          usBootUpVDDCIVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
-  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
-  USHORT                          usCoreReferenceClock;       //In 10Khz unit	
-  USHORT                          usMemoryReferenceClock;     //In 10Khz unit	
-  USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
-  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
-  UCHAR                           ucReserved9[3];
-  USHORT                          usBootUpMVDDCVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
-  USHORT                          usReserved12;
-  ULONG                           ulReserved10[3];            // New added comparing to previous version
-}ATOM_FIRMWARE_INFO_V2_2;
-
-#define ATOM_FIRMWARE_INFO_LAST  ATOM_FIRMWARE_INFO_V2_2
-
-
-// definition of ucRemoteDisplayConfig
-#define REMOTE_DISPLAY_DISABLE                   0x00
-#define REMOTE_DISPLAY_ENABLE                    0x01
-
-/****************************************************************************/	
-// Structures used in IntegratedSystemInfoTable
-/****************************************************************************/	
-#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN      0x2
-#define IGP_CAP_FLAG_AC_CARD               0x4
-#define IGP_CAP_FLAG_SDVO_CARD             0x8
-#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE     0x10
-
-typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
-{
-  ATOM_COMMON_TABLE_HEADER        sHeader; 
-  ULONG	                          ulBootUpEngineClock;		    //in 10kHz unit
-  ULONG	                          ulBootUpMemoryClock;		    //in 10kHz unit
-  ULONG	                          ulMaxSystemMemoryClock;	    //in 10kHz unit
-  ULONG	                          ulMinSystemMemoryClock;	    //in 10kHz unit
-  UCHAR                           ucNumberOfCyclesInPeriodHi;
-  UCHAR                           ucLCDTimingSel;             //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
-  USHORT                          usReserved1;
-  USHORT                          usInterNBVoltageLow;        //An intermidiate PMW value to set the voltage 
-  USHORT                          usInterNBVoltageHigh;       //Another intermidiate PMW value to set the voltage 
-  ULONG	                          ulReserved[2];
-
-  USHORT	                        usFSBClock;			            //In MHz unit
-  USHORT                          usCapabilityFlag;		        //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
-																                              //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
-                                                              //Bit[4]==1: P/2 mode, ==0: P/1 mode
-  USHORT	                        usPCIENBCfgReg7;				    //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
-  USHORT	                        usK8MemoryClock;            //in MHz unit
-  USHORT	                        usK8SyncStartDelay;         //in 0.01 us unit
-  USHORT	                        usK8DataReturnTime;         //in 0.01 us unit
-  UCHAR                           ucMaxNBVoltage;
-  UCHAR                           ucMinNBVoltage;
-  UCHAR                           ucMemoryType;					      //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
-  UCHAR                           ucNumberOfCyclesInPeriod;		//CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 
-  UCHAR                           ucStartingPWM_HighTime;     //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
-  UCHAR                           ucHTLinkWidth;              //16 bit vs. 8 bit
-  UCHAR                           ucMaxNBVoltageHigh;    
-  UCHAR                           ucMinNBVoltageHigh;
-}ATOM_INTEGRATED_SYSTEM_INFO;
-
-/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
-ulBootUpMemoryClock:    For Intel IGP,it's the UMA system memory clock 
-                        For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
-ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
-                        For AMD IGP,for now this can be 0
-ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 
-                        For AMD IGP,for now this can be 0
-
-usFSBClock:             For Intel IGP,it's FSB Freq 
-                        For AMD IGP,it's HT Link Speed
-
-usK8MemoryClock:        For AMD IGP only. For RevF CPU, set it to 200
-usK8SyncStartDelay:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
-usK8DataReturnTime:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
-
-VC:Voltage Control
-ucMaxNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
-ucMinNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
-
-ucNumberOfCyclesInPeriod:   Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 
-ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 
-
-ucMaxNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of  the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
-ucMinNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
-
-
-usInterNBVoltageLow:    Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
-usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
-*/
-
-
-/*
-The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
-Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 
-The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
-
-SW components can access the IGP system infor structure in the same way as before
-*/
-
-
-typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
-{
-  ATOM_COMMON_TABLE_HEADER   sHeader;
-  ULONG	                     ulBootUpEngineClock;       //in 10kHz unit
-  ULONG			     ulReserved1[2];            //must be 0x0 for the reserved
-  ULONG	                     ulBootUpUMAClock;          //in 10kHz unit
-  ULONG	                     ulBootUpSidePortClock;     //in 10kHz unit
-  ULONG	                     ulMinSidePortClock;        //in 10kHz unit
-  ULONG			     ulReserved2[6];            //must be 0x0 for the reserved
-  ULONG                      ulSystemConfig;            //see explanation below
-  ULONG                      ulBootUpReqDisplayVector;
-  ULONG                      ulOtherDisplayMisc;
-  ULONG                      ulDDISlot1Config;
-  ULONG                      ulDDISlot2Config;
-  UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
-  UCHAR                      ucUMAChannelNumber;
-  UCHAR                      ucDockingPinBit;
-  UCHAR                      ucDockingPinPolarity;
-  ULONG                      ulDockingPinCFGInfo;
-  ULONG                      ulCPUCapInfo;
-  USHORT                     usNumberOfCyclesInPeriod;
-  USHORT                     usMaxNBVoltage;
-  USHORT                     usMinNBVoltage;
-  USHORT                     usBootUpNBVoltage;
-  ULONG                      ulHTLinkFreq;              //in 10Khz
-  USHORT                     usMinHTLinkWidth;
-  USHORT                     usMaxHTLinkWidth;
-  USHORT                     usUMASyncStartDelay;
-  USHORT                     usUMADataReturnTime;
-  USHORT                     usLinkStatusZeroTime;
-  USHORT                     usDACEfuse;				//for storing badgap value (for RS880 only)
-  ULONG                      ulHighVoltageHTLinkFreq;     // in 10Khz
-  ULONG                      ulLowVoltageHTLinkFreq;      // in 10Khz
-  USHORT                     usMaxUpStreamHTLinkWidth;
-  USHORT                     usMaxDownStreamHTLinkWidth;
-  USHORT                     usMinUpStreamHTLinkWidth;
-  USHORT                     usMinDownStreamHTLinkWidth;
-  USHORT                     usFirmwareVersion;         //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
-  USHORT                     usFullT0Time;             // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
-  ULONG                      ulReserved3[96];          //must be 0x0
-}ATOM_INTEGRATED_SYSTEM_INFO_V2;   
-
-/*
-ulBootUpEngineClock:   Boot-up Engine Clock in 10Khz;
-ulBootUpUMAClock:      Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
-ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
-
-ulSystemConfig:  
-Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 
-Bit[1]=1: system boots up at AMD overdrived state or user customized  mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
-      =0: system boots up at driver control state. Power state depends on PowerPlay table.
-Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
-Bit[3]=1: Only one power state(Performance) will be supported.
-      =0: Multiple power states supported from PowerPlay table.
-Bit[4]=1: CLMC is supported and enabled on current system. 
-      =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.  
-Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.  
-      =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
-Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
-      =0: Voltage settings is determined by powerplay table.
-Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
-      =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
-Bit[8]=1: CDLF is supported and enabled on current system.
-      =0: CDLF is not supported or enabled on current system.
-Bit[9]=1: DLL Shut Down feature is enabled on current system.
-      =0: DLL Shut Down feature is not enabled or supported on current system.
-
-ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
-
-ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
-			              [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition;
-
-ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
-      [3:0]  - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
-			[7:4]  - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
-      When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
-      in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
-      one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
-
-			[15:8] - Lane configuration attribute; 
-      [23:16]- Connector type, possible value:
-               CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
-               CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
-               CONNECTOR_OBJECT_ID_HDMI_TYPE_A
-               CONNECTOR_OBJECT_ID_DISPLAYPORT
-               CONNECTOR_OBJECT_ID_eDP
-			[31:24]- Reserved
-
-ulDDISlot2Config: Same as Slot1.
-ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
-For IGP, Hypermemory is the only memory type showed in CCC.
-
-ucUMAChannelNumber:  how many channels for the UMA;
-
-ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 
-ucDockingPinBit:     which bit in this register to read the pin status;
-ucDockingPinPolarity:Polarity of the pin when docked;
-
-ulCPUCapInfo:        [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
-
-usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
-
-usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 
-usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
-                    GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
-                    PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
-                    GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
-
-usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
-
-ulHTLinkFreq:       Bootup HT link Frequency in 10Khz.
-usMinHTLinkWidth:   Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 
-                    If CDLW enabled, both upstream and downstream width should be the same during bootup.
-usMaxHTLinkWidth:   Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 
-                    If CDLW enabled, both upstream and downstream width should be the same during bootup.  
-
-usUMASyncStartDelay: Memory access latency, required for watermark calculation 
-usUMADataReturnTime: Memory access latency, required for watermark calculation
-usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 
-for Griffin or Greyhound. SBIOS needs to convert to actual time by:
-                     if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
-                     if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
-                     if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
-                     if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
-
-ulHighVoltageHTLinkFreq:     HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
-                             This must be less than or equal to ulHTLinkFreq(bootup frequency). 
-ulLowVoltageHTLinkFreq:      HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
-                             This must be less than or equal to ulHighVoltageHTLinkFreq.
-
-usMaxUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
-usMaxDownStreamHTLinkWidth:  same as above.
-usMinUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
-usMinDownStreamHTLinkWidth:  same as above.
-*/
-
-// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo  - CPU type definition 
-#define    INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU             0
-#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN        1
-#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND      2
-#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__K8             3
-#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH        4
-#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI         5
-
-#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE       INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI    // this deff reflects max defined CPU code
-
-#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE                 0x00000001
-#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE             0x00000002
-#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE                  0x00000004 
-#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY         0x00000008
-#define SYSTEM_CONFIG_CLMC_ENABLED                        0x00000010
-#define SYSTEM_CONFIG_CDLW_ENABLED                        0x00000020
-#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED              0x00000040
-#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED            0x00000080
-#define SYSTEM_CONFIG_CDLF_ENABLED                        0x00000100
-#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED                0x00000200
-
-#define IGP_DDI_SLOT_LANE_CONFIG_MASK                     0x000000FF
-
-#define b0IGP_DDI_SLOT_LANE_MAP_MASK                      0x0F
-#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK              0xF0
-#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3                    0x01
-#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7                    0x02
-#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11                   0x04
-#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15                  0x08
-
-#define IGP_DDI_SLOT_ATTRIBUTE_MASK                       0x0000FF00
-#define IGP_DDI_SLOT_CONFIG_REVERSED                      0x00000100
-#define b1IGP_DDI_SLOT_CONFIG_REVERSED                    0x01
-
-#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK                  0x00FF0000
-
-// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
-typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
-{
-  ATOM_COMMON_TABLE_HEADER   sHeader;
-  ULONG	                     ulBootUpEngineClock;       //in 10kHz unit
-  ULONG                      ulDentistVCOFreq;          //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 
-  ULONG                      ulLClockFreq;              //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
-  ULONG	                     ulBootUpUMAClock;          //in 10kHz unit
-  ULONG                      ulReserved1[8];            //must be 0x0 for the reserved
-  ULONG                      ulBootUpReqDisplayVector;
-  ULONG                      ulOtherDisplayMisc;
-  ULONG                      ulReserved2[4];            //must be 0x0 for the reserved
-  ULONG                      ulSystemConfig;            //TBD
-  ULONG                      ulCPUCapInfo;              //TBD
-  USHORT                     usMaxNBVoltage;            //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
-  USHORT                     usMinNBVoltage;            //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
-  USHORT                     usBootUpNBVoltage;         //boot up NB voltage
-  UCHAR                      ucHtcTmpLmt;               //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
-  UCHAR                      ucTjOffset;                //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
-  ULONG                      ulReserved3[4];            //must be 0x0 for the reserved
-  ULONG                      ulDDISlot1Config;          //see above ulDDISlot1Config definition
-  ULONG                      ulDDISlot2Config;
-  ULONG                      ulDDISlot3Config;
-  ULONG                      ulDDISlot4Config;
-  ULONG                      ulReserved4[4];            //must be 0x0 for the reserved
-  UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
-  UCHAR                      ucUMAChannelNumber;
-  USHORT                     usReserved;
-  ULONG                      ulReserved5[4];            //must be 0x0 for the reserved
-  ULONG                      ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
-  ULONG                      ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
-  ULONG                      ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
-  ULONG                      ulReserved6[61];           //must be 0x0
-}ATOM_INTEGRATED_SYSTEM_INFO_V5;   
-
-#define ATOM_CRT_INT_ENCODER1_INDEX                       0x00000000
-#define ATOM_LCD_INT_ENCODER1_INDEX                       0x00000001
-#define ATOM_TV_INT_ENCODER1_INDEX                        0x00000002
-#define ATOM_DFP_INT_ENCODER1_INDEX                       0x00000003
-#define ATOM_CRT_INT_ENCODER2_INDEX                       0x00000004
-#define ATOM_LCD_EXT_ENCODER1_INDEX                       0x00000005
-#define ATOM_TV_EXT_ENCODER1_INDEX                        0x00000006
-#define ATOM_DFP_EXT_ENCODER1_INDEX                       0x00000007
-#define ATOM_CV_INT_ENCODER1_INDEX                        0x00000008
-#define ATOM_DFP_INT_ENCODER2_INDEX                       0x00000009
-#define ATOM_CRT_EXT_ENCODER1_INDEX                       0x0000000A
-#define ATOM_CV_EXT_ENCODER1_INDEX                        0x0000000B
-#define ATOM_DFP_INT_ENCODER3_INDEX                       0x0000000C
-#define ATOM_DFP_INT_ENCODER4_INDEX                       0x0000000D
-
-// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
-#define ASIC_INT_DAC1_ENCODER_ID    											0x00 
-#define ASIC_INT_TV_ENCODER_ID														0x02
-#define ASIC_INT_DIG1_ENCODER_ID													0x03
-#define ASIC_INT_DAC2_ENCODER_ID													0x04
-#define ASIC_EXT_TV_ENCODER_ID														0x06
-#define ASIC_INT_DVO_ENCODER_ID														0x07
-#define ASIC_INT_DIG2_ENCODER_ID													0x09
-#define ASIC_EXT_DIG_ENCODER_ID														0x05
-#define ASIC_EXT_DIG2_ENCODER_ID													0x08
-#define ASIC_INT_DIG3_ENCODER_ID													0x0a
-#define ASIC_INT_DIG4_ENCODER_ID													0x0b
-#define ASIC_INT_DIG5_ENCODER_ID													0x0c
-#define ASIC_INT_DIG6_ENCODER_ID													0x0d
-#define ASIC_INT_DIG7_ENCODER_ID													0x0e
-
-//define Encoder attribute
-#define ATOM_ANALOG_ENCODER																0
-#define ATOM_DIGITAL_ENCODER															1		
-#define ATOM_DP_ENCODER															      2		
-
-#define ATOM_ENCODER_ENUM_MASK                            0x70
-#define ATOM_ENCODER_ENUM_ID1                             0x00
-#define ATOM_ENCODER_ENUM_ID2                             0x10
-#define ATOM_ENCODER_ENUM_ID3                             0x20
-#define ATOM_ENCODER_ENUM_ID4                             0x30
-#define ATOM_ENCODER_ENUM_ID5                             0x40 
-#define ATOM_ENCODER_ENUM_ID6                             0x50
-
-#define ATOM_DEVICE_CRT1_INDEX                            0x00000000
-#define ATOM_DEVICE_LCD1_INDEX                            0x00000001
-#define ATOM_DEVICE_TV1_INDEX                             0x00000002
-#define ATOM_DEVICE_DFP1_INDEX                            0x00000003
-#define ATOM_DEVICE_CRT2_INDEX                            0x00000004
-#define ATOM_DEVICE_LCD2_INDEX                            0x00000005
-#define ATOM_DEVICE_DFP6_INDEX                            0x00000006
-#define ATOM_DEVICE_DFP2_INDEX                            0x00000007
-#define ATOM_DEVICE_CV_INDEX                              0x00000008
-#define ATOM_DEVICE_DFP3_INDEX                            0x00000009
-#define ATOM_DEVICE_DFP4_INDEX                            0x0000000A
-#define ATOM_DEVICE_DFP5_INDEX                            0x0000000B
-
-#define ATOM_DEVICE_RESERVEDC_INDEX                       0x0000000C
-#define ATOM_DEVICE_RESERVEDD_INDEX                       0x0000000D
-#define ATOM_DEVICE_RESERVEDE_INDEX                       0x0000000E
-#define ATOM_DEVICE_RESERVEDF_INDEX                       0x0000000F
-#define ATOM_MAX_SUPPORTED_DEVICE_INFO                    (ATOM_DEVICE_DFP3_INDEX+1)
-#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2                  ATOM_MAX_SUPPORTED_DEVICE_INFO
-#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3                  (ATOM_DEVICE_DFP5_INDEX + 1 )
-
-#define ATOM_MAX_SUPPORTED_DEVICE                         (ATOM_DEVICE_RESERVEDF_INDEX+1)
-
-#define ATOM_DEVICE_CRT1_SUPPORT                          (0x1L << ATOM_DEVICE_CRT1_INDEX )
-#define ATOM_DEVICE_LCD1_SUPPORT                          (0x1L << ATOM_DEVICE_LCD1_INDEX )
-#define ATOM_DEVICE_TV1_SUPPORT                           (0x1L << ATOM_DEVICE_TV1_INDEX  )
-#define ATOM_DEVICE_DFP1_SUPPORT                          (0x1L << ATOM_DEVICE_DFP1_INDEX )
-#define ATOM_DEVICE_CRT2_SUPPORT                          (0x1L << ATOM_DEVICE_CRT2_INDEX )
-#define ATOM_DEVICE_LCD2_SUPPORT                          (0x1L << ATOM_DEVICE_LCD2_INDEX )
-#define ATOM_DEVICE_DFP6_SUPPORT                          (0x1L << ATOM_DEVICE_DFP6_INDEX )
-#define ATOM_DEVICE_DFP2_SUPPORT                          (0x1L << ATOM_DEVICE_DFP2_INDEX )
-#define ATOM_DEVICE_CV_SUPPORT                            (0x1L << ATOM_DEVICE_CV_INDEX   )
-#define ATOM_DEVICE_DFP3_SUPPORT                          (0x1L << ATOM_DEVICE_DFP3_INDEX )
-#define ATOM_DEVICE_DFP4_SUPPORT                          (0x1L << ATOM_DEVICE_DFP4_INDEX )
-#define ATOM_DEVICE_DFP5_SUPPORT                          (0x1L << ATOM_DEVICE_DFP5_INDEX )
-
-#define ATOM_DEVICE_CRT_SUPPORT                           (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
-#define ATOM_DEVICE_DFP_SUPPORT                           (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT |  ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
-#define ATOM_DEVICE_TV_SUPPORT                            (ATOM_DEVICE_TV1_SUPPORT)
-#define ATOM_DEVICE_LCD_SUPPORT                           (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
-
-#define ATOM_DEVICE_CONNECTOR_TYPE_MASK                   0x000000F0
-#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT                  0x00000004
-#define ATOM_DEVICE_CONNECTOR_VGA                         0x00000001
-#define ATOM_DEVICE_CONNECTOR_DVI_I                       0x00000002
-#define ATOM_DEVICE_CONNECTOR_DVI_D                       0x00000003
-#define ATOM_DEVICE_CONNECTOR_DVI_A                       0x00000004
-#define ATOM_DEVICE_CONNECTOR_SVIDEO                      0x00000005
-#define ATOM_DEVICE_CONNECTOR_COMPOSITE                   0x00000006
-#define ATOM_DEVICE_CONNECTOR_LVDS                        0x00000007
-#define ATOM_DEVICE_CONNECTOR_DIGI_LINK                   0x00000008
-#define ATOM_DEVICE_CONNECTOR_SCART                       0x00000009
-#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A                 0x0000000A
-#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B                 0x0000000B
-#define ATOM_DEVICE_CONNECTOR_CASE_1                      0x0000000E
-#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT                 0x0000000F
-
-
-#define ATOM_DEVICE_DAC_INFO_MASK                         0x0000000F
-#define ATOM_DEVICE_DAC_INFO_SHIFT                        0x00000000
-#define ATOM_DEVICE_DAC_INFO_NODAC                        0x00000000
-#define ATOM_DEVICE_DAC_INFO_DACA                         0x00000001
-#define ATOM_DEVICE_DAC_INFO_DACB                         0x00000002
-#define ATOM_DEVICE_DAC_INFO_EXDAC                        0x00000003
-
-#define ATOM_DEVICE_I2C_ID_NOI2C                          0x00000000
-
-#define ATOM_DEVICE_I2C_LINEMUX_MASK                      0x0000000F
-#define ATOM_DEVICE_I2C_LINEMUX_SHIFT                     0x00000000
-
-#define ATOM_DEVICE_I2C_ID_MASK                           0x00000070
-#define ATOM_DEVICE_I2C_ID_SHIFT                          0x00000004
-#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE              0x00000001
-#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE                  0x00000002
-#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE                0x00000003    //For IGP RS600
-#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL                 0x00000004    //For IGP RS690
-
-#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK                 0x00000080
-#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT                0x00000007
-#define	ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C            0x00000000
-#define	ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C            0x00000001
-
-//  usDeviceSupport:
-//  Bits0	= 0 - no CRT1 support= 1- CRT1 is supported
-//  Bit 1	= 0 - no LCD1 support= 1- LCD1 is supported
-//  Bit 2	= 0 - no TV1  support= 1- TV1  is supported
-//  Bit 3	= 0 - no DFP1 support= 1- DFP1 is supported
-//  Bit 4	= 0 - no CRT2 support= 1- CRT2 is supported
-//  Bit 5	= 0 - no LCD2 support= 1- LCD2 is supported
-//  Bit 6	= 0 - no DFP6 support= 1- DFP6 is supported
-//  Bit 7	= 0 - no DFP2 support= 1- DFP2 is supported
-//  Bit 8	= 0 - no CV   support= 1- CV   is supported
-//  Bit 9	= 0 - no DFP3 support= 1- DFP3 is supported
-//  Bit 10      = 0 - no DFP4 support= 1- DFP4 is supported
-//  Bit 11      = 0 - no DFP5 support= 1- DFP5 is supported
-//   
-//  
-
-/****************************************************************************/
-/* Structure used in MclkSS_InfoTable                                       */
-/****************************************************************************/
-//		ucI2C_ConfigID
-//    [7:0] - I2C LINE Associate ID
-//          = 0   - no I2C
-//    [7]		-	HW_Cap        =	1,  [6:0]=HW assisted I2C ID(HW line selection)
-//                          =	0,  [6:0]=SW assisted I2C ID
-//    [6-4]	- HW_ENGINE_ID  =	1,  HW engine for NON multimedia use
-//                          =	2,	HW engine for Multimedia use
-//                          =	3-7	Reserved for future I2C engines
-//		[3-0] - I2C_LINE_MUX  = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
-
-typedef struct _ATOM_I2C_ID_CONFIG
-{
-#if ATOM_BIG_ENDIAN
-  UCHAR   bfHW_Capable:1;
-  UCHAR   bfHW_EngineID:3;
-  UCHAR   bfI2C_LineMux:4;
-#else
-  UCHAR   bfI2C_LineMux:4;
-  UCHAR   bfHW_EngineID:3;
-  UCHAR   bfHW_Capable:1;
-#endif
-}ATOM_I2C_ID_CONFIG;
-
-typedef union _ATOM_I2C_ID_CONFIG_ACCESS
-{
-  ATOM_I2C_ID_CONFIG sbfAccess;
-  UCHAR              ucAccess;
-}ATOM_I2C_ID_CONFIG_ACCESS;
-   
-
-/****************************************************************************/	
-// Structure used in GPIO_I2C_InfoTable
-/****************************************************************************/	
-typedef struct _ATOM_GPIO_I2C_ASSIGMENT
-{
-  USHORT                    usClkMaskRegisterIndex;
-  USHORT                    usClkEnRegisterIndex;
-  USHORT                    usClkY_RegisterIndex;
-  USHORT                    usClkA_RegisterIndex;
-  USHORT                    usDataMaskRegisterIndex;
-  USHORT                    usDataEnRegisterIndex;
-  USHORT                    usDataY_RegisterIndex;
-  USHORT                    usDataA_RegisterIndex;
-  ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
-  UCHAR                     ucClkMaskShift;
-  UCHAR                     ucClkEnShift;
-  UCHAR                     ucClkY_Shift;
-  UCHAR                     ucClkA_Shift;
-  UCHAR                     ucDataMaskShift;
-  UCHAR                     ucDataEnShift;
-  UCHAR                     ucDataY_Shift;
-  UCHAR                     ucDataA_Shift;
-  UCHAR                     ucReserved1;
-  UCHAR                     ucReserved2;
-}ATOM_GPIO_I2C_ASSIGMENT;
-
-typedef struct _ATOM_GPIO_I2C_INFO
-{ 
-  ATOM_COMMON_TABLE_HEADER	sHeader;
-  ATOM_GPIO_I2C_ASSIGMENT   asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
-}ATOM_GPIO_I2C_INFO;
-
-/****************************************************************************/	
-// Common Structure used in other structures
-/****************************************************************************/	
-
-#ifndef _H2INC
-  
-//Please don't add or expand this bitfield structure below, this one will retire soon.!
-typedef struct _ATOM_MODE_MISC_INFO
-{ 
-#if ATOM_BIG_ENDIAN
-  USHORT Reserved:6;
-  USHORT RGB888:1;
-  USHORT DoubleClock:1;
-  USHORT Interlace:1;
-  USHORT CompositeSync:1;
-  USHORT V_ReplicationBy2:1;
-  USHORT H_ReplicationBy2:1;
-  USHORT VerticalCutOff:1;
-  USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
-  USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
-  USHORT HorizontalCutOff:1;
-#else
-  USHORT HorizontalCutOff:1;
-  USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
-  USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
-  USHORT VerticalCutOff:1;
-  USHORT H_ReplicationBy2:1;
-  USHORT V_ReplicationBy2:1;
-  USHORT CompositeSync:1;
-  USHORT Interlace:1;
-  USHORT DoubleClock:1;
-  USHORT RGB888:1;
-  USHORT Reserved:6;           
-#endif
-}ATOM_MODE_MISC_INFO;
-  
-typedef union _ATOM_MODE_MISC_INFO_ACCESS
-{ 
-  ATOM_MODE_MISC_INFO sbfAccess;
-  USHORT              usAccess;
-}ATOM_MODE_MISC_INFO_ACCESS;
-  
-#else
-  
-typedef union _ATOM_MODE_MISC_INFO_ACCESS
-{ 
-  USHORT              usAccess;
-}ATOM_MODE_MISC_INFO_ACCESS;
-   
-#endif
-
-// usModeMiscInfo-
-#define ATOM_H_CUTOFF           0x01
-#define ATOM_HSYNC_POLARITY     0x02             //0=Active High, 1=Active Low
-#define ATOM_VSYNC_POLARITY     0x04             //0=Active High, 1=Active Low
-#define ATOM_V_CUTOFF           0x08
-#define ATOM_H_REPLICATIONBY2   0x10
-#define ATOM_V_REPLICATIONBY2   0x20
-#define ATOM_COMPOSITESYNC      0x40
-#define ATOM_INTERLACE          0x80
-#define ATOM_DOUBLE_CLOCK_MODE  0x100
-#define ATOM_RGB888_MODE        0x200
-
-//usRefreshRate-
-#define ATOM_REFRESH_43         43
-#define ATOM_REFRESH_47         47
-#define ATOM_REFRESH_56         56	
-#define ATOM_REFRESH_60         60
-#define ATOM_REFRESH_65         65
-#define ATOM_REFRESH_70         70
-#define ATOM_REFRESH_72         72
-#define ATOM_REFRESH_75         75
-#define ATOM_REFRESH_85         85
-
-// ATOM_MODE_TIMING data are exactly the same as VESA timing data.
-// Translation from EDID to ATOM_MODE_TIMING, use the following formula.
-//
-//	VESA_HTOTAL			=	VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
-//						=	EDID_HA + EDID_HBL
-//	VESA_HDISP			=	VESA_ACTIVE	=	EDID_HA
-//	VESA_HSYNC_START	=	VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
-//						=	EDID_HA + EDID_HSO
-//	VESA_HSYNC_WIDTH	=	VESA_HSYNC_TIME	=	EDID_HSPW
-//	VESA_BORDER			=	EDID_BORDER
-
-/****************************************************************************/	
-// Structure used in SetCRTC_UsingDTDTimingTable
-/****************************************************************************/	
-typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
-{
-  USHORT  usH_Size;
-  USHORT  usH_Blanking_Time;
-  USHORT  usV_Size;
-  USHORT  usV_Blanking_Time;			
-  USHORT  usH_SyncOffset;
-  USHORT  usH_SyncWidth;
-  USHORT  usV_SyncOffset;
-  USHORT  usV_SyncWidth;
-  ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;  
-  UCHAR   ucH_Border;         // From DFP EDID
-  UCHAR   ucV_Border;
-  UCHAR   ucCRTC;             // ATOM_CRTC1 or ATOM_CRTC2  
-  UCHAR   ucPadding[3];
-}SET_CRTC_USING_DTD_TIMING_PARAMETERS;
-
-/****************************************************************************/	
-// Structure used in SetCRTC_TimingTable
-/****************************************************************************/	
-typedef struct _SET_CRTC_TIMING_PARAMETERS
-{
-  USHORT                      usH_Total;        // horizontal total
-  USHORT                      usH_Disp;         // horizontal display
-  USHORT                      usH_SyncStart;    // horozontal Sync start
-  USHORT                      usH_SyncWidth;    // horizontal Sync width
-  USHORT                      usV_Total;        // vertical total
-  USHORT                      usV_Disp;         // vertical display
-  USHORT                      usV_SyncStart;    // vertical Sync start
-  USHORT                      usV_SyncWidth;    // vertical Sync width
-  ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
-  UCHAR                       ucCRTC;           // ATOM_CRTC1 or ATOM_CRTC2
-  UCHAR                       ucOverscanRight;  // right
-  UCHAR                       ucOverscanLeft;   // left
-  UCHAR                       ucOverscanBottom; // bottom
-  UCHAR                       ucOverscanTop;    // top
-  UCHAR                       ucReserved;
-}SET_CRTC_TIMING_PARAMETERS;
-#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
-
-/****************************************************************************/	
-// Structure used in StandardVESA_TimingTable
-//                   AnalogTV_InfoTable 
-//                   ComponentVideoInfoTable
-/****************************************************************************/	
-typedef struct _ATOM_MODE_TIMING
-{
-  USHORT  usCRTC_H_Total;
-  USHORT  usCRTC_H_Disp;
-  USHORT  usCRTC_H_SyncStart;
-  USHORT  usCRTC_H_SyncWidth;
-  USHORT  usCRTC_V_Total;
-  USHORT  usCRTC_V_Disp;
-  USHORT  usCRTC_V_SyncStart;
-  USHORT  usCRTC_V_SyncWidth;
-  USHORT  usPixelClock;					                 //in 10Khz unit
-  ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
-  USHORT  usCRTC_OverscanRight;
-  USHORT  usCRTC_OverscanLeft;
-  USHORT  usCRTC_OverscanBottom;
-  USHORT  usCRTC_OverscanTop;
-  USHORT  usReserve;
-  UCHAR   ucInternalModeNumber;
-  UCHAR   ucRefreshRate;
-}ATOM_MODE_TIMING;
-
-typedef struct _ATOM_DTD_FORMAT
-{
-  USHORT  usPixClk;
-  USHORT  usHActive;
-  USHORT  usHBlanking_Time;
-  USHORT  usVActive;
-  USHORT  usVBlanking_Time;			
-  USHORT  usHSyncOffset;
-  USHORT  usHSyncWidth;
-  USHORT  usVSyncOffset;
-  USHORT  usVSyncWidth;
-  USHORT  usImageHSize;
-  USHORT  usImageVSize;
-  UCHAR   ucHBorder;
-  UCHAR   ucVBorder;
-  ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
-  UCHAR   ucInternalModeNumber;
-  UCHAR   ucRefreshRate;
-}ATOM_DTD_FORMAT;
-
-/****************************************************************************/	
-// Structure used in LVDS_InfoTable 
-//  * Need a document to describe this table
-/****************************************************************************/	
-#define SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
-#define SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
-#define SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
-#define SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
-
-//ucTableFormatRevision=1
-//ucTableContentRevision=1
-typedef struct _ATOM_LVDS_INFO
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  ATOM_DTD_FORMAT     sLCDTiming;
-  USHORT              usModePatchTableOffset;
-  USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
-  USHORT              usOffDelayInMs;
-  UCHAR               ucPowerSequenceDigOntoDEin10Ms;
-  UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
-  UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
-                                                 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
-                                                 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
-                                                 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
-  UCHAR               ucPanelDefaultRefreshRate;
-  UCHAR               ucPanelIdentification;
-  UCHAR               ucSS_Id;
-}ATOM_LVDS_INFO;
-
-//ucTableFormatRevision=1
-//ucTableContentRevision=2
-typedef struct _ATOM_LVDS_INFO_V12
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  ATOM_DTD_FORMAT     sLCDTiming;
-  USHORT              usExtInfoTableOffset;
-  USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
-  USHORT              usOffDelayInMs;
-  UCHAR               ucPowerSequenceDigOntoDEin10Ms;
-  UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
-  UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
-                                                 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
-                                                 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
-                                                 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
-  UCHAR               ucPanelDefaultRefreshRate;
-  UCHAR               ucPanelIdentification;
-  UCHAR               ucSS_Id;
-  USHORT              usLCDVenderID;
-  USHORT              usLCDProductID;
-  UCHAR               ucLCDPanel_SpecialHandlingCap; 
-	UCHAR								ucPanelInfoSize;					//  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
-  UCHAR               ucReserved[2];
-}ATOM_LVDS_INFO_V12;
-
-//Definitions for ucLCDPanel_SpecialHandlingCap:
-
-//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 
-//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 
-#define	LCDPANEL_CAP_READ_EDID                  0x1
-
-//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
-//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
-//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
-#define	LCDPANEL_CAP_DRR_SUPPORTED              0x2
-
-//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
-#define	LCDPANEL_CAP_eDP                        0x4
-
-
-//Color Bit Depth definition in EDID V1.4 @BYTE 14h
-//Bit 6  5  4
-                              //      0  0  0  -  Color bit depth is undefined
-                              //      0  0  1  -  6 Bits per Primary Color
-                              //      0  1  0  -  8 Bits per Primary Color
-                              //      0  1  1  - 10 Bits per Primary Color
-                              //      1  0  0  - 12 Bits per Primary Color
-                              //      1  0  1  - 14 Bits per Primary Color
-                              //      1  1  0  - 16 Bits per Primary Color
-                              //      1  1  1  - Reserved
-
-#define PANEL_COLOR_BIT_DEPTH_MASK    0x70
-
-// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}   
-#define PANEL_RANDOM_DITHER   0x80
-#define PANEL_RANDOM_DITHER_MASK   0x80
-
-#define ATOM_LVDS_INFO_LAST  ATOM_LVDS_INFO_V12   // no need to change this 
-
-/****************************************************************************/	
-// Structures used by LCD_InfoTable V1.3    Note: previous version was called ATOM_LVDS_INFO_V12
-// ASIC Families:  NI
-// ucTableFormatRevision=1
-// ucTableContentRevision=3
-/****************************************************************************/	
-typedef struct _ATOM_LCD_INFO_V13
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  ATOM_DTD_FORMAT     sLCDTiming;
-  USHORT              usExtInfoTableOffset;
-  USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
-  ULONG               ulReserved0;
-  UCHAR               ucLCD_Misc;                // Reorganized in V13
-                                                 // Bit0: {=0:single, =1:dual},
-                                                 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888}  // was {=0:666RGB, =1:888RGB},
-                                                 // Bit3:2: {Grey level}
-                                                 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 
-                                                 // Bit7   Reserved.  was for ATOM_PANEL_MISC_API_ENABLED, still need it?  
-  UCHAR               ucPanelDefaultRefreshRate;
-  UCHAR               ucPanelIdentification;
-  UCHAR               ucSS_Id;
-  USHORT              usLCDVenderID;
-  USHORT              usLCDProductID;
-  UCHAR               ucLCDPanel_SpecialHandlingCap;  // Reorganized in V13 
-                                                 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
-                                                 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
-                                                 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
-                                                 // Bit7-3: Reserved 
-  UCHAR               ucPanelInfoSize;					 //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
-  USHORT              usBacklightPWM;            //  Backlight PWM in Hz. New in _V13
-
-  UCHAR               ucPowerSequenceDIGONtoDE_in4Ms;
-  UCHAR               ucPowerSequenceDEtoVARY_BL_in4Ms;
-  UCHAR               ucPowerSequenceVARY_BLtoDE_in4Ms;
-  UCHAR               ucPowerSequenceDEtoDIGON_in4Ms;
-
-  UCHAR               ucOffDelay_in4Ms;
-  UCHAR               ucPowerSequenceVARY_BLtoBLON_in4Ms;
-  UCHAR               ucPowerSequenceBLONtoVARY_BL_in4Ms;
-  UCHAR               ucReserved1;
-
-  UCHAR               ucDPCD_eDP_CONFIGURATION_CAP;     // dpcd 0dh
-  UCHAR               ucDPCD_MAX_LINK_RATE;             // dpcd 01h
-  UCHAR               ucDPCD_MAX_LANE_COUNT;            // dpcd 02h
-  UCHAR               ucDPCD_MAX_DOWNSPREAD;            // dpcd 03h
-
-  USHORT              usMaxPclkFreqInSingleLink;        // Max PixelClock frequency in single link mode. 
-  UCHAR               uceDPToLVDSRxId;
-  UCHAR               ucLcdReservd;
-  ULONG               ulReserved[2];
-}ATOM_LCD_INFO_V13;  
-
-#define ATOM_LCD_INFO_LAST  ATOM_LCD_INFO_V13    
-
-//Definitions for ucLCD_Misc
-#define ATOM_PANEL_MISC_V13_DUAL                   0x00000001
-#define ATOM_PANEL_MISC_V13_FPDI                   0x00000002
-#define ATOM_PANEL_MISC_V13_GREY_LEVEL             0x0000000C
-#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT       2
-#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK   0x70
-#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR         0x10
-#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR         0x20
-
-//Color Bit Depth definition in EDID V1.4 @BYTE 14h
-//Bit 6  5  4
-                              //      0  0  0  -  Color bit depth is undefined
-                              //      0  0  1  -  6 Bits per Primary Color
-                              //      0  1  0  -  8 Bits per Primary Color
-                              //      0  1  1  - 10 Bits per Primary Color
-                              //      1  0  0  - 12 Bits per Primary Color
-                              //      1  0  1  - 14 Bits per Primary Color
-                              //      1  1  0  - 16 Bits per Primary Color
-                              //      1  1  1  - Reserved
- 
-//Definitions for ucLCDPanel_SpecialHandlingCap:
-
-//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 
-//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 
-#define	LCDPANEL_CAP_V13_READ_EDID              0x1        // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
-
-//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
-//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
-//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
-#define	LCDPANEL_CAP_V13_DRR_SUPPORTED          0x2        // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
-
-//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
-#define	LCDPANEL_CAP_V13_eDP                    0x4        // = LCDPANEL_CAP_eDP no change comparing to previous version
-
-//uceDPToLVDSRxId
-#define eDP_TO_LVDS_RX_DISABLE                  0x00       // no eDP->LVDS translator chip 
-#define eDP_TO_LVDS_COMMON_ID                   0x01       // common eDP->LVDS translator chip without AMD SW init
-#define eDP_TO_LVDS_RT_ID                       0x02       // RT tanslator which require AMD SW init
-
-typedef struct  _ATOM_PATCH_RECORD_MODE
-{
-  UCHAR     ucRecordType;
-  USHORT    usHDisp;
-  USHORT    usVDisp;
-}ATOM_PATCH_RECORD_MODE;
-
-typedef struct  _ATOM_LCD_RTS_RECORD
-{
-  UCHAR     ucRecordType;
-  UCHAR     ucRTSValue;
-}ATOM_LCD_RTS_RECORD;
-
-//!! If the record below exits, it shoud always be the first record for easy use in command table!!! 
-// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
-typedef struct  _ATOM_LCD_MODE_CONTROL_CAP
-{
-  UCHAR     ucRecordType;
-  USHORT    usLCDCap;
-}ATOM_LCD_MODE_CONTROL_CAP;
-
-#define LCD_MODE_CAP_BL_OFF                   1
-#define LCD_MODE_CAP_CRTC_OFF                 2
-#define LCD_MODE_CAP_PANEL_OFF                4
-
-typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
-{
-  UCHAR ucRecordType;
-  UCHAR ucFakeEDIDLength;
-  UCHAR ucFakeEDIDString[1];    // This actually has ucFakeEdidLength elements.
-} ATOM_FAKE_EDID_PATCH_RECORD;
-
-typedef struct  _ATOM_PANEL_RESOLUTION_PATCH_RECORD
-{
-   UCHAR    ucRecordType;
-   USHORT		usHSize;
-   USHORT		usVSize;
-}ATOM_PANEL_RESOLUTION_PATCH_RECORD;
-
-#define LCD_MODE_PATCH_RECORD_MODE_TYPE       1
-#define LCD_RTS_RECORD_TYPE                   2
-#define LCD_CAP_RECORD_TYPE                   3
-#define LCD_FAKE_EDID_PATCH_RECORD_TYPE       4
-#define LCD_PANEL_RESOLUTION_RECORD_TYPE      5
-#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE     6
-#define ATOM_RECORD_END_TYPE                  0xFF
-
-/****************************Spread Spectrum Info Table Definitions **********************/
-
-//ucTableFormatRevision=1
-//ucTableContentRevision=2
-typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
-{
-  USHORT              usSpreadSpectrumPercentage; 
-  UCHAR               ucSpreadSpectrumType;	    //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS  Others:TBD
-  UCHAR               ucSS_Step;
-  UCHAR               ucSS_Delay;
-  UCHAR               ucSS_Id;
-  UCHAR               ucRecommendedRef_Div;
-  UCHAR               ucSS_Range;               //it was reserved for V11
-}ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
-
-#define ATOM_MAX_SS_ENTRY                      16
-#define ATOM_DP_SS_ID1												 0x0f1			// SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 
-#define ATOM_DP_SS_ID2												 0x0f2			// SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 
-#define ATOM_LVLINK_2700MHz_SS_ID              0x0f3      // SS ID for LV link translator chip at 2.7Ghz
-#define ATOM_LVLINK_1620MHz_SS_ID              0x0f4      // SS ID for LV link translator chip at 1.62Ghz
-
-
-#define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
-#define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
-#define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
-#define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
-#define ATOM_INTERNAL_SS_MASK                  0x00000000
-#define ATOM_EXTERNAL_SS_MASK                  0x00000002
-#define EXEC_SS_STEP_SIZE_SHIFT                2
-#define EXEC_SS_DELAY_SHIFT                    4    
-#define ACTIVEDATA_TO_BLON_DELAY_SHIFT         4
-
-typedef struct _ATOM_SPREAD_SPECTRUM_INFO
-{ 
-  ATOM_COMMON_TABLE_HEADER	sHeader;
-  ATOM_SPREAD_SPECTRUM_ASSIGNMENT   asSS_Info[ATOM_MAX_SS_ENTRY];
-}ATOM_SPREAD_SPECTRUM_INFO;
-
-/****************************************************************************/	
-// Structure used in AnalogTV_InfoTable (Top level)
-/****************************************************************************/	
-//ucTVBootUpDefaultStd definition:
-
-//ATOM_TV_NTSC                1
-//ATOM_TV_NTSCJ               2
-//ATOM_TV_PAL                 3
-//ATOM_TV_PALM                4
-//ATOM_TV_PALCN               5
-//ATOM_TV_PALN                6
-//ATOM_TV_PAL60               7
-//ATOM_TV_SECAM               8
-
-//ucTVSupportedStd definition:
-#define NTSC_SUPPORT          0x1
-#define NTSCJ_SUPPORT         0x2
-
-#define PAL_SUPPORT           0x4
-#define PALM_SUPPORT          0x8
-#define PALCN_SUPPORT         0x10
-#define PALN_SUPPORT          0x20
-#define PAL60_SUPPORT         0x40
-#define SECAM_SUPPORT         0x80
-
-#define MAX_SUPPORTED_TV_TIMING    2
-
-typedef struct _ATOM_ANALOG_TV_INFO
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  UCHAR                    ucTV_SupportedStandard;
-  UCHAR                    ucTV_BootUpDefaultStandard; 
-  UCHAR                    ucExt_TV_ASIC_ID;
-  UCHAR                    ucExt_TV_ASIC_SlaveAddr;
-  /*ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING];*/
-  ATOM_MODE_TIMING         aModeTimings[MAX_SUPPORTED_TV_TIMING];
-}ATOM_ANALOG_TV_INFO;
-
-#define MAX_SUPPORTED_TV_TIMING_V1_2    3
-
-typedef struct _ATOM_ANALOG_TV_INFO_V1_2
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  UCHAR                    ucTV_SupportedStandard;
-  UCHAR                    ucTV_BootUpDefaultStandard; 
-  UCHAR                    ucExt_TV_ASIC_ID;
-  UCHAR                    ucExt_TV_ASIC_SlaveAddr;
-  ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2];
-}ATOM_ANALOG_TV_INFO_V1_2;
-
-typedef struct _ATOM_DPCD_INFO
-{
-  UCHAR   ucRevisionNumber;        //10h : Revision 1.0; 11h : Revision 1.1   
-  UCHAR   ucMaxLinkRate;           //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
-  UCHAR   ucMaxLane;               //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 
-  UCHAR   ucMaxDownSpread;         //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
-}ATOM_DPCD_INFO;
-
-#define ATOM_DPCD_MAX_LANE_MASK    0x1F
-
-/**************************************************************************/
-// VRAM usage and their defintions
-
-// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
-// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
-// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
-// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
-// To Bios:  ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 
-
-#ifndef VESA_MEMORY_IN_64K_BLOCK
-#define VESA_MEMORY_IN_64K_BLOCK        0x100       //256*64K=16Mb (Max. VESA memory is 16Mb!)
-#endif
-
-#define ATOM_EDID_RAW_DATASIZE          256         //In Bytes
-#define ATOM_HWICON_SURFACE_SIZE        4096        //In Bytes
-#define ATOM_HWICON_INFOTABLE_SIZE      32
-#define MAX_DTD_MODE_IN_VRAM            6
-#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE  (MAX_DTD_MODE_IN_VRAM*28)    //28= (SIZEOF ATOM_DTD_FORMAT) 
-#define ATOM_STD_MODE_SUPPORT_TBL_SIZE  32*8                         //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
-//20 bytes for Encoder Type and DPCD in STD EDID area
-#define DFP_ENCODER_TYPE_OFFSET         (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)    
-#define ATOM_DP_DPCD_OFFSET             (DFP_ENCODER_TYPE_OFFSET + 4 )        
-
-#define ATOM_HWICON1_SURFACE_ADDR       0
-#define ATOM_HWICON2_SURFACE_ADDR       (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
-#define ATOM_HWICON_INFOTABLE_ADDR      (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
-#define ATOM_CRT1_EDID_ADDR             (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
-#define ATOM_CRT1_DTD_MODE_TBL_ADDR     (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_CRT1_STD_MODE_TBL_ADDR	    (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_LCD1_EDID_ADDR             (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_LCD1_DTD_MODE_TBL_ADDR     (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_LCD1_STD_MODE_TBL_ADDR   	(ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_TV1_DTD_MODE_TBL_ADDR      (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_DFP1_EDID_ADDR             (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_DFP1_DTD_MODE_TBL_ADDR     (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_DFP1_STD_MODE_TBL_ADDR	    (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_CRT2_EDID_ADDR             (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_CRT2_DTD_MODE_TBL_ADDR     (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_CRT2_STD_MODE_TBL_ADDR	    (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_LCD2_EDID_ADDR             (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_LCD2_DTD_MODE_TBL_ADDR     (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_LCD2_STD_MODE_TBL_ADDR   	(ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_DFP6_EDID_ADDR             (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_DFP6_DTD_MODE_TBL_ADDR     (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_DFP6_STD_MODE_TBL_ADDR     (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_DFP2_EDID_ADDR             (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_DFP2_DTD_MODE_TBL_ADDR     (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_DFP2_STD_MODE_TBL_ADDR     (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_CV_EDID_ADDR               (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_CV_DTD_MODE_TBL_ADDR       (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_CV_STD_MODE_TBL_ADDR       (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_DFP3_EDID_ADDR             (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_DFP3_DTD_MODE_TBL_ADDR     (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_DFP3_STD_MODE_TBL_ADDR     (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_DFP4_EDID_ADDR             (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_DFP4_DTD_MODE_TBL_ADDR     (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_DFP4_STD_MODE_TBL_ADDR     (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_DFP5_EDID_ADDR             (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_DFP5_DTD_MODE_TBL_ADDR     (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_DFP5_STD_MODE_TBL_ADDR     (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_DP_TRAINING_TBL_ADDR       (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_STACK_STORAGE_START        (ATOM_DP_TRAINING_TBL_ADDR + 1024)       
-#define ATOM_STACK_STORAGE_END          ATOM_STACK_STORAGE_START + 512        
-
-//The size below is in Kb!
-#define ATOM_VRAM_RESERVE_SIZE         ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
-   
-#define ATOM_VRAM_RESERVE_V2_SIZE      32
-
-#define	ATOM_VRAM_OPERATION_FLAGS_MASK         0xC0000000L
-#define ATOM_VRAM_OPERATION_FLAGS_SHIFT        30
-#define	ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION   0x1
-#define	ATOM_VRAM_BLOCK_NEEDS_RESERVATION      0x0
-
-/***********************************************************************************/	
-// Structure used in VRAM_UsageByFirmwareTable
-// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
-//        at running time.   
-// note2: From RV770, the memory is more than 32bit addressable, so we will change 
-//        ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 
-//        exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 
-//        (in offset to start of memory address) is KB aligned instead of byte aligend.
-/***********************************************************************************/	
-// Note3:
-/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter,
-for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can  have:
-
-If (ulStartAddrUsedByFirmware!=0)
-FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
-Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
-else	//Non VGA case
- if (FB_Size<=2Gb)
-    FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
- else
-	  FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
-
-CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
-
-/***********************************************************************************/	
-#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO			1
-
-typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
-{
-  ULONG   ulStartAddrUsedByFirmware;
-  USHORT  usFirmwareUseInKb;
-  USHORT  usReserved;
-}ATOM_FIRMWARE_VRAM_RESERVE_INFO;
-
-typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  ATOM_FIRMWARE_VRAM_RESERVE_INFO	asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
-}ATOM_VRAM_USAGE_BY_FIRMWARE;
-
-// change verion to 1.5, when allow driver to allocate the vram area for command table access. 
-typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
-{
-  ULONG   ulStartAddrUsedByFirmware;
-  USHORT  usFirmwareUseInKb;
-  USHORT  usFBUsedByDrvInKb;
-}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
-
-typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5	asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
-}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
-
-/****************************************************************************/	
-// Structure used in GPIO_Pin_LUTTable
-/****************************************************************************/	
-typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
-{
-  USHORT                   usGpioPin_AIndex;
-  UCHAR                    ucGpioPinBitShift;
-  UCHAR                    ucGPIO_ID;
-}ATOM_GPIO_PIN_ASSIGNMENT;
-
-//ucGPIO_ID pre-define id for multiple usage
-//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable
-#define PP_AC_DC_SWITCH_GPIO_PINID          60
-//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
-#define VDDC_VRHOT_GPIO_PINID               61
-//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled
-#define VDDC_PCC_GPIO_PINID                 62
-
-typedef struct _ATOM_GPIO_PIN_LUT
-{
-  ATOM_COMMON_TABLE_HEADER  sHeader;
-  ATOM_GPIO_PIN_ASSIGNMENT	asGPIO_Pin[1];
-}ATOM_GPIO_PIN_LUT;
-
-/****************************************************************************/	
-// Structure used in ComponentVideoInfoTable	
-/****************************************************************************/	
-#define GPIO_PIN_ACTIVE_HIGH          0x1
-
-#define MAX_SUPPORTED_CV_STANDARDS    5
-
-// definitions for ATOM_D_INFO.ucSettings
-#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK  0x1F    // [4:0]
-#define ATOM_GPIO_SETTINGS_RESERVED_MASK  0x60    // [6:5] = must be zeroed out
-#define ATOM_GPIO_SETTINGS_ACTIVE_MASK    0x80    // [7]
-
-typedef struct _ATOM_GPIO_INFO
-{
-  USHORT  usAOffset;
-  UCHAR   ucSettings;
-  UCHAR   ucReserved;
-}ATOM_GPIO_INFO;
-
-// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
-#define ATOM_CV_RESTRICT_FORMAT_SELECTION           0x2
-
-// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
-#define ATOM_GPIO_DEFAULT_MODE_EN                   0x80 //[7];
-#define ATOM_GPIO_SETTING_PERMODE_MASK              0x7F //[6:0]
-
-// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
-//Line 3 out put 5V.
-#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A       0x01     //represent gpio 3 state for 16:9
-#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B       0x02     //represent gpio 4 state for 16:9
-#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT   0x0   
-
-//Line 3 out put 2.2V              
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04     //represent gpio 3 state for 4:3 Letter box
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08     //represent gpio 4 state for 4:3 Letter box
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2     
-
-//Line 3 out put 0V
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A        0x10     //represent gpio 3 state for 4:3
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B        0x20     //represent gpio 4 state for 4:3
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT    0x4 
-
-#define ATOM_CV_LINE3_ASPECTRATIO_MASK              0x3F     // bit [5:0]
-
-#define ATOM_CV_LINE3_ASPECTRATIO_EXIST             0x80     //bit 7
-
-//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
-#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A   3   //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
-#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B   4   //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
-
-
-typedef struct _ATOM_COMPONENT_VIDEO_INFO
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;
-  USHORT             usMask_PinRegisterIndex;
-  USHORT             usEN_PinRegisterIndex;
-  USHORT             usY_PinRegisterIndex;
-  USHORT             usA_PinRegisterIndex;
-  UCHAR              ucBitShift;
-  UCHAR              ucPinActiveState;  //ucPinActiveState: Bit0=1 active high, =0 active low
-  ATOM_DTD_FORMAT    sReserved;         // must be zeroed out
-  UCHAR              ucMiscInfo;
-  UCHAR              uc480i;
-  UCHAR              uc480p;
-  UCHAR              uc720p;
-  UCHAR              uc1080i;
-  UCHAR              ucLetterBoxMode;
-  UCHAR              ucReserved[3];
-  UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
-  ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
-  ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
-}ATOM_COMPONENT_VIDEO_INFO;
-
-//ucTableFormatRevision=2
-//ucTableContentRevision=1
-typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;
-  UCHAR              ucMiscInfo;
-  UCHAR              uc480i;
-  UCHAR              uc480p;
-  UCHAR              uc720p;
-  UCHAR              uc1080i;
-  UCHAR              ucReserved;
-  UCHAR              ucLetterBoxMode;
-  UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
-  ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
-  ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
-}ATOM_COMPONENT_VIDEO_INFO_V21;
-
-#define ATOM_COMPONENT_VIDEO_INFO_LAST  ATOM_COMPONENT_VIDEO_INFO_V21
-
-/****************************************************************************/	
-// Structure used in object_InfoTable
-/****************************************************************************/	
-typedef struct _ATOM_OBJECT_HEADER
-{ 
-  ATOM_COMMON_TABLE_HEADER	sHeader;
-  USHORT                    usDeviceSupport;
-  USHORT                    usConnectorObjectTableOffset;
-  USHORT                    usRouterObjectTableOffset;
-  USHORT                    usEncoderObjectTableOffset;
-  USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
-  USHORT                    usDisplayPathTableOffset;
-}ATOM_OBJECT_HEADER;
-
-typedef struct _ATOM_OBJECT_HEADER_V3
-{ 
-  ATOM_COMMON_TABLE_HEADER	sHeader;
-  USHORT                    usDeviceSupport;
-  USHORT                    usConnectorObjectTableOffset;
-  USHORT                    usRouterObjectTableOffset;
-  USHORT                    usEncoderObjectTableOffset;
-  USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
-  USHORT                    usDisplayPathTableOffset;
-  USHORT                    usMiscObjectTableOffset;
-}ATOM_OBJECT_HEADER_V3;
-
-typedef struct  _ATOM_DISPLAY_OBJECT_PATH
-{
-  USHORT    usDeviceTag;                                   //supported device 
-  USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
-  USHORT    usConnObjectId;                                //Connector Object ID 
-  USHORT    usGPUObjectId;                                 //GPU ID 
-  USHORT    usGraphicObjIds[1];                             //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
-}ATOM_DISPLAY_OBJECT_PATH;
-
-typedef struct  _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
-{
-  USHORT    usDeviceTag;                                   //supported device 
-  USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
-  USHORT    usConnObjectId;                                //Connector Object ID 
-  USHORT    usGPUObjectId;                                 //GPU ID 
-  USHORT    usGraphicObjIds[2];                            //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 
-}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;
-
-typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
-{
-  UCHAR                           ucNumOfDispPath;
-  UCHAR                           ucVersion;
-  UCHAR                           ucPadding[2];
-  ATOM_DISPLAY_OBJECT_PATH        asDispPath[1];
-}ATOM_DISPLAY_OBJECT_PATH_TABLE;
-
-
-typedef struct _ATOM_OBJECT                                //each object has this structure    
-{
-  USHORT              usObjectID;
-  USHORT              usSrcDstTableOffset;
-  USHORT              usRecordOffset;                     //this pointing to a bunch of records defined below
-  USHORT              usReserved;
-}ATOM_OBJECT;
-
-typedef struct _ATOM_OBJECT_TABLE                         //Above 4 object table offset pointing to a bunch of objects all have this structure     
-{
-  UCHAR               ucNumberOfObjects;
-  UCHAR               ucPadding[3];
-  ATOM_OBJECT         asObjects[1];
-}ATOM_OBJECT_TABLE;
-
-typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT         //usSrcDstTableOffset pointing to this structure
-{
-  UCHAR               ucNumberOfSrc;
-  USHORT              usSrcObjectID[1];
-  UCHAR               ucNumberOfDst;
-  USHORT              usDstObjectID[1];
-}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
-
-
-//Two definitions below are for OPM on MXM module designs
-
-#define EXT_HPDPIN_LUTINDEX_0                   0
-#define EXT_HPDPIN_LUTINDEX_1                   1
-#define EXT_HPDPIN_LUTINDEX_2                   2
-#define EXT_HPDPIN_LUTINDEX_3                   3
-#define EXT_HPDPIN_LUTINDEX_4                   4
-#define EXT_HPDPIN_LUTINDEX_5                   5
-#define EXT_HPDPIN_LUTINDEX_6                   6
-#define EXT_HPDPIN_LUTINDEX_7                   7
-#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES   (EXT_HPDPIN_LUTINDEX_7+1)
-
-#define EXT_AUXDDC_LUTINDEX_0                   0
-#define EXT_AUXDDC_LUTINDEX_1                   1
-#define EXT_AUXDDC_LUTINDEX_2                   2
-#define EXT_AUXDDC_LUTINDEX_3                   3
-#define EXT_AUXDDC_LUTINDEX_4                   4
-#define EXT_AUXDDC_LUTINDEX_5                   5
-#define EXT_AUXDDC_LUTINDEX_6                   6
-#define EXT_AUXDDC_LUTINDEX_7                   7
-#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES   (EXT_AUXDDC_LUTINDEX_7+1)
-
-//ucChannelMapping are defined as following
-//for DP connector, eDP, DP to VGA/LVDS 
-//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
-//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
-//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
-//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
-typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING
-{
-#if ATOM_BIG_ENDIAN
-  UCHAR ucDP_Lane3_Source:2;
-  UCHAR ucDP_Lane2_Source:2;
-  UCHAR ucDP_Lane1_Source:2;
-  UCHAR ucDP_Lane0_Source:2;
-#else
-  UCHAR ucDP_Lane0_Source:2;
-  UCHAR ucDP_Lane1_Source:2;
-  UCHAR ucDP_Lane2_Source:2;
-  UCHAR ucDP_Lane3_Source:2;
-#endif
-}ATOM_DP_CONN_CHANNEL_MAPPING;
-
-//for DVI/HDMI, in dual link case, both links have to have same mapping. 
-//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
-//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
-//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
-//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
-typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING
-{
-#if ATOM_BIG_ENDIAN
-  UCHAR ucDVI_CLK_Source:2;
-  UCHAR ucDVI_DATA0_Source:2;
-  UCHAR ucDVI_DATA1_Source:2;
-  UCHAR ucDVI_DATA2_Source:2;
-#else
-  UCHAR ucDVI_DATA2_Source:2;
-  UCHAR ucDVI_DATA1_Source:2;
-  UCHAR ucDVI_DATA0_Source:2;
-  UCHAR ucDVI_CLK_Source:2;
-#endif
-}ATOM_DVI_CONN_CHANNEL_MAPPING;
-
-typedef struct _EXT_DISPLAY_PATH
-{
-  USHORT  usDeviceTag;                    //A bit vector to show what devices are supported 
-  USHORT  usDeviceACPIEnum;               //16bit device ACPI id. 
-  USHORT  usDeviceConnector;              //A physical connector for displays to plug in, using object connector definitions
-  UCHAR   ucExtAUXDDCLutIndex;            //An index into external AUX/DDC channel LUT
-  UCHAR   ucExtHPDPINLutIndex;            //An index into external HPD pin LUT
-  USHORT  usExtEncoderObjId;              //external encoder object id
-  union{
-    UCHAR   ucChannelMapping;                  // if ucChannelMapping=0, using default one to one mapping
-    ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
-    ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
-  };
-  UCHAR   ucChPNInvert;                   // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
-  USHORT  usCaps;
-  USHORT  usReserved; 
-}EXT_DISPLAY_PATH;
-   
-#define NUMBER_OF_UCHAR_FOR_GUID          16
-#define MAX_NUMBER_OF_EXT_DISPLAY_PATH    7
-
-//usCaps
-#define  EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE          0x01
-#define  EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN        0x02
-
-typedef  struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;
-  UCHAR                    ucGuid [NUMBER_OF_UCHAR_FOR_GUID];     // a GUID is a 16 byte long string
-  EXT_DISPLAY_PATH         sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
-  UCHAR                    ucChecksum;                            // a simple Checksum of the sum of whole structure equal to 0x0. 
-  UCHAR                    uc3DStereoPinId;                       // use for eDP panel
-  UCHAR                    ucRemoteDisplayConfig;
-  UCHAR                    uceDPToLVDSRxId;
-  UCHAR                    ucFixDPVoltageSwing;                   // usCaps[1]=1, this indicate DP_LANE_SET value
-  UCHAR                    Reserved[3];                           // for potential expansion
-}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
-
-//Related definitions, all records are different but they have a commond header
-typedef struct _ATOM_COMMON_RECORD_HEADER
-{
-  UCHAR               ucRecordType;                      //An emun to indicate the record type
-  UCHAR               ucRecordSize;                      //The size of the whole record in byte
-}ATOM_COMMON_RECORD_HEADER;
-
-
-#define ATOM_I2C_RECORD_TYPE                           1         
-#define ATOM_HPD_INT_RECORD_TYPE                       2
-#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE             3
-#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE          4
-#define	ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE	     5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
-#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE          6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
-#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE      7
-#define ATOM_JTAG_RECORD_TYPE                          8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
-#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE              9
-#define ATOM_ENCODER_DVO_CF_RECORD_TYPE               10
-#define ATOM_CONNECTOR_CF_RECORD_TYPE                 11
-#define	ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE	      12
-#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE  13
-#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE	      14
-#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE	15
-#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE          16 //This is for the case when connectors are not known to object table
-#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE          17 //This is for the case when connectors are not known to object table
-#define ATOM_OBJECT_LINK_RECORD_TYPE                   18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
-#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE          19
-#define ATOM_ENCODER_CAP_RECORD_TYPE                   20
-#define ATOM_BRACKET_LAYOUT_RECORD_TYPE                21
-
-//Must be updated when new record type is added,equal to that record definition!
-#define ATOM_MAX_OBJECT_RECORD_NUMBER             ATOM_BRACKET_LAYOUT_RECORD_TYPE
-
-typedef struct  _ATOM_I2C_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  ATOM_I2C_ID_CONFIG          sucI2cId; 
-  UCHAR                       ucI2CAddr;              //The slave address, it's 0 when the record is attached to connector for DDC
-}ATOM_I2C_RECORD;
-
-typedef struct  _ATOM_HPD_INT_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  UCHAR                       ucHPDIntGPIOID;         //Corresponding block in GPIO_PIN_INFO table gives the pin info           
-  UCHAR                       ucPlugged_PinState;
-}ATOM_HPD_INT_RECORD;
-
-
-typedef struct  _ATOM_OUTPUT_PROTECTION_RECORD 
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  UCHAR                       ucProtectionFlag;
-  UCHAR                       ucReserved;
-}ATOM_OUTPUT_PROTECTION_RECORD;
-
-typedef struct  _ATOM_CONNECTOR_DEVICE_TAG
-{
-  ULONG                       ulACPIDeviceEnum;       //Reserved for now
-  USHORT                      usDeviceID;             //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
-  USHORT                      usPadding;
-}ATOM_CONNECTOR_DEVICE_TAG;
-
-typedef struct  _ATOM_CONNECTOR_DEVICE_TAG_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  UCHAR                       ucNumberOfDevice;
-  UCHAR                       ucReserved;
-  ATOM_CONNECTOR_DEVICE_TAG   asDeviceTag[1];         //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
-}ATOM_CONNECTOR_DEVICE_TAG_RECORD;
-
-
-typedef struct  _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  UCHAR						            ucConfigGPIOID;
-  UCHAR						            ucConfigGPIOState;	    //Set to 1 when it's active high to enable external flow in
-  UCHAR                       ucFlowinGPIPID;
-  UCHAR                       ucExtInGPIPID;
-}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
-
-typedef struct  _ATOM_ENCODER_FPGA_CONTROL_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  UCHAR                       ucCTL1GPIO_ID;
-  UCHAR                       ucCTL1GPIOState;        //Set to 1 when it's active high
-  UCHAR                       ucCTL2GPIO_ID;
-  UCHAR                       ucCTL2GPIOState;        //Set to 1 when it's active high
-  UCHAR                       ucCTL3GPIO_ID;
-  UCHAR                       ucCTL3GPIOState;        //Set to 1 when it's active high
-  UCHAR                       ucCTLFPGA_IN_ID;
-  UCHAR                       ucPadding[3];
-}ATOM_ENCODER_FPGA_CONTROL_RECORD;
-
-typedef struct  _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  UCHAR                       ucGPIOID;               //Corresponding block in GPIO_PIN_INFO table gives the pin info 
-  UCHAR                       ucTVActiveState;        //Indicating when the pin==0 or 1 when TV is connected
-}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
-
-typedef struct  _ATOM_JTAG_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  UCHAR                       ucTMSGPIO_ID;
-  UCHAR                       ucTMSGPIOState;         //Set to 1 when it's active high
-  UCHAR                       ucTCKGPIO_ID;
-  UCHAR                       ucTCKGPIOState;         //Set to 1 when it's active high
-  UCHAR                       ucTDOGPIO_ID;
-  UCHAR                       ucTDOGPIOState;         //Set to 1 when it's active high
-  UCHAR                       ucTDIGPIO_ID;
-  UCHAR                       ucTDIGPIOState;         //Set to 1 when it's active high
-  UCHAR                       ucPadding[2];
-}ATOM_JTAG_RECORD;
-
-
-//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
-typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
-{
-  UCHAR                       ucGPIOID;               // GPIO_ID, find the corresponding ID in GPIO_LUT table
-  UCHAR                       ucGPIO_PinState;        // Pin state showing how to set-up the pin
-}ATOM_GPIO_PIN_CONTROL_PAIR;
-
-typedef struct  _ATOM_OBJECT_GPIO_CNTL_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  UCHAR                       ucFlags;                // Future expnadibility
-  UCHAR                       ucNumberOfPins;         // Number of GPIO pins used to control the object
-  ATOM_GPIO_PIN_CONTROL_PAIR  asGpio[1];              // the real gpio pin pair determined by number of pins ucNumberOfPins
-}ATOM_OBJECT_GPIO_CNTL_RECORD;
-
-//Definitions for GPIO pin state 
-#define GPIO_PIN_TYPE_INPUT             0x00
-#define GPIO_PIN_TYPE_OUTPUT            0x10
-#define GPIO_PIN_TYPE_HW_CONTROL        0x20
-
-//For GPIO_PIN_TYPE_OUTPUT the following is defined 
-#define GPIO_PIN_OUTPUT_STATE_MASK      0x01
-#define GPIO_PIN_OUTPUT_STATE_SHIFT     0
-#define GPIO_PIN_STATE_ACTIVE_LOW       0x0
-#define GPIO_PIN_STATE_ACTIVE_HIGH      0x1
-
-// Indexes to GPIO array in GLSync record 
-// GLSync record is for Frame Lock/Gen Lock feature.
-#define ATOM_GPIO_INDEX_GLSYNC_REFCLK    0
-#define ATOM_GPIO_INDEX_GLSYNC_HSYNC     1
-#define ATOM_GPIO_INDEX_GLSYNC_VSYNC     2
-#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ  3
-#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT  4
-#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
-#define ATOM_GPIO_INDEX_GLSYNC_V_RESET   6
-#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7
-#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL  8
-#define ATOM_GPIO_INDEX_GLSYNC_MAX       9
-
-typedef struct  _ATOM_ENCODER_DVO_CF_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  ULONG                       ulStrengthControl;      // DVOA strength control for CF
-  UCHAR                       ucPadding[2];
-}ATOM_ENCODER_DVO_CF_RECORD;
-
-// Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap
-#define ATOM_ENCODER_CAP_RECORD_HBR2                  0x01         // DP1.2 HBR2 is supported by HW encoder
-#define ATOM_ENCODER_CAP_RECORD_HBR2_EN               0x02         // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 
-
-typedef struct  _ATOM_ENCODER_CAP_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  union {
-    USHORT                    usEncoderCap;         
-    struct {
-#if ATOM_BIG_ENDIAN
-      USHORT                  usReserved:14;        // Bit1-15 may be defined for other capability in future
-      USHORT                  usHBR2En:1;           // Bit1 is for DP1.2 HBR2 enable
-      USHORT                  usHBR2Cap:1;          // Bit0 is for DP1.2 HBR2 capability. 
-#else
-      USHORT                  usHBR2Cap:1;          // Bit0 is for DP1.2 HBR2 capability. 
-      USHORT                  usHBR2En:1;           // Bit1 is for DP1.2 HBR2 enable
-      USHORT                  usReserved:14;        // Bit1-15 may be defined for other capability in future
-#endif
-    };
-  }; 
-}ATOM_ENCODER_CAP_RECORD;                             
-
-// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
-#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA   1
-#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB   2
-
-typedef struct  _ATOM_CONNECTOR_CF_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  USHORT                      usMaxPixClk;
-  UCHAR                       ucFlowCntlGpioId;
-  UCHAR                       ucSwapCntlGpioId;
-  UCHAR                       ucConnectedDvoBundle;
-  UCHAR                       ucPadding;
-}ATOM_CONNECTOR_CF_RECORD;
-
-typedef struct  _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-	ATOM_DTD_FORMAT							asTiming;
-}ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
-
-typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;                //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
-  UCHAR                       ucSubConnectorType;     //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
-  UCHAR                       ucReserved;
-}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
-
-
-typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
-{
-	ATOM_COMMON_RECORD_HEADER   sheader;                
-	UCHAR												ucMuxType;							//decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
-	UCHAR												ucMuxControlPin;
-	UCHAR												ucMuxState[2];					//for alligment purpose
-}ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
-
-typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
-{
-	ATOM_COMMON_RECORD_HEADER   sheader;                
-	UCHAR												ucMuxType;
-	UCHAR												ucMuxControlPin;
-	UCHAR												ucMuxState[2];					//for alligment purpose
-}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
-
-// define ucMuxType
-#define ATOM_ROUTER_MUX_PIN_STATE_MASK								0x0f
-#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT		0x01
-
-typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD     //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  UCHAR                       ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES];  //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 
-}ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
-
-typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD  //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  ATOM_I2C_ID_CONFIG          ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES];  //An fixed size array which maps external pins to internal DDC ID
-}ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
-
-typedef struct _ATOM_OBJECT_LINK_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  USHORT                      usObjectID;         //could be connector, encorder or other object in object.h
-}ATOM_OBJECT_LINK_RECORD;
-
-typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  USHORT                      usReserved;
-}ATOM_CONNECTOR_REMOTE_CAP_RECORD;
-
-typedef struct  _ATOM_CONNECTOR_LAYOUT_INFO
-{
-   USHORT usConnectorObjectId;
-   UCHAR  ucConnectorType;
-   UCHAR  ucPosition;
-}ATOM_CONNECTOR_LAYOUT_INFO;
-
-// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
-#define CONNECTOR_TYPE_DVI_D                 1
-#define CONNECTOR_TYPE_DVI_I                 2
-#define CONNECTOR_TYPE_VGA                   3
-#define CONNECTOR_TYPE_HDMI                  4
-#define CONNECTOR_TYPE_DISPLAY_PORT          5
-#define CONNECTOR_TYPE_MINI_DISPLAY_PORT     6
-
-typedef struct  _ATOM_BRACKET_LAYOUT_RECORD
-{
-  ATOM_COMMON_RECORD_HEADER   sheader;
-  UCHAR                       ucLength;
-  UCHAR                       ucWidth;
-  UCHAR                       ucConnNum;
-  UCHAR                       ucReserved;
-  ATOM_CONNECTOR_LAYOUT_INFO  asConnInfo[1];
-}ATOM_BRACKET_LAYOUT_RECORD;
-
-/****************************************************************************/	
-// ASIC voltage data table
-/****************************************************************************/	
-typedef struct  _ATOM_VOLTAGE_INFO_HEADER
-{
-   USHORT   usVDDCBaseLevel;                //In number of 50mv unit
-   USHORT   usReserved;                     //For possible extension table offset
-   UCHAR    ucNumOfVoltageEntries;
-   UCHAR    ucBytesPerVoltageEntry;
-   UCHAR    ucVoltageStep;                  //Indicating in how many mv increament is one step, 0.5mv unit
-   UCHAR    ucDefaultVoltageEntry;
-   UCHAR    ucVoltageControlI2cLine;
-   UCHAR    ucVoltageControlAddress;
-   UCHAR    ucVoltageControlOffset;
-}ATOM_VOLTAGE_INFO_HEADER;
-
-typedef struct  _ATOM_VOLTAGE_INFO
-{
-   ATOM_COMMON_TABLE_HEADER	sHeader; 
-   ATOM_VOLTAGE_INFO_HEADER viHeader;
-   UCHAR    ucVoltageEntries[64];            //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
-}ATOM_VOLTAGE_INFO;
-
-
-typedef struct  _ATOM_VOLTAGE_FORMULA
-{
-   USHORT   usVoltageBaseLevel;             // In number of 1mv unit
-   USHORT   usVoltageStep;                  // Indicating in how many mv increament is one step, 1mv unit
-	 UCHAR		ucNumOfVoltageEntries;					// Number of Voltage Entry, which indicate max Voltage
-	 UCHAR		ucFlag;													// bit0=0 :step is 1mv =1 0.5mv
-	 UCHAR		ucBaseVID;											// if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
-	 UCHAR		ucReserved;
-	 UCHAR		ucVIDAdjustEntries[32];					// 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
-}ATOM_VOLTAGE_FORMULA;
-
-typedef struct  _VOLTAGE_LUT_ENTRY
-{
-	 USHORT		usVoltageCode;									// The Voltage ID, either GPIO or I2C code
-	 USHORT		usVoltageValue;									// The corresponding Voltage Value, in mV
-}VOLTAGE_LUT_ENTRY;
-
-typedef struct  _ATOM_VOLTAGE_FORMULA_V2
-{
-	 UCHAR		ucNumOfVoltageEntries;					// Number of Voltage Entry, which indicate max Voltage
-	 UCHAR		ucReserved[3];
-	 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
-}ATOM_VOLTAGE_FORMULA_V2;
-
-typedef struct _ATOM_VOLTAGE_CONTROL
-{
-	UCHAR		 ucVoltageControlId;							//Indicate it is controlled by I2C or GPIO or HW state machine		
-  UCHAR    ucVoltageControlI2cLine;
-  UCHAR    ucVoltageControlAddress;
-  UCHAR    ucVoltageControlOffset;	 	
-  USHORT   usGpioPin_AIndex;								//GPIO_PAD register index
-  UCHAR    ucGpioPinBitShift[9];						//at most 8 pin support 255 VIDs, termintate with 0xff
-	UCHAR		 ucReserved;
-}ATOM_VOLTAGE_CONTROL;
-
-// Define ucVoltageControlId
-#define	VOLTAGE_CONTROLLED_BY_HW							0x00
-#define	VOLTAGE_CONTROLLED_BY_I2C_MASK				0x7F
-#define	VOLTAGE_CONTROLLED_BY_GPIO						0x80
-#define	VOLTAGE_CONTROL_ID_LM64								0x01									//I2C control, used for R5xx Core Voltage
-#define	VOLTAGE_CONTROL_ID_DAC								0x02									//I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
-#define	VOLTAGE_CONTROL_ID_VT116xM						0x03									//I2C control, used for R6xx Core Voltage
-#define VOLTAGE_CONTROL_ID_DS4402							0x04									
-#define VOLTAGE_CONTROL_ID_UP6266 						0x05									
-#define VOLTAGE_CONTROL_ID_SCORPIO						0x06
-#define	VOLTAGE_CONTROL_ID_VT1556M						0x07									
-#define	VOLTAGE_CONTROL_ID_CHL822x						0x08									
-#define	VOLTAGE_CONTROL_ID_VT1586M						0x09
-#define VOLTAGE_CONTROL_ID_UP1637 						0x0A
-#define	VOLTAGE_CONTROL_ID_CHL8214            0x0B
-#define	VOLTAGE_CONTROL_ID_UP1801             0x0C
-#define	VOLTAGE_CONTROL_ID_ST6788A            0x0D
-#define VOLTAGE_CONTROL_ID_CHLIR3564SVI2      0x0E
-#define VOLTAGE_CONTROL_ID_AD527x      	      0x0F
-#define VOLTAGE_CONTROL_ID_NCP81022    	      0x10
-#define VOLTAGE_CONTROL_ID_LTC2635			  0x11
-
-typedef struct  _ATOM_VOLTAGE_OBJECT
-{
- 	 UCHAR		ucVoltageType;									//Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI	 
-	 UCHAR		ucSize;													//Size of Object	
-	 ATOM_VOLTAGE_CONTROL			asControl;			//describ how to control 	 
- 	 ATOM_VOLTAGE_FORMULA			asFormula;			//Indicate How to convert real Voltage to VID 
-}ATOM_VOLTAGE_OBJECT;
-
-typedef struct  _ATOM_VOLTAGE_OBJECT_V2
-{
- 	 UCHAR		ucVoltageType;									//Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI	 
-	 UCHAR		ucSize;													//Size of Object	
-	 ATOM_VOLTAGE_CONTROL			asControl;			//describ how to control 	 
- 	 ATOM_VOLTAGE_FORMULA_V2	asFormula;			//Indicate How to convert real Voltage to VID 
-}ATOM_VOLTAGE_OBJECT_V2;
-
-typedef struct  _ATOM_VOLTAGE_OBJECT_INFO
-{
-   ATOM_COMMON_TABLE_HEADER	sHeader; 
-	 ATOM_VOLTAGE_OBJECT			asVoltageObj[3];	//Info for Voltage control	  	 
-}ATOM_VOLTAGE_OBJECT_INFO;
-
-typedef struct  _ATOM_VOLTAGE_OBJECT_INFO_V2
-{
-   ATOM_COMMON_TABLE_HEADER	sHeader; 
-	 ATOM_VOLTAGE_OBJECT_V2			asVoltageObj[3];	//Info for Voltage control	  	 
-}ATOM_VOLTAGE_OBJECT_INFO_V2;
-
-typedef struct  _ATOM_LEAKID_VOLTAGE
-{
-	UCHAR		ucLeakageId;
-	UCHAR		ucReserved;
-	USHORT	usVoltage;
-}ATOM_LEAKID_VOLTAGE;
-
-typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
- 	 UCHAR		ucVoltageType;									//Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI	 
-   UCHAR		ucVoltageMode;							    //Indicate voltage control mode: Init/Set/Leakage/Set phase 
-	 USHORT		usSize;													//Size of Object	
-}ATOM_VOLTAGE_OBJECT_HEADER_V3;
-
-// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode
-#define VOLTAGE_OBJ_GPIO_LUT                 0        //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
-#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ          3        //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3
-#define VOLTAGE_OBJ_PHASE_LUT                4        //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
-#define VOLTAGE_OBJ_SVID2                    7        //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3
-#define VOLTAGE_OBJ_EVV                      8 
-#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT     0x10     //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
-#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT   0x11     //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
-#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT  0x12     //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
-
-typedef struct  _VOLTAGE_LUT_ENTRY_V2
-{
-	 ULONG		ulVoltageId;									  // The Voltage ID which is used to program GPIO register
-	 USHORT		usVoltageValue;									// The corresponding Voltage Value, in mV
-}VOLTAGE_LUT_ENTRY_V2;
-
-typedef struct  _LEAKAGE_VOLTAGE_LUT_ENTRY_V2
-{
-  USHORT	usVoltageLevel; 							  // The Voltage ID which is used to program GPIO register
-  USHORT  usVoltageId;                    
-	USHORT	usLeakageId;									  // The corresponding Voltage Value, in mV
-}LEAKAGE_VOLTAGE_LUT_ENTRY_V2;
-
-typedef struct  _ATOM_I2C_VOLTAGE_OBJECT_V3
-{
-   ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
-   UCHAR	ucVoltageRegulatorId;					  //Indicate Voltage Regulator Id
-   UCHAR    ucVoltageControlI2cLine;
-   UCHAR    ucVoltageControlAddress;
-   UCHAR    ucVoltageControlOffset;	 	
-   ULONG    ulReserved;
-   VOLTAGE_LUT_ENTRY asVolI2cLut[1];        // end with 0xff
-}ATOM_I2C_VOLTAGE_OBJECT_V3;
-
-// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
-#define VOLTAGE_DATA_ONE_BYTE                0
-#define VOLTAGE_DATA_TWO_BYTE                1
-
-typedef struct  _ATOM_GPIO_VOLTAGE_OBJECT_V3
-{
-   ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;   // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
-   UCHAR    ucVoltageGpioCntlId;         // default is 0 which indicate control through CG VID mode 
-   UCHAR    ucGpioEntryNum;              // indiate the entry numbers of Votlage/Gpio value Look up table
-   UCHAR    ucPhaseDelay;                // phase delay in unit of micro second
-   UCHAR    ucReserved;   
-   ULONG    ulGpioMaskVal;               // GPIO Mask value
-   VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];   
-}ATOM_GPIO_VOLTAGE_OBJECT_V3;
-
-typedef struct  _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
-{
-   ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = 0x10/0x11/0x12
-   UCHAR    ucLeakageCntlId;             // default is 0
-   UCHAR    ucLeakageEntryNum;           // indicate the entry number of LeakageId/Voltage Lut table
-   UCHAR    ucReserved[2];               
-   ULONG    ulMaxVoltageLevel;
-   LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1];   
-}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3;
-
-
-typedef struct  _ATOM_SVID2_VOLTAGE_OBJECT_V3
-{
-   ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = VOLTAGE_OBJ_SVID2
-// 14:7  PSI0_VID
-// 6  PSI0_EN
-// 5  PSI1
-// 4:2  load line slope trim. 
-// 1:0  offset trim, 
-   USHORT   usLoadLine_PSI;    
-// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31
-   UCHAR    ucSVDGpioId;     //0~31 indicate GPIO0~31
-   UCHAR    ucSVCGpioId;     //0~31 indicate GPIO0~31
-   ULONG    ulReserved;
-}ATOM_SVID2_VOLTAGE_OBJECT_V3;
-
-typedef union _ATOM_VOLTAGE_OBJECT_V3{
-  ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj;
-  ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj;
-  ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj;
-  ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj;
-}ATOM_VOLTAGE_OBJECT_V3;
-
-typedef struct  _ATOM_VOLTAGE_OBJECT_INFO_V3_1
-{
-   ATOM_COMMON_TABLE_HEADER	sHeader; 
-	 ATOM_VOLTAGE_OBJECT_V3			asVoltageObj[3];	//Info for Voltage control	  	 
-}ATOM_VOLTAGE_OBJECT_INFO_V3_1;
-
-typedef struct  _ATOM_ASIC_PROFILE_VOLTAGE
-{
-	UCHAR		ucProfileId;
-	UCHAR		ucReserved;
-	USHORT	usSize;
-	USHORT	usEfuseSpareStartAddr;
-	USHORT	usFuseIndex[8];												//from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 
-	ATOM_LEAKID_VOLTAGE					asLeakVol[2];			//Leakid and relatd voltage
-}ATOM_ASIC_PROFILE_VOLTAGE;
-
-//ucProfileId
-#define	ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE			1		
-#define	ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE			1
-#define	ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE					2
-
-typedef struct  _ATOM_ASIC_PROFILING_INFO
-{
-  ATOM_COMMON_TABLE_HEADER			asHeader; 
-	ATOM_ASIC_PROFILE_VOLTAGE			asVoltage;
-}ATOM_ASIC_PROFILING_INFO;
-
-typedef struct  _ATOM_ASIC_PROFILING_INFO_V2_1
-{
-  ATOM_COMMON_TABLE_HEADER			asHeader; 
-  UCHAR  ucLeakageBinNum;                // indicate the entry number of LeakageId/Voltage Lut table
-  USHORT usLeakageBinArrayOffset;        // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) 
-
-  UCHAR  ucElbVDDC_Num;               
-  USHORT usElbVDDC_IdArrayOffset;        // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 )
-  USHORT usElbVDDC_LevelArrayOffset;     // offset of 2 dimension voltage level USHORT array
-
-  UCHAR  ucElbVDDCI_Num;
-  USHORT usElbVDDCI_IdArrayOffset;       // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 )
-  USHORT usElbVDDCI_LevelArrayOffset;    // offset of 2 dimension voltage level USHORT array
-}ATOM_ASIC_PROFILING_INFO_V2_1;
-
-typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_1
-{
-  ATOM_COMMON_TABLE_HEADER         asHeader; 
-  ULONG  ulEvvDerateTdp;
-  ULONG  ulEvvDerateTdc;
-  ULONG  ulBoardCoreTemp;
-  ULONG  ulMaxVddc;
-  ULONG  ulMinVddc;
-  ULONG  ulLoadLineSlop;
-  ULONG  ulLeakageTemp;
-  ULONG  ulLeakageVoltage;
-  ULONG  ulCACmEncodeRange;
-  ULONG  ulCACmEncodeAverage;
-  ULONG  ulCACbEncodeRange;
-  ULONG  ulCACbEncodeAverage;
-  ULONG  ulKt_bEncodeRange;
-  ULONG  ulKt_bEncodeAverage;
-  ULONG  ulKv_mEncodeRange;
-  ULONG  ulKv_mEncodeAverage;
-  ULONG  ulKv_bEncodeRange;
-  ULONG  ulKv_bEncodeAverage;
-  ULONG  ulLkgEncodeLn_MaxDivMin;
-  ULONG  ulLkgEncodeMin;
-  ULONG  ulEfuseLogisticAlpha;
-  USHORT usPowerDpm0;
-  USHORT usCurrentDpm0;
-  USHORT usPowerDpm1;
-  USHORT usCurrentDpm1;
-  USHORT usPowerDpm2;
-  USHORT usCurrentDpm2;
-  USHORT usPowerDpm3;
-  USHORT usCurrentDpm3;
-  USHORT usPowerDpm4;
-  USHORT usCurrentDpm4;
-  USHORT usPowerDpm5;
-  USHORT usCurrentDpm5;
-  USHORT usPowerDpm6;
-  USHORT usCurrentDpm6;
-  USHORT usPowerDpm7;
-  USHORT usCurrentDpm7;
-}ATOM_ASIC_PROFILING_INFO_V3_1;
-
-
-typedef struct _ATOM_POWER_SOURCE_OBJECT
-{
-	UCHAR	ucPwrSrcId;													// Power source
-	UCHAR	ucPwrSensorType;										// GPIO, I2C or none
-	UCHAR	ucPwrSensId;											  // if GPIO detect, it is GPIO id,  if I2C detect, it is I2C id
-	UCHAR	ucPwrSensSlaveAddr;									// Slave address if I2C detect
-	UCHAR ucPwrSensRegIndex;									// I2C register Index if I2C detect
-	UCHAR ucPwrSensRegBitMask;								// detect which bit is used if I2C detect
-	UCHAR	ucPwrSensActiveState;								// high active or low active
-	UCHAR	ucReserve[3];												// reserve		
-	USHORT usSensPwr;													// in unit of watt
-}ATOM_POWER_SOURCE_OBJECT;
-
-typedef struct _ATOM_POWER_SOURCE_INFO
-{
-		ATOM_COMMON_TABLE_HEADER		asHeader;
-		UCHAR												asPwrbehave[16];
-		ATOM_POWER_SOURCE_OBJECT		asPwrObj[1];
-}ATOM_POWER_SOURCE_INFO;
-
-
-//Define ucPwrSrcId
-#define POWERSOURCE_PCIE_ID1						0x00
-#define POWERSOURCE_6PIN_CONNECTOR_ID1	0x01
-#define POWERSOURCE_8PIN_CONNECTOR_ID1	0x02
-#define POWERSOURCE_6PIN_CONNECTOR_ID2	0x04
-#define POWERSOURCE_8PIN_CONNECTOR_ID2	0x08
-
-//define ucPwrSensorId
-#define POWER_SENSOR_ALWAYS							0x00
-#define POWER_SENSOR_GPIO								0x01
-#define POWER_SENSOR_I2C								0x02
-
-typedef struct _ATOM_CLK_VOLT_CAPABILITY
-{
-  ULONG      ulVoltageIndex;                      // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table        
-  ULONG      ulMaximumSupportedCLK;               // Maximum clock supported with specified voltage index, unit in 10kHz
-}ATOM_CLK_VOLT_CAPABILITY;
-
-typedef struct _ATOM_AVAILABLE_SCLK_LIST
-{
-  ULONG      ulSupportedSCLK;               // Maximum clock supported with specified voltage index,  unit in 10kHz
-  USHORT     usVoltageIndex;                // The Voltage Index indicated by FUSE for specified SCLK  
-  USHORT     usVoltageID;                   // The Voltage ID indicated by FUSE for specified SCLK 
-}ATOM_AVAILABLE_SCLK_LIST;
-
-// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition
-#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE             1       // refer to ulSystemConfig bit[0]
-
-// this IntegrateSystemInfoTable is used for Liano/Ontario APU
-typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
-{
-  ATOM_COMMON_TABLE_HEADER   sHeader;
-  ULONG  ulBootUpEngineClock;
-  ULONG  ulDentistVCOFreq;          
-  ULONG  ulBootUpUMAClock;          
-  ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];            
-  ULONG  ulBootUpReqDisplayVector;
-  ULONG  ulOtherDisplayMisc;
-  ULONG  ulGPUCapInfo;
-  ULONG  ulSB_MMIO_Base_Addr;
-  USHORT usRequestedPWMFreqInHz;
-  UCHAR  ucHtcTmpLmt;   
-  UCHAR  ucHtcHystLmt;
-  ULONG  ulMinEngineClock;           
-  ULONG  ulSystemConfig;            
-  ULONG  ulCPUCapInfo;              
-  USHORT usNBP0Voltage;               
-  USHORT usNBP1Voltage;
-  USHORT usBootUpNBVoltage;                       
-  USHORT usExtDispConnInfoOffset;
-  USHORT usPanelRefreshRateRange;     
-  UCHAR  ucMemoryType;  
-  UCHAR  ucUMAChannelNumber;
-  ULONG  ulCSR_M3_ARB_CNTL_DEFAULT[10];  
-  ULONG  ulCSR_M3_ARB_CNTL_UVD[10]; 
-  ULONG  ulCSR_M3_ARB_CNTL_FS3D[10];
-  ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
-  ULONG  ulGMCRestoreResetTime;
-  ULONG  ulMinimumNClk;
-  ULONG  ulIdleNClk;
-  ULONG  ulDDR_DLL_PowerUpTime;
-  ULONG  ulDDR_PLL_PowerUpTime;
-  USHORT usPCIEClkSSPercentage;
-  USHORT usPCIEClkSSType;
-  USHORT usLvdsSSPercentage;
-  USHORT usLvdsSSpreadRateIn10Hz;
-  USHORT usHDMISSPercentage;
-  USHORT usHDMISSpreadRateIn10Hz;
-  USHORT usDVISSPercentage;
-  USHORT usDVISSpreadRateIn10Hz;
-  ULONG  SclkDpmBoostMargin;
-  ULONG  SclkDpmThrottleMargin;
-  USHORT SclkDpmTdpLimitPG; 
-  USHORT SclkDpmTdpLimitBoost;
-  ULONG  ulBoostEngineCLock;
-  UCHAR  ulBoostVid_2bit;  
-  UCHAR  EnableBoost;
-  USHORT GnbTdpLimit;
-  USHORT usMaxLVDSPclkFreqInSingleLink;
-  UCHAR  ucLvdsMisc;
-  UCHAR  ucLVDSReserved;
-  ULONG  ulReserved3[15]; 
-  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;   
-}ATOM_INTEGRATED_SYSTEM_INFO_V6;   
-
-// ulGPUCapInfo
-#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE       0x01
-#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION          0x08
-
-//ucLVDSMisc:                   
-#define SYS_INFO_LVDSMISC__888_FPDI_MODE                                             0x01
-#define SYS_INFO_LVDSMISC__DL_CH_SWAP                                                0x02
-#define SYS_INFO_LVDSMISC__888_BPC                                                   0x04
-#define SYS_INFO_LVDSMISC__OVERRIDE_EN                                               0x08
-#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW                                           0x10
-// new since Trinity
-#define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN                               0x20
-
-// not used any more
-#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW                                          0x04
-#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW                                          0x08
-
-/**********************************************************************************************************************
-  ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
-ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
-ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit. 
-ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit. 
-sDISPCLK_Voltage:                 Report Display clock voltage requirement.
- 
-ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
-                                  ATOM_DEVICE_CRT1_SUPPORT                  0x0001
-                                  ATOM_DEVICE_CRT2_SUPPORT                  0x0010
-                                  ATOM_DEVICE_DFP1_SUPPORT                  0x0008 
-                                  ATOM_DEVICE_DFP6_SUPPORT                  0x0040 
-                                  ATOM_DEVICE_DFP2_SUPPORT                  0x0080       
-                                  ATOM_DEVICE_DFP3_SUPPORT                  0x0200       
-                                  ATOM_DEVICE_DFP4_SUPPORT                  0x0400        
-                                  ATOM_DEVICE_DFP5_SUPPORT                  0x0800
-                                  ATOM_DEVICE_LCD1_SUPPORT                  0x0002
-ulOtherDisplayMisc:      	        Other display related flags, not defined yet. 
-ulGPUCapInfo:                     bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
-                                        =1: TMDS/HDMI Coherent Mode use signel PLL mode.
-                                  bit[3]=0: Enable HW AUX mode detection logic
-                                        =1: Disable HW AUX mode dettion logic
-ulSB_MMIO_Base_Addr:              Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
-
-usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 
-                                  Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
-                                  
-                                  When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
-                                  1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
-                                  VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
-                                  Changing BL using VBIOS function is functional in both driver and non-driver present environment; 
-                                  and enabling VariBri under the driver environment from PP table is optional.
-
-                                  2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
-                                  that BL control from GPU is expected.
-                                  VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
-                                  Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
-                                  it's per platform 
-                                  and enabling VariBri under the driver environment from PP table is optional.
-
-ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt. 
-                                  Threshold on value to enter HTC_active state.
-ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt. 
-                                  To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
-ulMinEngineClock:                 Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
-ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled 
-                                        =1: PCIE Power Gating Enabled
-                                  Bit[1]=0: DDR-DLL shut-down feature disabled.
-                                         1: DDR-DLL shut-down feature enabled.
-                                  Bit[2]=0: DDR-PLL Power down feature disabled.
-                                         1: DDR-PLL Power down feature enabled.                                 
-ulCPUCapInfo:                     TBD
-usNBP0Voltage:                    VID for voltage on NB P0 State
-usNBP1Voltage:                    VID for voltage on NB P1 State  
-usBootUpNBVoltage:                Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
-usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
-usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
-                                  to indicate a range.
-                                  SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
-                                  SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
-                                  SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
-                                  SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
-ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
-ucUMAChannelNumber:      	        System memory channel numbers. 
-ulCSR_M3_ARB_CNTL_DEFAULT[10]:    Arrays with values for CSR M3 arbiter for default
-ulCSR_M3_ARB_CNTL_UVD[10]:        Arrays with values for CSR M3 arbiter for UVD playback.
-ulCSR_M3_ARB_CNTL_FS3D[10]:       Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
-sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high  
-ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 
-ulMinimumNClk:                    Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 
-ulIdleNClk:                       NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
-ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
-ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
-usPCIEClkSSPercentage:            PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
-usPCIEClkSSType:                  PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread.
-usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 
-usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 
-usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting. 
-usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting. 
-usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting. 
-usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting. 
-usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
-ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
-                                  [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
-                                  [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
-                                  [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
-                                  [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
-**********************************************************************************************************************/
-
-// this Table is used for Liano/Ontario APU
-typedef struct _ATOM_FUSION_SYSTEM_INFO_V1
-{
-  ATOM_INTEGRATED_SYSTEM_INFO_V6    sIntegratedSysInfo;   
-  ULONG  ulPowerplayTable[128];  
-}ATOM_FUSION_SYSTEM_INFO_V1; 
-
-
-typedef struct _ATOM_TDP_CONFIG_BITS
-{
-#if ATOM_BIG_ENDIAN
-  ULONG   uReserved:2;
-  ULONG   uTDP_Value:14;  // Original TDP value in tens of milli watts
-  ULONG   uCTDP_Value:14; // Override value in tens of milli watts
-  ULONG   uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
-#else
-  ULONG   uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
-  ULONG   uCTDP_Value:14; // Override value in tens of milli watts
-  ULONG   uTDP_Value:14;  // Original TDP value in tens of milli watts
-  ULONG   uReserved:2;
-#endif
-}ATOM_TDP_CONFIG_BITS;
-
-typedef union _ATOM_TDP_CONFIG
-{
-  ATOM_TDP_CONFIG_BITS TDP_config;
-  ULONG            TDP_config_all;
-}ATOM_TDP_CONFIG;
-
-/**********************************************************************************************************************
-  ATOM_FUSION_SYSTEM_INFO_V1 Description
-sIntegratedSysInfo:               refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
-ulPowerplayTable[128]:            This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]    
-**********************************************************************************************************************/ 
-
-// this IntegrateSystemInfoTable is used for Trinity APU
-typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
-{
-  ATOM_COMMON_TABLE_HEADER   sHeader;
-  ULONG  ulBootUpEngineClock;
-  ULONG  ulDentistVCOFreq;
-  ULONG  ulBootUpUMAClock;
-  ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];
-  ULONG  ulBootUpReqDisplayVector;
-  ULONG  ulOtherDisplayMisc;
-  ULONG  ulGPUCapInfo;
-  ULONG  ulSB_MMIO_Base_Addr;
-  USHORT usRequestedPWMFreqInHz;
-  UCHAR  ucHtcTmpLmt;
-  UCHAR  ucHtcHystLmt;
-  ULONG  ulMinEngineClock;
-  ULONG  ulSystemConfig;            
-  ULONG  ulCPUCapInfo;
-  USHORT usNBP0Voltage;               
-  USHORT usNBP1Voltage;
-  USHORT usBootUpNBVoltage;                       
-  USHORT usExtDispConnInfoOffset;
-  USHORT usPanelRefreshRateRange;     
-  UCHAR  ucMemoryType;  
-  UCHAR  ucUMAChannelNumber;
-  UCHAR  strVBIOSMsg[40];
-  ATOM_TDP_CONFIG  asTdpConfig;
-  ULONG  ulReserved[19];
-  ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
-  ULONG  ulGMCRestoreResetTime;
-  ULONG  ulMinimumNClk;
-  ULONG  ulIdleNClk;
-  ULONG  ulDDR_DLL_PowerUpTime;
-  ULONG  ulDDR_PLL_PowerUpTime;
-  USHORT usPCIEClkSSPercentage;
-  USHORT usPCIEClkSSType;
-  USHORT usLvdsSSPercentage;
-  USHORT usLvdsSSpreadRateIn10Hz;
-  USHORT usHDMISSPercentage;
-  USHORT usHDMISSpreadRateIn10Hz;
-  USHORT usDVISSPercentage;
-  USHORT usDVISSpreadRateIn10Hz;
-  ULONG  SclkDpmBoostMargin;
-  ULONG  SclkDpmThrottleMargin;
-  USHORT SclkDpmTdpLimitPG; 
-  USHORT SclkDpmTdpLimitBoost;
-  ULONG  ulBoostEngineCLock;
-  UCHAR  ulBoostVid_2bit;  
-  UCHAR  EnableBoost;
-  USHORT GnbTdpLimit;
-  USHORT usMaxLVDSPclkFreqInSingleLink;
-  UCHAR  ucLvdsMisc;
-  UCHAR  ucTravisLVDSVolAdjust;
-  UCHAR  ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
-  UCHAR  ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
-  UCHAR  ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
-  UCHAR  ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
-  UCHAR  ucLVDSOffToOnDelay_in4Ms;
-  UCHAR  ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
-  UCHAR  ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
-  UCHAR  ucMinAllowedBL_Level;
-  ULONG  ulLCDBitDepthControlVal;
-  ULONG  ulNbpStateMemclkFreq[4];
-  USHORT usNBP2Voltage;               
-  USHORT usNBP3Voltage;
-  ULONG  ulNbpStateNClkFreq[4];
-  UCHAR  ucNBDPMEnable;
-  UCHAR  ucReserved[3];
-  UCHAR  ucDPMState0VclkFid;
-  UCHAR  ucDPMState0DclkFid;
-  UCHAR  ucDPMState1VclkFid;
-  UCHAR  ucDPMState1DclkFid;
-  UCHAR  ucDPMState2VclkFid;
-  UCHAR  ucDPMState2DclkFid;
-  UCHAR  ucDPMState3VclkFid;
-  UCHAR  ucDPMState3DclkFid;
-  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
-}ATOM_INTEGRATED_SYSTEM_INFO_V1_7;
-
-// ulOtherDisplayMisc
-#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT            0x01
-#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT  0x02
-#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT       0x04
-#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT                         0x08
-
-// ulGPUCapInfo
-#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE                0x01
-#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE                               0x02
-#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS                               0x10
-
-/**********************************************************************************************************************
-  ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description
-ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
-ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit. 
-ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit. 
-sDISPCLK_Voltage:                 Report Display clock voltage requirement.
- 
-ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Trinity projects:
-                                  ATOM_DEVICE_CRT1_SUPPORT                  0x0001
-                                  ATOM_DEVICE_DFP1_SUPPORT                  0x0008 
-                                  ATOM_DEVICE_DFP6_SUPPORT                  0x0040 
-                                  ATOM_DEVICE_DFP2_SUPPORT                  0x0080       
-                                  ATOM_DEVICE_DFP3_SUPPORT                  0x0200       
-                                  ATOM_DEVICE_DFP4_SUPPORT                  0x0400        
-                                  ATOM_DEVICE_DFP5_SUPPORT                  0x0800
-                                  ATOM_DEVICE_LCD1_SUPPORT                  0x0002
-ulOtherDisplayMisc:      	        bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 
-                                        =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 
-                                  bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
-                                        =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
-                                  bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
-                                        =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
-                                  bit[3]=0: VBIOS fast boot is disable
-                                        =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
-ulGPUCapInfo:                     bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
-                                        =1: TMDS/HDMI Coherent Mode use signel PLL mode.
-                                  bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
-                                        =1: DP mode use single PLL mode
-                                  bit[3]=0: Enable AUX HW mode detection logic
-                                        =1: Disable AUX HW mode detection logic
-                                      
-ulSB_MMIO_Base_Addr:              Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
-
-usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 
-                                  Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
-                                  
-                                  When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
-                                  1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
-                                  VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
-                                  Changing BL using VBIOS function is functional in both driver and non-driver present environment; 
-                                  and enabling VariBri under the driver environment from PP table is optional.
-
-                                  2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
-                                  that BL control from GPU is expected.
-                                  VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
-                                  Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
-                                  it's per platform 
-                                  and enabling VariBri under the driver environment from PP table is optional.
-
-ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt. 
-                                  Threshold on value to enter HTC_active state.
-ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt. 
-                                  To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
-ulMinEngineClock:                 Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
-ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled 
-                                        =1: PCIE Power Gating Enabled
-                                  Bit[1]=0: DDR-DLL shut-down feature disabled.
-                                         1: DDR-DLL shut-down feature enabled.
-                                  Bit[2]=0: DDR-PLL Power down feature disabled.
-                                         1: DDR-PLL Power down feature enabled.                                 
-ulCPUCapInfo:                     TBD
-usNBP0Voltage:                    VID for voltage on NB P0 State
-usNBP1Voltage:                    VID for voltage on NB P1 State  
-usNBP2Voltage:                    VID for voltage on NB P2 State
-usNBP3Voltage:                    VID for voltage on NB P3 State  
-usBootUpNBVoltage:                Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
-usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
-usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
-                                  to indicate a range.
-                                  SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
-                                  SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
-                                  SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
-                                  SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
-ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
-ucUMAChannelNumber:      	        System memory channel numbers. 
-ulCSR_M3_ARB_CNTL_DEFAULT[10]:    Arrays with values for CSR M3 arbiter for default
-ulCSR_M3_ARB_CNTL_UVD[10]:        Arrays with values for CSR M3 arbiter for UVD playback.
-ulCSR_M3_ARB_CNTL_FS3D[10]:       Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
-sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high  
-ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 
-ulMinimumNClk:                    Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 
-ulIdleNClk:                       NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
-ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
-ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
-usPCIEClkSSPercentage:            PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
-usPCIEClkSSType:                  PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
-usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 
-usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 
-usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting. 
-usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting. 
-usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting. 
-usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting. 
-usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
-ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
-                                  [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
-                                  [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
-                                  [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
-                                  [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
-                                  [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
-ucTravisLVDSVolAdjust             When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 
-                                  value to program Travis register LVDS_CTRL_4
-ucLVDSPwrOnSeqDIGONtoDE_in4Ms:    LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
-                                  =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-ucLVDSPwrOnDEtoVARY_BL_in4Ms:     LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).  
-                                  =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-
-ucLVDSPwrOffVARY_BLtoDE_in4Ms:    LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 
-                                  =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-
-ucLVDSPwrOffDEtoDIGON_in4Ms:      LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 
-                                  =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-
-ucLVDSOffToOnDelay_in4Ms:         LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 
-                                  =0 means to use VBIOS default delay which is 125 ( 500ms ).
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-
-ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
-                                  LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 
-                                  =0 means to use VBIOS default delay which is 0 ( 0ms ).
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-
-ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:  
-                                  LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 
-                                  =0 means to use VBIOS default delay which is 0 ( 0ms ).
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-
-ucMinAllowedBL_Level:             Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 
-
-ulNbpStateMemclkFreq[4]:          system memory clock frequncey in unit of 10Khz in different NB pstate. 
-
-**********************************************************************************************************************/
-
-// this IntegrateSystemInfoTable is used for Kaveri & Kabini APU
-typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8
-{
-  ATOM_COMMON_TABLE_HEADER   sHeader;
-  ULONG  ulBootUpEngineClock;
-  ULONG  ulDentistVCOFreq;
-  ULONG  ulBootUpUMAClock;
-  ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];
-  ULONG  ulBootUpReqDisplayVector;
-  ULONG  ulVBIOSMisc;
-  ULONG  ulGPUCapInfo;
-  ULONG  ulDISP_CLK2Freq;
-  USHORT usRequestedPWMFreqInHz;
-  UCHAR  ucHtcTmpLmt;
-  UCHAR  ucHtcHystLmt;
-  ULONG  ulReserved2;
-  ULONG  ulSystemConfig;            
-  ULONG  ulCPUCapInfo;
-  ULONG  ulReserved3;
-  USHORT usGPUReservedSysMemSize;
-  USHORT usExtDispConnInfoOffset;
-  USHORT usPanelRefreshRateRange;     
-  UCHAR  ucMemoryType;  
-  UCHAR  ucUMAChannelNumber;
-  UCHAR  strVBIOSMsg[40];
-  ATOM_TDP_CONFIG  asTdpConfig;
-  ULONG  ulReserved[19];
-  ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
-  ULONG  ulGMCRestoreResetTime;
-  ULONG  ulReserved4;
-  ULONG  ulIdleNClk;
-  ULONG  ulDDR_DLL_PowerUpTime;
-  ULONG  ulDDR_PLL_PowerUpTime;
-  USHORT usPCIEClkSSPercentage;
-  USHORT usPCIEClkSSType;
-  USHORT usLvdsSSPercentage;
-  USHORT usLvdsSSpreadRateIn10Hz;
-  USHORT usHDMISSPercentage;
-  USHORT usHDMISSpreadRateIn10Hz;
-  USHORT usDVISSPercentage;
-  USHORT usDVISSpreadRateIn10Hz;
-  ULONG  ulGPUReservedSysMemBaseAddrLo;
-  ULONG  ulGPUReservedSysMemBaseAddrHi;
-  ULONG  ulReserved5[3];
-  USHORT usMaxLVDSPclkFreqInSingleLink;
-  UCHAR  ucLvdsMisc;
-  UCHAR  ucTravisLVDSVolAdjust;
-  UCHAR  ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
-  UCHAR  ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
-  UCHAR  ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
-  UCHAR  ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
-  UCHAR  ucLVDSOffToOnDelay_in4Ms;
-  UCHAR  ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
-  UCHAR  ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
-  UCHAR  ucMinAllowedBL_Level;
-  ULONG  ulLCDBitDepthControlVal;
-  ULONG  ulNbpStateMemclkFreq[4];
-  ULONG  ulReserved6;               
-  ULONG  ulNbpStateNClkFreq[4];
-  USHORT usNBPStateVoltage[4];            
-  USHORT usBootUpNBVoltage;   
-  USHORT usReserved2; 
-  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
-}ATOM_INTEGRATED_SYSTEM_INFO_V1_8;
-
-/**********************************************************************************************************************
-  ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description
-ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
-ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit. 
-ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit. 
-sDISPCLK_Voltage:                 Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels).
- 
-ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Trinity projects:
-                                  ATOM_DEVICE_CRT1_SUPPORT                  0x0001
-                                  ATOM_DEVICE_DFP1_SUPPORT                  0x0008
-                                  ATOM_DEVICE_DFP6_SUPPORT                  0x0040
-                                  ATOM_DEVICE_DFP2_SUPPORT                  0x0080
-                                  ATOM_DEVICE_DFP3_SUPPORT                  0x0200
-                                  ATOM_DEVICE_DFP4_SUPPORT                  0x0400
-                                  ATOM_DEVICE_DFP5_SUPPORT                  0x0800
-                                  ATOM_DEVICE_LCD1_SUPPORT                  0x0002
-
-ulVBIOSMisc:      	              Miscellenous flags for VBIOS requirement and interface 
-                                  bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 
-                                        =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
-                                  bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
-                                        =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
-                                  bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
-                                        =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
-                                  bit[3]=0: VBIOS fast boot is disable
-                                        =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
-
-ulGPUCapInfo:                     bit[0~2]= Reserved
-                                  bit[3]=0: Enable AUX HW mode detection logic
-                                        =1: Disable AUX HW mode detection logic
-                                  bit[4]=0: Disable DFS bypass feature
-                                        =1: Enable DFS bypass feature
-
-usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 
-                                  Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
-                                  
-                                  When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
-                                  1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
-                                  VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
-                                  Changing BL using VBIOS function is functional in both driver and non-driver present environment; 
-                                  and enabling VariBri under the driver environment from PP table is optional.
-
-                                  2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
-                                  that BL control from GPU is expected.
-                                  VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
-                                  Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
-                                  it's per platform 
-                                  and enabling VariBri under the driver environment from PP table is optional.
-
-ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state.
-ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt. 
-                                  To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
-
-ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled 
-                                        =1: PCIE Power Gating Enabled
-                                  Bit[1]=0: DDR-DLL shut-down feature disabled.
-                                         1: DDR-DLL shut-down feature enabled.
-                                  Bit[2]=0: DDR-PLL Power down feature disabled.
-                                         1: DDR-PLL Power down feature enabled. 
-                                  Bit[3]=0: GNB DPM is disabled
-                                        =1: GNB DPM is enabled                                
-ulCPUCapInfo:                     TBD
-
-usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
-usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
-                                  to indicate a range.
-                                  SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
-                                  SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
-                                  SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
-                                  SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
-
-ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
-ucUMAChannelNumber:      	        System memory channel numbers. 
-
-strVBIOSMsg[40]:                  VBIOS boot up customized message string 
-
-sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high  
-
-ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 
-ulIdleNClk:                       NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
-ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
-ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
-
-usPCIEClkSSPercentage:            PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
-usPCIEClkSSType:                  PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
-usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 
-usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 
-usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting. 
-usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting. 
-usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting. 
-usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting. 
-
-usGPUReservedSysMemSize:          Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB.
-ulGPUReservedSysMemBaseAddrLo:    Low 32 bits base address to the reserved system memory. 
-ulGPUReservedSysMemBaseAddrHi:    High 32 bits base address to the reserved system memory. 
-
-usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
-ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
-                                  [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
-                                  [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
-                                  [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
-                                  [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
-                                  [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
-ucTravisLVDSVolAdjust             When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 
-                                  value to program Travis register LVDS_CTRL_4
-ucLVDSPwrOnSeqDIGONtoDE_in4Ms:    
-                                  LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
-                                  =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-ucLVDSPwrOnDEtoVARY_BL_in4Ms:     
-                                  LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).  
-                                  =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-ucLVDSPwrOffVARY_BLtoDE_in4Ms:    
-                                  LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 
-                                  =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-ucLVDSPwrOffDEtoDIGON_in4Ms:      
-                                   LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 
-                                  =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-ucLVDSOffToOnDelay_in4Ms:         
-                                  LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 
-                                  =0 means to use VBIOS default delay which is 125 ( 500ms ).
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
-                                  LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 
-                                  =0 means to use VBIOS default delay which is 0 ( 0ms ).
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-
-ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:  
-                                  LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 
-                                  =0 means to use VBIOS default delay which is 0 ( 0ms ).
-                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
-ucMinAllowedBL_Level:             Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 
-
-ulLCDBitDepthControlVal:          GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL
-
-ulNbpStateMemclkFreq[4]:          system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3).
-ulNbpStateNClkFreq[4]:            NB P-State NClk frequency in different NB P-State
-usNBPStateVoltage[4]:             NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
-usBootUpNBVoltage:                NB P-State voltage during boot up before driver loaded 
-sExtDispConnInfo:                 Display connector information table provided to VBIOS
-
-**********************************************************************************************************************/
-
-// this Table is used for Kaveri/Kabini APU
-typedef struct _ATOM_FUSION_SYSTEM_INFO_V2
-{
-  ATOM_INTEGRATED_SYSTEM_INFO_V1_8    sIntegratedSysInfo;       // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
-  ULONG                               ulPowerplayTable[128];    // Update comments here to link new powerplay table definition structure
-}ATOM_FUSION_SYSTEM_INFO_V2; 
-
-
-/**************************************************************************/
-// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
-//Memory SS Info Table
-//Define Memory Clock SS chip ID
-#define ICS91719  1
-#define ICS91720  2
-
-//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
-typedef struct _ATOM_I2C_DATA_RECORD
-{
-  UCHAR         ucNunberOfBytes;                                              //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
-  UCHAR         ucI2CData[1];                                                 //I2C data in bytes, should be less than 16 bytes usually
-}ATOM_I2C_DATA_RECORD;
-
-
-//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
-typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
-{
-  ATOM_I2C_ID_CONFIG_ACCESS       sucI2cId;               //I2C line and HW/SW assisted cap.
-  UCHAR		                        ucSSChipID;             //SS chip being used
-  UCHAR		                        ucSSChipSlaveAddr;      //Slave Address to set up this SS chip
-  UCHAR                           ucNumOfI2CDataRecords;  //number of data block
-  ATOM_I2C_DATA_RECORD            asI2CData[1];  
-}ATOM_I2C_DEVICE_SETUP_INFO;
-
-//==========================================================================================
-typedef struct  _ATOM_ASIC_MVDD_INFO
-{
-  ATOM_COMMON_TABLE_HEADER	      sHeader; 
-  ATOM_I2C_DEVICE_SETUP_INFO      asI2CSetup[1];
-}ATOM_ASIC_MVDD_INFO;
-
-//==========================================================================================
-#define ATOM_MCLK_SS_INFO         ATOM_ASIC_MVDD_INFO
-
-//==========================================================================================
-/**************************************************************************/
-
-typedef struct _ATOM_ASIC_SS_ASSIGNMENT
-{
-	ULONG								ulTargetClockRange;						//Clock Out frequence (VCO ), in unit of 10Khz
-  USHORT              usSpreadSpectrumPercentage;		//in unit of 0.01%
-	USHORT							usSpreadRateInKhz;						//in unit of kHz, modulation freq
-  UCHAR               ucClockIndication;					  //Indicate which clock source needs SS
-	UCHAR								ucSpreadSpectrumMode;					//Bit1=0 Down Spread,=1 Center Spread.
-	UCHAR								ucReserved[2];
-}ATOM_ASIC_SS_ASSIGNMENT;
-
-//Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type.
-//SS is not required or enabled if a match is not found.
-#define ASIC_INTERNAL_MEMORY_SS	         1
-#define ASIC_INTERNAL_ENGINE_SS	         2
-#define ASIC_INTERNAL_UVD_SS             3
-#define ASIC_INTERNAL_SS_ON_TMDS         4
-#define ASIC_INTERNAL_SS_ON_HDMI         5
-#define ASIC_INTERNAL_SS_ON_LVDS         6
-#define ASIC_INTERNAL_SS_ON_DP           7
-#define ASIC_INTERNAL_SS_ON_DCPLL        8
-#define ASIC_EXTERNAL_SS_ON_DP_CLOCK     9
-#define ASIC_INTERNAL_VCE_SS             10
-#define ASIC_INTERNAL_GPUPLL_SS          11
-
-
-typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
-{
-	ULONG								ulTargetClockRange;						//For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
-                                                    //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
-  USHORT              usSpreadSpectrumPercentage;		//in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4
-	USHORT							usSpreadRateIn10Hz;						//in unit of 10Hz, modulation freq
-  UCHAR               ucClockIndication;					  //Indicate which clock source needs SS
-	UCHAR								ucSpreadSpectrumMode;					//Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
-	UCHAR								ucReserved[2];
-}ATOM_ASIC_SS_ASSIGNMENT_V2;
-
-//ucSpreadSpectrumMode
-//#define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
-//#define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
-//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
-//#define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
-//#define ATOM_INTERNAL_SS_MASK                  0x00000000
-//#define ATOM_EXTERNAL_SS_MASK                  0x00000002
-
-typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
-{
-  ATOM_COMMON_TABLE_HEADER	      sHeader; 
-  ATOM_ASIC_SS_ASSIGNMENT		      asSpreadSpectrum[4];
-}ATOM_ASIC_INTERNAL_SS_INFO;
-
-typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
-{
-  ATOM_COMMON_TABLE_HEADER	      sHeader; 
-  ATOM_ASIC_SS_ASSIGNMENT_V2		  asSpreadSpectrum[1];      //this is point only. 
-}ATOM_ASIC_INTERNAL_SS_INFO_V2;
-
-typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
-{
-	ULONG								ulTargetClockRange;						//For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
-                                                    //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
-  USHORT              usSpreadSpectrumPercentage;		//in unit of 0.01%
-	USHORT							usSpreadRateIn10Hz;						//in unit of 10Hz, modulation freq
-  UCHAR               ucClockIndication;					  //Indicate which clock source needs SS
-	UCHAR								ucSpreadSpectrumMode;					//Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
-	UCHAR								ucReserved[2];
-}ATOM_ASIC_SS_ASSIGNMENT_V3;
-
-//ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode
-#define SS_MODE_V3_CENTRE_SPREAD_MASK             0x01
-#define SS_MODE_V3_EXTERNAL_SS_MASK               0x02
-#define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK    0x10
-
-typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
-{
-  ATOM_COMMON_TABLE_HEADER	      sHeader; 
-  ATOM_ASIC_SS_ASSIGNMENT_V3		  asSpreadSpectrum[1];      //this is pointer only. 
-}ATOM_ASIC_INTERNAL_SS_INFO_V3;
-
-
-//==============================Scratch Pad Definition Portion===============================
-#define ATOM_DEVICE_CONNECT_INFO_DEF  0
-#define ATOM_ROM_LOCATION_DEF         1
-#define ATOM_TV_STANDARD_DEF          2
-#define ATOM_ACTIVE_INFO_DEF          3
-#define ATOM_LCD_INFO_DEF             4
-#define ATOM_DOS_REQ_INFO_DEF         5
-#define ATOM_ACC_CHANGE_INFO_DEF      6
-#define ATOM_DOS_MODE_INFO_DEF        7
-#define ATOM_I2C_CHANNEL_STATUS_DEF   8
-#define ATOM_I2C_CHANNEL_STATUS1_DEF  9
-#define ATOM_INTERNAL_TIMER_DEF       10
-
-// BIOS_0_SCRATCH Definition 
-#define ATOM_S0_CRT1_MONO               0x00000001L
-#define ATOM_S0_CRT1_COLOR              0x00000002L
-#define ATOM_S0_CRT1_MASK               (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
-
-#define ATOM_S0_TV1_COMPOSITE_A         0x00000004L
-#define ATOM_S0_TV1_SVIDEO_A            0x00000008L
-#define ATOM_S0_TV1_MASK_A              (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
-
-#define ATOM_S0_CV_A                    0x00000010L
-#define ATOM_S0_CV_DIN_A                0x00000020L
-#define ATOM_S0_CV_MASK_A               (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
-
-
-#define ATOM_S0_CRT2_MONO               0x00000100L
-#define ATOM_S0_CRT2_COLOR              0x00000200L
-#define ATOM_S0_CRT2_MASK               (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
-
-#define ATOM_S0_TV1_COMPOSITE           0x00000400L
-#define ATOM_S0_TV1_SVIDEO              0x00000800L
-#define ATOM_S0_TV1_SCART               0x00004000L
-#define ATOM_S0_TV1_MASK                (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
-
-#define ATOM_S0_CV                      0x00001000L
-#define ATOM_S0_CV_DIN                  0x00002000L
-#define ATOM_S0_CV_MASK                 (ATOM_S0_CV+ATOM_S0_CV_DIN)
-
-#define ATOM_S0_DFP1                    0x00010000L
-#define ATOM_S0_DFP2                    0x00020000L
-#define ATOM_S0_LCD1                    0x00040000L
-#define ATOM_S0_LCD2                    0x00080000L
-#define ATOM_S0_DFP6                    0x00100000L
-#define ATOM_S0_DFP3                    0x00200000L
-#define ATOM_S0_DFP4                    0x00400000L
-#define ATOM_S0_DFP5                    0x00800000L
-
-#define ATOM_S0_DFP_MASK                ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
-
-#define ATOM_S0_FAD_REGISTER_BUG        0x02000000L // If set, indicates we are running a PCIE asic with 
-                                                    // the FAD/HDP reg access bug.  Bit is read by DAL, this is obsolete from RV5xx
-
-#define ATOM_S0_THERMAL_STATE_MASK      0x1C000000L
-#define ATOM_S0_THERMAL_STATE_SHIFT     26
-
-#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
-#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 
-
-#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC     1
-#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC     2
-#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
-#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
-
-//Byte aligned definition for BIOS usage
-#define ATOM_S0_CRT1_MONOb0             0x01
-#define ATOM_S0_CRT1_COLORb0            0x02
-#define ATOM_S0_CRT1_MASKb0             (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
-
-#define ATOM_S0_TV1_COMPOSITEb0         0x04
-#define ATOM_S0_TV1_SVIDEOb0            0x08
-#define ATOM_S0_TV1_MASKb0              (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
-
-#define ATOM_S0_CVb0                    0x10
-#define ATOM_S0_CV_DINb0                0x20
-#define ATOM_S0_CV_MASKb0               (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
-
-#define ATOM_S0_CRT2_MONOb1             0x01
-#define ATOM_S0_CRT2_COLORb1            0x02
-#define ATOM_S0_CRT2_MASKb1             (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
-
-#define ATOM_S0_TV1_COMPOSITEb1         0x04
-#define ATOM_S0_TV1_SVIDEOb1            0x08
-#define ATOM_S0_TV1_SCARTb1             0x40
-#define ATOM_S0_TV1_MASKb1              (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
-
-#define ATOM_S0_CVb1                    0x10
-#define ATOM_S0_CV_DINb1                0x20
-#define ATOM_S0_CV_MASKb1               (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
-
-#define ATOM_S0_DFP1b2                  0x01
-#define ATOM_S0_DFP2b2                  0x02
-#define ATOM_S0_LCD1b2                  0x04
-#define ATOM_S0_LCD2b2                  0x08
-#define ATOM_S0_DFP6b2                  0x10
-#define ATOM_S0_DFP3b2                  0x20
-#define ATOM_S0_DFP4b2                  0x40
-#define ATOM_S0_DFP5b2                  0x80
-
-
-#define ATOM_S0_THERMAL_STATE_MASKb3    0x1C
-#define ATOM_S0_THERMAL_STATE_SHIFTb3   2
-
-#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
-#define ATOM_S0_LCD1_SHIFT              18
-
-// BIOS_1_SCRATCH Definition
-#define ATOM_S1_ROM_LOCATION_MASK       0x0000FFFFL
-#define ATOM_S1_PCI_BUS_DEV_MASK        0xFFFF0000L
-
-//	BIOS_2_SCRATCH Definition
-#define ATOM_S2_TV1_STANDARD_MASK       0x0000000FL
-#define ATOM_S2_CURRENT_BL_LEVEL_MASK   0x0000FF00L
-#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT  8
-
-#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK       0x0C000000L
-#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
-#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE     0x10000000L
-
-#define ATOM_S2_DEVICE_DPMS_STATE       0x00010000L
-#define ATOM_S2_VRI_BRIGHT_ENABLE       0x20000000L
-
-#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE     0x0
-#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE    0x1
-#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE   0x2
-#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE   0x3
-#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
-#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK   0xC0000000L
-
-
-//Byte aligned definition for BIOS usage
-#define ATOM_S2_TV1_STANDARD_MASKb0     0x0F
-#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
-#define ATOM_S2_DEVICE_DPMS_STATEb2     0x01
-
-#define ATOM_S2_DEVICE_DPMS_MASKw1      0x3FF
-#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3     0x0C
-#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3   0x10
-#define ATOM_S2_TMDS_COHERENT_MODEb3    0x10          // used by VBIOS code only, use coherent mode for TMDS/HDMI mode
-#define ATOM_S2_VRI_BRIGHT_ENABLEb3     0x20
-#define ATOM_S2_ROTATION_STATE_MASKb3   0xC0
-
-
-// BIOS_3_SCRATCH Definition
-#define ATOM_S3_CRT1_ACTIVE             0x00000001L
-#define ATOM_S3_LCD1_ACTIVE             0x00000002L
-#define ATOM_S3_TV1_ACTIVE              0x00000004L
-#define ATOM_S3_DFP1_ACTIVE             0x00000008L
-#define ATOM_S3_CRT2_ACTIVE             0x00000010L
-#define ATOM_S3_LCD2_ACTIVE             0x00000020L
-#define ATOM_S3_DFP6_ACTIVE             0x00000040L
-#define ATOM_S3_DFP2_ACTIVE             0x00000080L
-#define ATOM_S3_CV_ACTIVE               0x00000100L
-#define ATOM_S3_DFP3_ACTIVE							0x00000200L
-#define ATOM_S3_DFP4_ACTIVE							0x00000400L
-#define ATOM_S3_DFP5_ACTIVE							0x00000800L
-
-#define ATOM_S3_DEVICE_ACTIVE_MASK      0x00000FFFL
-
-#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE         0x00001000L
-#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
-
-#define ATOM_S3_CRT1_CRTC_ACTIVE        0x00010000L
-#define ATOM_S3_LCD1_CRTC_ACTIVE        0x00020000L
-#define ATOM_S3_TV1_CRTC_ACTIVE         0x00040000L
-#define ATOM_S3_DFP1_CRTC_ACTIVE        0x00080000L
-#define ATOM_S3_CRT2_CRTC_ACTIVE        0x00100000L
-#define ATOM_S3_LCD2_CRTC_ACTIVE        0x00200000L
-#define ATOM_S3_DFP6_CRTC_ACTIVE        0x00400000L
-#define ATOM_S3_DFP2_CRTC_ACTIVE        0x00800000L
-#define ATOM_S3_CV_CRTC_ACTIVE          0x01000000L
-#define ATOM_S3_DFP3_CRTC_ACTIVE				0x02000000L
-#define ATOM_S3_DFP4_CRTC_ACTIVE				0x04000000L
-#define ATOM_S3_DFP5_CRTC_ACTIVE				0x08000000L
-
-#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
-#define ATOM_S3_ASIC_GUI_ENGINE_HUNG    0x20000000L
-//Below two definitions are not supported in pplib, but in the old powerplay in DAL
-#define ATOM_S3_ALLOW_FAST_PWR_SWITCH   0x40000000L
-#define ATOM_S3_RQST_GPU_USE_MIN_PWR    0x80000000L
-
-//Byte aligned definition for BIOS usage
-#define ATOM_S3_CRT1_ACTIVEb0           0x01
-#define ATOM_S3_LCD1_ACTIVEb0           0x02
-#define ATOM_S3_TV1_ACTIVEb0            0x04
-#define ATOM_S3_DFP1_ACTIVEb0           0x08
-#define ATOM_S3_CRT2_ACTIVEb0           0x10
-#define ATOM_S3_LCD2_ACTIVEb0           0x20
-#define ATOM_S3_DFP6_ACTIVEb0           0x40
-#define ATOM_S3_DFP2_ACTIVEb0           0x80
-#define ATOM_S3_CV_ACTIVEb1             0x01
-#define ATOM_S3_DFP3_ACTIVEb1						0x02
-#define ATOM_S3_DFP4_ACTIVEb1						0x04
-#define ATOM_S3_DFP5_ACTIVEb1						0x08
-
-#define ATOM_S3_ACTIVE_CRTC1w0          0xFFF
-
-#define ATOM_S3_CRT1_CRTC_ACTIVEb2      0x01
-#define ATOM_S3_LCD1_CRTC_ACTIVEb2      0x02
-#define ATOM_S3_TV1_CRTC_ACTIVEb2       0x04
-#define ATOM_S3_DFP1_CRTC_ACTIVEb2      0x08
-#define ATOM_S3_CRT2_CRTC_ACTIVEb2      0x10
-#define ATOM_S3_LCD2_CRTC_ACTIVEb2      0x20
-#define ATOM_S3_DFP6_CRTC_ACTIVEb2      0x40
-#define ATOM_S3_DFP2_CRTC_ACTIVEb2      0x80
-#define ATOM_S3_CV_CRTC_ACTIVEb3        0x01
-#define ATOM_S3_DFP3_CRTC_ACTIVEb3			0x02
-#define ATOM_S3_DFP4_CRTC_ACTIVEb3			0x04
-#define ATOM_S3_DFP5_CRTC_ACTIVEb3			0x08
-
-#define ATOM_S3_ACTIVE_CRTC2w1          0xFFF
-
-// BIOS_4_SCRATCH Definition
-#define ATOM_S4_LCD1_PANEL_ID_MASK      0x000000FFL
-#define ATOM_S4_LCD1_REFRESH_MASK       0x0000FF00L
-#define ATOM_S4_LCD1_REFRESH_SHIFT      8
-
-//Byte aligned definition for BIOS usage
-#define ATOM_S4_LCD1_PANEL_ID_MASKb0	  0x0FF
-#define ATOM_S4_LCD1_REFRESH_MASKb1		  ATOM_S4_LCD1_PANEL_ID_MASKb0
-#define ATOM_S4_VRAM_INFO_MASKb2        ATOM_S4_LCD1_PANEL_ID_MASKb0
-
-// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
-#define ATOM_S5_DOS_REQ_CRT1b0          0x01
-#define ATOM_S5_DOS_REQ_LCD1b0          0x02
-#define ATOM_S5_DOS_REQ_TV1b0           0x04
-#define ATOM_S5_DOS_REQ_DFP1b0          0x08
-#define ATOM_S5_DOS_REQ_CRT2b0          0x10
-#define ATOM_S5_DOS_REQ_LCD2b0          0x20
-#define ATOM_S5_DOS_REQ_DFP6b0          0x40
-#define ATOM_S5_DOS_REQ_DFP2b0          0x80
-#define ATOM_S5_DOS_REQ_CVb1            0x01
-#define ATOM_S5_DOS_REQ_DFP3b1					0x02
-#define ATOM_S5_DOS_REQ_DFP4b1					0x04
-#define ATOM_S5_DOS_REQ_DFP5b1					0x08
-
-#define ATOM_S5_DOS_REQ_DEVICEw0        0x0FFF
-
-#define ATOM_S5_DOS_REQ_CRT1            0x0001
-#define ATOM_S5_DOS_REQ_LCD1            0x0002
-#define ATOM_S5_DOS_REQ_TV1             0x0004
-#define ATOM_S5_DOS_REQ_DFP1            0x0008
-#define ATOM_S5_DOS_REQ_CRT2            0x0010
-#define ATOM_S5_DOS_REQ_LCD2            0x0020
-#define ATOM_S5_DOS_REQ_DFP6            0x0040
-#define ATOM_S5_DOS_REQ_DFP2            0x0080
-#define ATOM_S5_DOS_REQ_CV              0x0100
-#define ATOM_S5_DOS_REQ_DFP3            0x0200
-#define ATOM_S5_DOS_REQ_DFP4            0x0400
-#define ATOM_S5_DOS_REQ_DFP5            0x0800
-
-#define ATOM_S5_DOS_FORCE_CRT1b2        ATOM_S5_DOS_REQ_CRT1b0
-#define ATOM_S5_DOS_FORCE_TV1b2         ATOM_S5_DOS_REQ_TV1b0
-#define ATOM_S5_DOS_FORCE_CRT2b2        ATOM_S5_DOS_REQ_CRT2b0
-#define ATOM_S5_DOS_FORCE_CVb3          ATOM_S5_DOS_REQ_CVb1
-#define ATOM_S5_DOS_FORCE_DEVICEw1      (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
-                                        (ATOM_S5_DOS_FORCE_CVb3<<8))
-
-// BIOS_6_SCRATCH Definition
-#define ATOM_S6_DEVICE_CHANGE           0x00000001L
-#define ATOM_S6_SCALER_CHANGE           0x00000002L
-#define ATOM_S6_LID_CHANGE              0x00000004L
-#define ATOM_S6_DOCKING_CHANGE          0x00000008L
-#define ATOM_S6_ACC_MODE                0x00000010L
-#define ATOM_S6_EXT_DESKTOP_MODE        0x00000020L
-#define ATOM_S6_LID_STATE               0x00000040L
-#define ATOM_S6_DOCK_STATE              0x00000080L
-#define ATOM_S6_CRITICAL_STATE          0x00000100L
-#define ATOM_S6_HW_I2C_BUSY_STATE       0x00000200L
-#define ATOM_S6_THERMAL_STATE_CHANGE    0x00000400L
-#define ATOM_S6_INTERRUPT_SET_BY_BIOS   0x00000800L
-#define ATOM_S6_REQ_LCD_EXPANSION_FULL         0x00001000L //Normal expansion Request bit for LCD
-#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO  0x00002000L //Aspect ratio expansion Request bit for LCD
-
-#define ATOM_S6_DISPLAY_STATE_CHANGE    0x00004000L        //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
-#define ATOM_S6_I2C_STATE_CHANGE        0x00008000L        //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
-
-#define ATOM_S6_ACC_REQ_CRT1            0x00010000L
-#define ATOM_S6_ACC_REQ_LCD1            0x00020000L
-#define ATOM_S6_ACC_REQ_TV1             0x00040000L
-#define ATOM_S6_ACC_REQ_DFP1            0x00080000L
-#define ATOM_S6_ACC_REQ_CRT2            0x00100000L
-#define ATOM_S6_ACC_REQ_LCD2            0x00200000L
-#define ATOM_S6_ACC_REQ_DFP6            0x00400000L
-#define ATOM_S6_ACC_REQ_DFP2            0x00800000L
-#define ATOM_S6_ACC_REQ_CV              0x01000000L
-#define ATOM_S6_ACC_REQ_DFP3						0x02000000L
-#define ATOM_S6_ACC_REQ_DFP4						0x04000000L
-#define ATOM_S6_ACC_REQ_DFP5						0x08000000L
-
-#define ATOM_S6_ACC_REQ_MASK                0x0FFF0000L
-#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE    0x10000000L
-#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH    0x20000000L
-#define ATOM_S6_VRI_BRIGHTNESS_CHANGE       0x40000000L
-#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK  0x80000000L
-
-//Byte aligned definition for BIOS usage
-#define ATOM_S6_DEVICE_CHANGEb0         0x01
-#define ATOM_S6_SCALER_CHANGEb0         0x02
-#define ATOM_S6_LID_CHANGEb0            0x04
-#define ATOM_S6_DOCKING_CHANGEb0        0x08
-#define ATOM_S6_ACC_MODEb0              0x10
-#define ATOM_S6_EXT_DESKTOP_MODEb0      0x20
-#define ATOM_S6_LID_STATEb0             0x40
-#define ATOM_S6_DOCK_STATEb0            0x80
-#define ATOM_S6_CRITICAL_STATEb1        0x01
-#define ATOM_S6_HW_I2C_BUSY_STATEb1     0x02  
-#define ATOM_S6_THERMAL_STATE_CHANGEb1  0x04
-#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
-#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1        0x10    
-#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 
-
-#define ATOM_S6_ACC_REQ_CRT1b2          0x01
-#define ATOM_S6_ACC_REQ_LCD1b2          0x02
-#define ATOM_S6_ACC_REQ_TV1b2           0x04
-#define ATOM_S6_ACC_REQ_DFP1b2          0x08
-#define ATOM_S6_ACC_REQ_CRT2b2          0x10
-#define ATOM_S6_ACC_REQ_LCD2b2          0x20
-#define ATOM_S6_ACC_REQ_DFP6b2          0x40
-#define ATOM_S6_ACC_REQ_DFP2b2          0x80
-#define ATOM_S6_ACC_REQ_CVb3            0x01
-#define ATOM_S6_ACC_REQ_DFP3b3          0x02
-#define ATOM_S6_ACC_REQ_DFP4b3          0x04
-#define ATOM_S6_ACC_REQ_DFP5b3          0x08
-
-#define ATOM_S6_ACC_REQ_DEVICEw1        ATOM_S5_DOS_REQ_DEVICEw0
-#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
-#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
-#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3    0x40
-#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3    0x80
-
-#define ATOM_S6_DEVICE_CHANGE_SHIFT             0
-#define ATOM_S6_SCALER_CHANGE_SHIFT             1
-#define ATOM_S6_LID_CHANGE_SHIFT                2
-#define ATOM_S6_DOCKING_CHANGE_SHIFT            3
-#define ATOM_S6_ACC_MODE_SHIFT                  4
-#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT          5
-#define ATOM_S6_LID_STATE_SHIFT                 6
-#define ATOM_S6_DOCK_STATE_SHIFT                7
-#define ATOM_S6_CRITICAL_STATE_SHIFT            8
-#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT         9
-#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT      10
-#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT     11
-#define ATOM_S6_REQ_SCALER_SHIFT                12
-#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT         13
-#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT      14
-#define ATOM_S6_I2C_STATE_CHANGE_SHIFT          15
-#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT  28
-#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT  29
-#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT     30
-#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT     31
-
-// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
-#define ATOM_S7_DOS_MODE_TYPEb0             0x03
-#define ATOM_S7_DOS_MODE_VGAb0              0x00
-#define ATOM_S7_DOS_MODE_VESAb0             0x01
-#define ATOM_S7_DOS_MODE_EXTb0              0x02
-#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0      0x0C
-#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0     0xF0
-#define ATOM_S7_DOS_8BIT_DAC_ENb1           0x01
-#define ATOM_S7_ASIC_INIT_COMPLETEb1        0x02
-#define ATOM_S7_ASIC_INIT_COMPLETE_MASK     0x00000200
-#define ATOM_S7_DOS_MODE_NUMBERw1           0x0FFFF
-
-#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT       8
-
-// BIOS_8_SCRATCH Definition
-#define ATOM_S8_I2C_CHANNEL_BUSY_MASK       0x00000FFFF
-#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK     0x0FFFF0000   
-
-#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT      0
-#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT       16
-
-// BIOS_9_SCRATCH Definition
-#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 
-#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK  0x0000FFFF
-#endif
-#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK  
-#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK    0xFFFF0000
-#endif
-#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 
-#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
-#endif
-#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT   
-#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT   16
-#endif
-
- 
-#define ATOM_FLAG_SET                         0x20
-#define ATOM_FLAG_CLEAR                       0
-#define CLEAR_ATOM_S6_ACC_MODE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
-#define SET_ATOM_S6_DEVICE_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_SCALER_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_LID_CHANGE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
-
-#define SET_ATOM_S6_LID_STATE                 ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
-#define CLEAR_ATOM_S6_LID_STATE               ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
-
-#define SET_ATOM_S6_DOCK_CHANGE			          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_DOCK_STATE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
-#define CLEAR_ATOM_S6_DOCK_STATE              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
-
-#define SET_ATOM_S6_THERMAL_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE  ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
-
-#define SET_ATOM_S6_CRITICAL_STATE            ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
-#define CLEAR_ATOM_S6_CRITICAL_STATE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
-
-#define SET_ATOM_S6_REQ_SCALER                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)  
-#define CLEAR_ATOM_S6_REQ_SCALER              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
-
-#define SET_ATOM_S6_REQ_SCALER_ARATIO         ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
-#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO       ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
-
-#define SET_ATOM_S6_I2C_STATE_CHANGE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
-
-#define SET_ATOM_S6_DISPLAY_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
-
-#define SET_ATOM_S6_DEVICE_RECONFIG           ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define CLEAR_ATOM_S0_LCD1                    ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )|  ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
-#define SET_ATOM_S7_DOS_8BIT_DAC_EN           ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
-#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN         ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
-
-/****************************************************************************/	
-//Portion II: Definitinos only used in Driver
-/****************************************************************************/
-
-// Macros used by driver
-#ifdef __cplusplus
-#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
-
-#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
-#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
-#else // not __cplusplus
-#define	GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
-
-#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
-#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
-#endif // __cplusplus
-
-#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
-#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
-
-/****************************************************************************/	
-//Portion III: Definitinos only used in VBIOS
-/****************************************************************************/
-#define ATOM_DAC_SRC					0x80
-#define ATOM_SRC_DAC1					0
-#define ATOM_SRC_DAC2					0x80
-
-typedef struct _MEMORY_PLLINIT_PARAMETERS
-{
-  ULONG ulTargetMemoryClock; //In 10Khz unit
-  UCHAR   ucAction;					 //not define yet
-  UCHAR   ucFbDiv_Hi;				 //Fbdiv Hi byte
-  UCHAR   ucFbDiv;					 //FB value
-  UCHAR   ucPostDiv;				 //Post div
-}MEMORY_PLLINIT_PARAMETERS;
-
-#define MEMORY_PLLINIT_PS_ALLOCATION  MEMORY_PLLINIT_PARAMETERS
-
-
-#define	GPIO_PIN_WRITE													0x01			
-#define	GPIO_PIN_READ														0x00
-
-typedef struct  _GPIO_PIN_CONTROL_PARAMETERS
-{
-  UCHAR ucGPIO_ID;           //return value, read from GPIO pins
-  UCHAR ucGPIOBitShift;	     //define which bit in uGPIOBitVal need to be update 
-	UCHAR ucGPIOBitVal;		     //Set/Reset corresponding bit defined in ucGPIOBitMask
-  UCHAR ucAction;				     //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
-}GPIO_PIN_CONTROL_PARAMETERS;
-
-typedef struct _ENABLE_SCALER_PARAMETERS
-{
-  UCHAR ucScaler;            // ATOM_SCALER1, ATOM_SCALER2
-  UCHAR ucEnable;            // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
-  UCHAR ucTVStandard;        // 
-  UCHAR ucPadding[1];
-}ENABLE_SCALER_PARAMETERS; 
-#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 
-
-//ucEnable:
-#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION    0
-#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION  1
-#define SCALER_ENABLE_2TAP_ALPHA_MODE               2
-#define SCALER_ENABLE_MULTITAP_MODE                 3
-
-typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
-{
-  ULONG  usHWIconHorzVertPosn;        // Hardware Icon Vertical position
-  UCHAR  ucHWIconVertOffset;          // Hardware Icon Vertical offset
-  UCHAR  ucHWIconHorzOffset;          // Hardware Icon Horizontal offset
-  UCHAR  ucSelection;                 // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
-  UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
-}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
-
-typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
-{
-  ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS  sEnableIcon;
-  ENABLE_CRTC_PARAMETERS                  sReserved;  
-}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
-
-typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
-{
-  USHORT usHight;                     // Image Hight
-  USHORT usWidth;                     // Image Width
-  UCHAR  ucSurface;                   // Surface 1 or 2	
-  UCHAR  ucPadding[3];
-}ENABLE_GRAPH_SURFACE_PARAMETERS;
-
-typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
-{
-  USHORT usHight;                     // Image Hight
-  USHORT usWidth;                     // Image Width
-  UCHAR  ucSurface;                   // Surface 1 or 2
-  UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
-  UCHAR  ucPadding[2];
-}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
-
-typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
-{
-  USHORT usHight;                     // Image Hight
-  USHORT usWidth;                     // Image Width
-  UCHAR  ucSurface;                   // Surface 1 or 2
-  UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
-  USHORT usDeviceId;                  // Active Device Id for this surface. If no device, set to 0. 
-}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
-
-typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4
-{
-  USHORT usHight;                     // Image Hight
-  USHORT usWidth;                     // Image Width
-  USHORT usGraphPitch;
-  UCHAR  ucColorDepth;
-  UCHAR  ucPixelFormat;
-  UCHAR  ucSurface;                   // Surface 1 or 2
-  UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
-  UCHAR  ucModeType;
-  UCHAR  ucReserved;
-}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4;
-
-// ucEnable
-#define ATOM_GRAPH_CONTROL_SET_PITCH             0x0f
-#define ATOM_GRAPH_CONTROL_SET_DISP_START        0x10
-
-typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
-{
-  ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;          
-  ENABLE_YUV_PS_ALLOCATION        sReserved; // Don't set this one
-}ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
-
-typedef struct _MEMORY_CLEAN_UP_PARAMETERS
-{
-  USHORT  usMemoryStart;                //in 8Kb boundary, offset from memory base address
-  USHORT  usMemorySize;                 //8Kb blocks aligned
-}MEMORY_CLEAN_UP_PARAMETERS;
-#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
-
-typedef struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
-{
-  USHORT  usX_Size;                     //When use as input parameter, usX_Size indicates which CRTC                 
-  USHORT  usY_Size;
-}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 
-
-typedef struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2
-{
-  union{
-    USHORT  usX_Size;                     //When use as input parameter, usX_Size indicates which CRTC                 
-    USHORT  usSurface; 
-  };
-  USHORT usY_Size;
-  USHORT usDispXStart;               
-  USHORT usDispYStart;
-}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 
-
-
-typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 
-{
-  UCHAR  ucLutId;
-  UCHAR  ucAction;
-  USHORT usLutStartIndex;
-  USHORT usLutLength;
-  USHORT usLutOffsetInVram;
-}PALETTE_DATA_CONTROL_PARAMETERS_V3;
-
-// ucAction:
-#define PALETTE_DATA_AUTO_FILL            1
-#define PALETTE_DATA_READ                 2
-#define PALETTE_DATA_WRITE                3
-
-
-typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2
-{
-  UCHAR  ucInterruptId;
-  UCHAR  ucServiceId;
-  UCHAR  ucStatus;
-  UCHAR  ucReserved;
-}INTERRUPT_SERVICE_PARAMETER_V2;
-
-// ucInterruptId
-#define HDP1_INTERRUPT_ID                 1
-#define HDP2_INTERRUPT_ID                 2
-#define HDP3_INTERRUPT_ID                 3
-#define HDP4_INTERRUPT_ID                 4
-#define HDP5_INTERRUPT_ID                 5
-#define HDP6_INTERRUPT_ID                 6
-#define SW_INTERRUPT_ID                   11   
-
-// ucAction
-#define INTERRUPT_SERVICE_GEN_SW_INT      1
-#define INTERRUPT_SERVICE_GET_STATUS      2
-
- // ucStatus
-#define INTERRUPT_STATUS__INT_TRIGGER     1
-#define INTERRUPT_STATUS__HPD_HIGH        2
-
-typedef struct _INDIRECT_IO_ACCESS
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  UCHAR                    IOAccessSequence[256];
-} INDIRECT_IO_ACCESS;
-
-#define INDIRECT_READ              0x00
-#define INDIRECT_WRITE             0x80
-
-#define INDIRECT_IO_MM             0
-#define INDIRECT_IO_PLL            1
-#define INDIRECT_IO_MC             2
-#define INDIRECT_IO_PCIE           3
-#define INDIRECT_IO_PCIEP          4
-#define INDIRECT_IO_NBMISC         5
-#define INDIRECT_IO_SMU            5
-
-#define INDIRECT_IO_PLL_READ       INDIRECT_IO_PLL   | INDIRECT_READ
-#define INDIRECT_IO_PLL_WRITE      INDIRECT_IO_PLL   | INDIRECT_WRITE
-#define INDIRECT_IO_MC_READ        INDIRECT_IO_MC    | INDIRECT_READ
-#define INDIRECT_IO_MC_WRITE       INDIRECT_IO_MC    | INDIRECT_WRITE
-#define INDIRECT_IO_PCIE_READ      INDIRECT_IO_PCIE  | INDIRECT_READ
-#define INDIRECT_IO_PCIE_WRITE     INDIRECT_IO_PCIE  | INDIRECT_WRITE
-#define INDIRECT_IO_PCIEP_READ     INDIRECT_IO_PCIEP | INDIRECT_READ
-#define INDIRECT_IO_PCIEP_WRITE    INDIRECT_IO_PCIEP | INDIRECT_WRITE
-#define INDIRECT_IO_NBMISC_READ    INDIRECT_IO_NBMISC | INDIRECT_READ
-#define INDIRECT_IO_NBMISC_WRITE   INDIRECT_IO_NBMISC | INDIRECT_WRITE
-#define INDIRECT_IO_SMU_READ       INDIRECT_IO_SMU | INDIRECT_READ
-#define INDIRECT_IO_SMU_WRITE      INDIRECT_IO_SMU | INDIRECT_WRITE
-
-typedef struct _ATOM_OEM_INFO
-{ 
-  ATOM_COMMON_TABLE_HEADER	sHeader;
-  ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
-}ATOM_OEM_INFO;
-
-typedef struct _ATOM_TV_MODE
-{
-   UCHAR	ucVMode_Num;			  //Video mode number
-   UCHAR	ucTV_Mode_Num;			//Internal TV mode number
-}ATOM_TV_MODE;
-
-typedef struct _ATOM_BIOS_INT_TVSTD_MODE
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-   USHORT	usTV_Mode_LUT_Offset;	// Pointer to standard to internal number conversion table
-   USHORT	usTV_FIFO_Offset;		  // Pointer to FIFO entry table
-   USHORT	usNTSC_Tbl_Offset;		// Pointer to SDTV_Mode_NTSC table
-   USHORT	usPAL_Tbl_Offset;		  // Pointer to SDTV_Mode_PAL table 
-   USHORT	usCV_Tbl_Offset;		  // Pointer to SDTV_Mode_PAL table 
-}ATOM_BIOS_INT_TVSTD_MODE;
-
-
-typedef struct _ATOM_TV_MODE_SCALER_PTR
-{
-   USHORT	ucFilter0_Offset;		//Pointer to filter format 0 coefficients
-   USHORT	usFilter1_Offset;		//Pointer to filter format 0 coefficients
-   UCHAR	ucTV_Mode_Num;
-}ATOM_TV_MODE_SCALER_PTR;
-
-typedef struct _ATOM_STANDARD_VESA_TIMING
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  ATOM_DTD_FORMAT 				 aModeTimings[16];      // 16 is not the real array number, just for initial allocation
-}ATOM_STANDARD_VESA_TIMING;
-
-
-typedef struct _ATOM_STD_FORMAT
-{ 
-  USHORT    usSTD_HDisp;
-  USHORT    usSTD_VDisp;
-  USHORT    usSTD_RefreshRate;
-  USHORT    usReserved;
-}ATOM_STD_FORMAT;
-
-typedef struct _ATOM_VESA_TO_EXTENDED_MODE
-{
-  USHORT  usVESA_ModeNumber;
-  USHORT  usExtendedModeNumber;
-}ATOM_VESA_TO_EXTENDED_MODE;
-
-typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
-{ 
-  ATOM_COMMON_TABLE_HEADER   sHeader;  
-  ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
-}ATOM_VESA_TO_INTENAL_MODE_LUT;
-
-/*************** ATOM Memory Related Data Structure ***********************/
-typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
-	UCHAR												ucMemoryType;
-	UCHAR												ucMemoryVendor;
-	UCHAR												ucAdjMCId;
-	UCHAR												ucDynClkId;
-	ULONG												ulDllResetClkRange;
-}ATOM_MEMORY_VENDOR_BLOCK;
-
-
-typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
-#if ATOM_BIG_ENDIAN
-	ULONG												ucMemBlkId:8;
-	ULONG												ulMemClockRange:24;
-#else
-	ULONG												ulMemClockRange:24;
-	ULONG												ucMemBlkId:8;
-#endif
-}ATOM_MEMORY_SETTING_ID_CONFIG;
-
-typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
-{
-  ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
-  ULONG                         ulAccess;
-}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
-
-
-typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
-	ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS			ulMemoryID;
-	ULONG															        aulMemData[1];
-}ATOM_MEMORY_SETTING_DATA_BLOCK;
-
-
-typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
-	 USHORT											usRegIndex;                                     // MC register index
-	 UCHAR											ucPreRegDataLength;                             // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
-}ATOM_INIT_REG_INDEX_FORMAT;
-
-
-typedef struct _ATOM_INIT_REG_BLOCK{
-	USHORT													usRegIndexTblSize;													//size of asRegIndexBuf
-	USHORT													usRegDataBlkSize;														//size of ATOM_MEMORY_SETTING_DATA_BLOCK
-	ATOM_INIT_REG_INDEX_FORMAT			asRegIndexBuf[1];
-	ATOM_MEMORY_SETTING_DATA_BLOCK	asRegDataBuf[1];
-}ATOM_INIT_REG_BLOCK;
-
-#define END_OF_REG_INDEX_BLOCK  0x0ffff
-#define END_OF_REG_DATA_BLOCK   0x00000000
-#define ATOM_INIT_REG_MASK_FLAG 0x80               //Not used in BIOS
-#define	CLOCK_RANGE_HIGHEST			0x00ffffff
-
-#define VALUE_DWORD             SIZEOF ULONG
-#define VALUE_SAME_AS_ABOVE     0
-#define VALUE_MASK_DWORD        0x84
-
-#define INDEX_ACCESS_RANGE_BEGIN	    (VALUE_DWORD + 1)
-#define INDEX_ACCESS_RANGE_END		    (INDEX_ACCESS_RANGE_BEGIN + 1)
-#define VALUE_INDEX_ACCESS_SINGLE	    (INDEX_ACCESS_RANGE_END + 1)
-//#define ACCESS_MCIODEBUGIND            0x40       //defined in BIOS code
-#define ACCESS_PLACEHOLDER             0x80
-
-typedef struct _ATOM_MC_INIT_PARAM_TABLE
-{ 
-  ATOM_COMMON_TABLE_HEADER		sHeader;
-  USHORT											usAdjustARB_SEQDataOffset;
-  USHORT											usMCInitMemTypeTblOffset;
-  USHORT											usMCInitCommonTblOffset;
-  USHORT											usMCInitPowerDownTblOffset;
-	ULONG												ulARB_SEQDataBuf[32];
-	ATOM_INIT_REG_BLOCK					asMCInitMemType;
-	ATOM_INIT_REG_BLOCK					asMCInitCommon;
-}ATOM_MC_INIT_PARAM_TABLE;
-
-
-#define _4Mx16              0x2
-#define _4Mx32              0x3
-#define _8Mx16              0x12
-#define _8Mx32              0x13
-#define _16Mx16             0x22
-#define _16Mx32             0x23
-#define _32Mx16             0x32
-#define _32Mx32             0x33
-#define _64Mx8              0x41
-#define _64Mx16             0x42
-#define _64Mx32             0x43
-#define _128Mx8             0x51
-#define _128Mx16            0x52
-#define _128Mx32            0x53
-#define _256Mx8             0x61
-#define _256Mx16            0x62
-#define _512Mx8             0x71
-
-#define SAMSUNG             0x1
-#define INFINEON            0x2
-#define ELPIDA              0x3
-#define ETRON               0x4
-#define NANYA               0x5
-#define HYNIX               0x6
-#define MOSEL               0x7
-#define WINBOND             0x8
-#define ESMT                0x9
-#define MICRON              0xF
-
-#define QIMONDA             INFINEON
-#define PROMOS              MOSEL
-#define KRETON              INFINEON
-#define ELIXIR              NANYA
-#define MEZZA               ELPIDA
-
-
-/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
-
-#define UCODE_ROM_START_ADDRESS		0x1b800
-#define	UCODE_SIGNATURE			0x4375434d // 'MCuC' - MC uCode
-
-//uCode block header for reference
-
-typedef struct _MCuCodeHeader
-{
-  ULONG  ulSignature;
-  UCHAR  ucRevision;
-  UCHAR  ucChecksum;
-  UCHAR  ucReserved1;
-  UCHAR  ucReserved2;
-  USHORT usParametersLength;
-  USHORT usUCodeLength;
-  USHORT usReserved1;
-  USHORT usReserved2;
-} MCuCodeHeader;
-
-//////////////////////////////////////////////////////////////////////////////////
-
-#define ATOM_MAX_NUMBER_OF_VRAM_MODULE	16
-
-#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK	0xF
-typedef struct _ATOM_VRAM_MODULE_V1
-{
-  ULONG                      ulReserved;
-  USHORT                     usEMRSValue;  
-  USHORT                     usMRSValue;
-  USHORT                     usReserved;
-  UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
-  UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
-  UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender 
-  UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
-  UCHAR                      ucRow;             // Number of Row,in power of 2;
-  UCHAR                      ucColumn;          // Number of Column,in power of 2;
-  UCHAR                      ucBank;            // Nunber of Bank;
-  UCHAR                      ucRank;            // Number of Rank, in power of 2
-  UCHAR                      ucChannelNum;      // Number of channel;
-  UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
-  UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
-  UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
-  UCHAR                      ucReserved[2];
-}ATOM_VRAM_MODULE_V1;
-
-
-typedef struct _ATOM_VRAM_MODULE_V2
-{
-  ULONG                      ulReserved;
-  ULONG                      ulFlags;     			// To enable/disable functionalities based on memory type
-  ULONG                      ulEngineClock;     // Override of default engine clock for particular memory type
-  ULONG                      ulMemoryClock;     // Override of default memory clock for particular memory type
-  USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
-  USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
-  USHORT                     usEMRSValue;  
-  USHORT                     usMRSValue;
-  USHORT                     usReserved;
-  UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
-  UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
-  UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
-  UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
-  UCHAR                      ucRow;             // Number of Row,in power of 2;
-  UCHAR                      ucColumn;          // Number of Column,in power of 2;
-  UCHAR                      ucBank;            // Nunber of Bank;
-  UCHAR                      ucRank;            // Number of Rank, in power of 2
-  UCHAR                      ucChannelNum;      // Number of channel;
-  UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
-  UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
-  UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
-  UCHAR                      ucRefreshRateFactor;
-  UCHAR                      ucReserved[3];
-}ATOM_VRAM_MODULE_V2;
-
-
-typedef	struct _ATOM_MEMORY_TIMING_FORMAT
-{
-	ULONG											 ulClkRange;				// memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 	
-  union{
-	  USHORT										 usMRS;							// mode register						
-    USHORT                     usDDR3_MR0;
-  };
-  union{
-	  USHORT										 usEMRS;						// extended mode register
-    USHORT                     usDDR3_MR1;
-  };
-	UCHAR											 ucCL;							// CAS latency
-	UCHAR											 ucWL;							// WRITE Latency				
-	UCHAR											 uctRAS;						// tRAS
-	UCHAR											 uctRC;							// tRC	
-	UCHAR											 uctRFC;						// tRFC
-	UCHAR											 uctRCDR;						// tRCDR	
-	UCHAR											 uctRCDW;						// tRCDW
-	UCHAR											 uctRP;							// tRP
-	UCHAR											 uctRRD;						// tRRD	
-	UCHAR											 uctWR;							// tWR
-	UCHAR											 uctWTR;						// tWTR
-	UCHAR											 uctPDIX;						// tPDIX
-	UCHAR											 uctFAW;						// tFAW
-	UCHAR											 uctAOND;						// tAOND
-  union 
-  {
-    struct {
-	    UCHAR											 ucflag;						// flag to control memory timing calculation. bit0= control EMRS2 Infineon 
-	    UCHAR											 ucReserved;						
-    };
-    USHORT                   usDDR3_MR2;
-  };
-}ATOM_MEMORY_TIMING_FORMAT;
-
-
-typedef	struct _ATOM_MEMORY_TIMING_FORMAT_V1
-{
-	ULONG											 ulClkRange;				// memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 	
-	USHORT										 usMRS;							// mode register						
-	USHORT										 usEMRS;						// extended mode register
-	UCHAR											 ucCL;							// CAS latency
-	UCHAR											 ucWL;							// WRITE Latency				
-	UCHAR											 uctRAS;						// tRAS
-	UCHAR											 uctRC;							// tRC	
-	UCHAR											 uctRFC;						// tRFC
-	UCHAR											 uctRCDR;						// tRCDR	
-	UCHAR											 uctRCDW;						// tRCDW
-	UCHAR											 uctRP;							// tRP
-	UCHAR											 uctRRD;						// tRRD	
-	UCHAR											 uctWR;							// tWR
-	UCHAR											 uctWTR;						// tWTR
-	UCHAR											 uctPDIX;						// tPDIX
-	UCHAR											 uctFAW;						// tFAW
-	UCHAR											 uctAOND;						// tAOND
-	UCHAR											 ucflag;						// flag to control memory timing calculation. bit0= control EMRS2 Infineon 
-////////////////////////////////////GDDR parameters///////////////////////////////////
-	UCHAR											 uctCCDL;						// 
-	UCHAR											 uctCRCRL;						// 
-	UCHAR											 uctCRCWL;						// 
-	UCHAR											 uctCKE;						// 
-	UCHAR											 uctCKRSE;						// 
-	UCHAR											 uctCKRSX;						// 
-	UCHAR											 uctFAW32;						// 
-	UCHAR											 ucMR5lo;					// 
-	UCHAR											 ucMR5hi;					// 
-	UCHAR											 ucTerminator;
-}ATOM_MEMORY_TIMING_FORMAT_V1;
-
-typedef	struct _ATOM_MEMORY_TIMING_FORMAT_V2
-{
-	ULONG											 ulClkRange;				// memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 	
-	USHORT										 usMRS;							// mode register						
-	USHORT										 usEMRS;						// extended mode register
-	UCHAR											 ucCL;							// CAS latency
-	UCHAR											 ucWL;							// WRITE Latency				
-	UCHAR											 uctRAS;						// tRAS
-	UCHAR											 uctRC;							// tRC	
-	UCHAR											 uctRFC;						// tRFC
-	UCHAR											 uctRCDR;						// tRCDR	
-	UCHAR											 uctRCDW;						// tRCDW
-	UCHAR											 uctRP;							// tRP
-	UCHAR											 uctRRD;						// tRRD	
-	UCHAR											 uctWR;							// tWR
-	UCHAR											 uctWTR;						// tWTR
-	UCHAR											 uctPDIX;						// tPDIX
-	UCHAR											 uctFAW;						// tFAW
-	UCHAR											 uctAOND;						// tAOND
-	UCHAR											 ucflag;						// flag to control memory timing calculation. bit0= control EMRS2 Infineon 
-////////////////////////////////////GDDR parameters///////////////////////////////////
-	UCHAR											 uctCCDL;						// 
-	UCHAR											 uctCRCRL;						// 
-	UCHAR											 uctCRCWL;						// 
-	UCHAR											 uctCKE;						// 
-	UCHAR											 uctCKRSE;						// 
-	UCHAR											 uctCKRSX;						// 
-	UCHAR											 uctFAW32;						// 
-	UCHAR											 ucMR4lo;					// 
-	UCHAR											 ucMR4hi;					// 
-	UCHAR											 ucMR5lo;					// 
-	UCHAR											 ucMR5hi;					// 
-	UCHAR											 ucTerminator;
-	UCHAR											 ucReserved;	
-}ATOM_MEMORY_TIMING_FORMAT_V2;
-
-typedef	struct _ATOM_MEMORY_FORMAT
-{
-	ULONG											 ulDllDisClock;			// memory DLL will be disable when target memory clock is below this clock
-  union{
-    USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
-    USHORT                     usDDR3_Reserved;   // Not used for DDR3 memory
-  };
-  union{
-    USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
-    USHORT                     usDDR3_MR3;        // Used for DDR3 memory
-  };
-  UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
-  UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
-  UCHAR                      ucRow;             // Number of Row,in power of 2;
-  UCHAR                      ucColumn;          // Number of Column,in power of 2;
-  UCHAR                      ucBank;            // Nunber of Bank;
-  UCHAR                      ucRank;            // Number of Rank, in power of 2
-	UCHAR											 ucBurstSize;				// burst size, 0= burst size=4  1= burst size=8
-  UCHAR                      ucDllDisBit;				// position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
-  UCHAR                      ucRefreshRateFactor;	// memory refresh rate in unit of ms	
-	UCHAR											 ucDensity;					// _8Mx32, _16Mx32, _16Mx16, _32Mx16
-	UCHAR											 ucPreamble;				//[7:4] Write Preamble, [3:0] Read Preamble
-  UCHAR											 ucMemAttrib;				// Memory Device Addribute, like RDBI/WDBI etc
-	ATOM_MEMORY_TIMING_FORMAT	 asMemTiming[5];		//Memory Timing block sort from lower clock to higher clock
-}ATOM_MEMORY_FORMAT;
-
-
-typedef struct _ATOM_VRAM_MODULE_V3
-{
-	ULONG											 ulChannelMapCfg;		// board dependent paramenter:Channel combination
-	USHORT										 usSize;						// size of ATOM_VRAM_MODULE_V3
-  USHORT                     usDefaultMVDDQ;		// board dependent parameter:Default Memory Core Voltage
-  USHORT                     usDefaultMVDDC;		// board dependent parameter:Default Memory IO Voltage
-	UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
-  UCHAR                      ucChannelNum;      // board dependent parameter:Number of channel;
-	UCHAR											 ucChannelSize;			// board dependent parameter:32bit or 64bit	
-	UCHAR											 ucVREFI;						// board dependnt parameter: EXT or INT +160mv to -140mv
-	UCHAR											 ucNPL_RT;					// board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
-	UCHAR											 ucFlag;						// To enable/disable functionalities based on memory type
-	ATOM_MEMORY_FORMAT				 asMemory;					// describ all of video memory parameters from memory spec
-}ATOM_VRAM_MODULE_V3;
-
-
-//ATOM_VRAM_MODULE_V3.ucNPL_RT
-#define NPL_RT_MASK															0x0f
-#define BATTERY_ODT_MASK												0xc0
-
-#define ATOM_VRAM_MODULE		 ATOM_VRAM_MODULE_V3
-
-typedef struct _ATOM_VRAM_MODULE_V4
-{
-  ULONG	  ulChannelMapCfg;	                // board dependent parameter: Channel combination
-  USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
-  USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
-                                            // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
-  USHORT  usReserved;
-  UCHAR   ucExtMemoryID;    		            // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
-  UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
-  UCHAR   ucChannelNum;                     // Number of channels present in this module config
-  UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
-	UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
-	UCHAR	  ucFlag;						                // To enable/disable functionalities based on memory type
-	UCHAR	  ucMisc;						                // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
-  UCHAR		ucVREFI;                          // board dependent parameter
-  UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
-  UCHAR		ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
-  UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
-                                            // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
-  UCHAR   ucReserved[3];
-
-//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
-  union{
-    USHORT	usEMRS2Value;                   // EMRS2 Value is used for GDDR2 and GDDR4 memory type
-    USHORT  usDDR3_Reserved;
-  };
-  union{
-    USHORT	usEMRS3Value;                   // EMRS3 Value is used for GDDR2 and GDDR4 memory type
-    USHORT  usDDR3_MR3;                     // Used for DDR3 memory
-  };  
-  UCHAR   ucMemoryVenderID;  		            // Predefined, If not predefined, vendor detection table gets executed
-  UCHAR	  ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
-  UCHAR   ucReserved2[2];
-  ATOM_MEMORY_TIMING_FORMAT  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
-}ATOM_VRAM_MODULE_V4;
-
-#define VRAM_MODULE_V4_MISC_RANK_MASK       0x3
-#define VRAM_MODULE_V4_MISC_DUAL_RANK       0x1
-#define VRAM_MODULE_V4_MISC_BL_MASK         0x4
-#define VRAM_MODULE_V4_MISC_BL8             0x4
-#define VRAM_MODULE_V4_MISC_DUAL_CS         0x10
-
-typedef struct _ATOM_VRAM_MODULE_V5
-{
-  ULONG	  ulChannelMapCfg;	                // board dependent parameter: Channel combination
-  USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
-  USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
-                                            // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
-  USHORT  usReserved;
-  UCHAR   ucExtMemoryID;    		            // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
-  UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
-  UCHAR   ucChannelNum;                     // Number of channels present in this module config
-  UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
-	UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
-	UCHAR	  ucFlag;						                // To enable/disable functionalities based on memory type
-	UCHAR	  ucMisc;						                // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
-  UCHAR		ucVREFI;                          // board dependent parameter
-  UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
-  UCHAR		ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
-  UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
-                                            // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
-  UCHAR   ucReserved[3];
-
-//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
-  USHORT	usEMRS2Value;      		            // EMRS2 Value is used for GDDR2 and GDDR4 memory type
-  USHORT	usEMRS3Value;      		            // EMRS3 Value is used for GDDR2 and GDDR4 memory type
-  UCHAR   ucMemoryVenderID;  		            // Predefined, If not predefined, vendor detection table gets executed
-  UCHAR	  ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
-  UCHAR	  ucFIFODepth;			                // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
-  UCHAR   ucCDR_Bandwidth;		   // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
-  ATOM_MEMORY_TIMING_FORMAT_V1  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
-}ATOM_VRAM_MODULE_V5;
-
-typedef struct _ATOM_VRAM_MODULE_V6
-{
-  ULONG	  ulChannelMapCfg;	                // board dependent parameter: Channel combination
-  USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
-  USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
-                                            // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
-  USHORT  usReserved;
-  UCHAR   ucExtMemoryID;    		            // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
-  UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
-  UCHAR   ucChannelNum;                     // Number of channels present in this module config
-  UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
-	UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
-	UCHAR	  ucFlag;						                // To enable/disable functionalities based on memory type
-	UCHAR	  ucMisc;						                // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
-  UCHAR		ucVREFI;                          // board dependent parameter
-  UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
-  UCHAR		ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
-  UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
-                                            // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
-  UCHAR   ucReserved[3];
-
-//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
-  USHORT	usEMRS2Value;      		            // EMRS2 Value is used for GDDR2 and GDDR4 memory type
-  USHORT	usEMRS3Value;      		            // EMRS3 Value is used for GDDR2 and GDDR4 memory type
-  UCHAR   ucMemoryVenderID;  		            // Predefined, If not predefined, vendor detection table gets executed
-  UCHAR	  ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
-  UCHAR	  ucFIFODepth;			                // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
-  UCHAR   ucCDR_Bandwidth;		   // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
-  ATOM_MEMORY_TIMING_FORMAT_V2  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
-}ATOM_VRAM_MODULE_V6;
-
-typedef struct _ATOM_VRAM_MODULE_V7
-{
-// Design Specific Values
-  ULONG	  ulChannelMapCfg;	                // mmMC_SHARED_CHREMAP
-  USHORT  usModuleSize;                     // Size of ATOM_VRAM_MODULE_V7
-  USHORT  usPrivateReserved;                // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
-  USHORT  usEnableChannels;                 // bit vector which indicate which channels are enabled
-  UCHAR   ucExtMemoryID;                    // Current memory module ID
-  UCHAR   ucMemoryType;                     // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
-  UCHAR   ucChannelNum;                     // Number of mem. channels supported in this module
-  UCHAR   ucChannelWidth;                   // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
-  UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
-  UCHAR	  ucReserve;                        // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now.
-  UCHAR	  ucMisc;                           // RANK_OF_THISMEMORY etc.
-  UCHAR	  ucVREFI;                          // Not used.
-  UCHAR   ucNPL_RT;                         // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
-  UCHAR	  ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
-  UCHAR   ucMemorySize;                     // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
-  USHORT  usSEQSettingOffset;
-  UCHAR   ucReserved;
-// Memory Module specific values
-  USHORT  usEMRS2Value;                     // EMRS2/MR2 Value. 
-  USHORT  usEMRS3Value;                     // EMRS3/MR3 Value.
-  UCHAR   ucMemoryVenderID;                 // [7:4] Revision, [3:0] Vendor code
-  UCHAR	  ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
-  UCHAR	  ucFIFODepth;                      // FIFO depth can be detected during vendor detection, here is hardcoded per memory
-  UCHAR   ucCDR_Bandwidth;                  // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
-  char    strMemPNString[20];               // part number end with '0'. 
-}ATOM_VRAM_MODULE_V7;
-
-typedef struct _ATOM_VRAM_INFO_V2
-{
-  ATOM_COMMON_TABLE_HEADER   sHeader;
-  UCHAR                      ucNumOfVRAMModule;
-  ATOM_VRAM_MODULE           aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
-}ATOM_VRAM_INFO_V2;
-
-typedef struct _ATOM_VRAM_INFO_V3
-{
-  ATOM_COMMON_TABLE_HEADER   sHeader;
-	USHORT										 usMemAdjustTblOffset;													 // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
-	USHORT										 usMemClkPatchTblOffset;												 //	offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
-	USHORT										 usRerseved;
-	UCHAR           	         aVID_PinsShift[9];															 // 8 bit strap maximum+terminator
-  UCHAR                      ucNumOfVRAMModule;
-  ATOM_VRAM_MODULE		       aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
-	ATOM_INIT_REG_BLOCK				 asMemPatch;																		 // for allocation
-																																						 //	ATOM_INIT_REG_BLOCK				 aMemAdjust;
-}ATOM_VRAM_INFO_V3;
-
-#define	ATOM_VRAM_INFO_LAST	     ATOM_VRAM_INFO_V3
-
-typedef struct _ATOM_VRAM_INFO_V4
-{
-  ATOM_COMMON_TABLE_HEADER   sHeader;
-  USHORT                     usMemAdjustTblOffset;													 // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
-  USHORT                     usMemClkPatchTblOffset;												 //	offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
-  USHORT										 usRerseved;
-  UCHAR           	         ucMemDQ7_0ByteRemap;													   // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
-  ULONG                      ulMemDQ7_0BitRemap;                             // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
-  UCHAR                      ucReservde[4]; 
-  UCHAR                      ucNumOfVRAMModule;
-  ATOM_VRAM_MODULE_V4		     aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
-	ATOM_INIT_REG_BLOCK				 asMemPatch;																		 // for allocation
-																																						 //	ATOM_INIT_REG_BLOCK				 aMemAdjust;
-}ATOM_VRAM_INFO_V4;
-
-typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
-{
-  ATOM_COMMON_TABLE_HEADER   sHeader;
-  USHORT                     usMemAdjustTblOffset;													 // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
-  USHORT                     usMemClkPatchTblOffset;												 //	offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
-  USHORT                     usPerBytePresetOffset;                          // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
-  USHORT                     usReserved[3];
-  UCHAR                      ucNumOfVRAMModule;                              // indicate number of VRAM module
-  UCHAR                      ucMemoryClkPatchTblVer;                         // version of memory AC timing register list
-  UCHAR                      ucVramModuleVer;                                // indicate ATOM_VRAM_MODUE version
-  UCHAR                      ucReserved; 
-  ATOM_VRAM_MODULE_V7		     aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
-}ATOM_VRAM_INFO_HEADER_V2_1;
-
-
-typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
-{
-  ATOM_COMMON_TABLE_HEADER   sHeader;
-  UCHAR           	         aVID_PinsShift[9];   //8 bit strap maximum+terminator
-}ATOM_VRAM_GPIO_DETECTION_INFO;
-
-
-typedef struct _ATOM_MEMORY_TRAINING_INFO
-{
-	ATOM_COMMON_TABLE_HEADER   sHeader;
-	UCHAR											 ucTrainingLoop;
-	UCHAR											 ucReserved[3];
-	ATOM_INIT_REG_BLOCK				 asMemTrainingSetting;
-}ATOM_MEMORY_TRAINING_INFO;
-
-
-typedef struct SW_I2C_CNTL_DATA_PARAMETERS
-{
-  UCHAR    ucControl;
-  UCHAR    ucData; 
-  UCHAR    ucSatus; 
-  UCHAR    ucTemp; 
-} SW_I2C_CNTL_DATA_PARAMETERS;
-
-#define SW_I2C_CNTL_DATA_PS_ALLOCATION  SW_I2C_CNTL_DATA_PARAMETERS
-
-typedef struct _SW_I2C_IO_DATA_PARAMETERS
-{                               
-  USHORT   GPIO_Info;
-  UCHAR    ucAct; 
-  UCHAR    ucData; 
- } SW_I2C_IO_DATA_PARAMETERS;
-
-#define SW_I2C_IO_DATA_PS_ALLOCATION  SW_I2C_IO_DATA_PARAMETERS
-
-/****************************SW I2C CNTL DEFINITIONS**********************/
-#define SW_I2C_IO_RESET       0
-#define SW_I2C_IO_GET         1
-#define SW_I2C_IO_DRIVE       2
-#define SW_I2C_IO_SET         3
-#define SW_I2C_IO_START       4
-
-#define SW_I2C_IO_CLOCK       0
-#define SW_I2C_IO_DATA        0x80
-
-#define SW_I2C_IO_ZERO        0
-#define SW_I2C_IO_ONE         0x100
-
-#define SW_I2C_CNTL_READ      0
-#define SW_I2C_CNTL_WRITE     1
-#define SW_I2C_CNTL_START     2
-#define SW_I2C_CNTL_STOP      3
-#define SW_I2C_CNTL_OPEN      4
-#define SW_I2C_CNTL_CLOSE     5
-#define SW_I2C_CNTL_WRITE1BIT 6
-
-//==============================VESA definition Portion===============================
-#define VESA_OEM_PRODUCT_REV			            "01.00"
-#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT	     0xBB	//refer to VBE spec p.32, no TTY support
-#define VESA_MODE_WIN_ATTRIBUTE						     7
-#define VESA_WIN_SIZE											     64
-
-typedef struct _PTR_32_BIT_STRUCTURE
-{
-	USHORT	Offset16;			
-	USHORT	Segment16;				
-} PTR_32_BIT_STRUCTURE;
-
-typedef union _PTR_32_BIT_UNION
-{
-	PTR_32_BIT_STRUCTURE	SegmentOffset;
-	ULONG					        Ptr32_Bit;
-} PTR_32_BIT_UNION;
-
-typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
-{
-	UCHAR				      VbeSignature[4];
-	USHORT				    VbeVersion;
-	PTR_32_BIT_UNION	OemStringPtr;
-	UCHAR				      Capabilities[4];
-	PTR_32_BIT_UNION	VideoModePtr;
-	USHORT				    TotalMemory;
-} VBE_1_2_INFO_BLOCK_UPDATABLE;
-
-
-typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
-{
-	VBE_1_2_INFO_BLOCK_UPDATABLE	CommonBlock;
-	USHORT							    OemSoftRev;
-	PTR_32_BIT_UNION				OemVendorNamePtr;
-	PTR_32_BIT_UNION				OemProductNamePtr;
-	PTR_32_BIT_UNION				OemProductRevPtr;
-} VBE_2_0_INFO_BLOCK_UPDATABLE;
-
-typedef union _VBE_VERSION_UNION
-{
-	VBE_2_0_INFO_BLOCK_UPDATABLE	VBE_2_0_InfoBlock;
-	VBE_1_2_INFO_BLOCK_UPDATABLE	VBE_1_2_InfoBlock;
-} VBE_VERSION_UNION;
-
-typedef struct _VBE_INFO_BLOCK
-{
-	VBE_VERSION_UNION			UpdatableVBE_Info;
-	UCHAR						      Reserved[222];
-	UCHAR						      OemData[256];
-} VBE_INFO_BLOCK;
-
-typedef struct _VBE_FP_INFO
-{
-  USHORT	HSize;
-	USHORT	VSize;
-	USHORT	FPType;
-	UCHAR		RedBPP;
-	UCHAR		GreenBPP;
-	UCHAR		BlueBPP;
-	UCHAR		ReservedBPP;
-	ULONG		RsvdOffScrnMemSize;
-	ULONG		RsvdOffScrnMEmPtr;
-	UCHAR		Reserved[14];
-} VBE_FP_INFO;
-
-typedef struct _VESA_MODE_INFO_BLOCK
-{
-// Mandatory information for all VBE revisions
-  USHORT    ModeAttributes;  //			dw	?	; mode attributes
-	UCHAR     WinAAttributes;  //			db	?	; window A attributes
-	UCHAR     WinBAttributes;  //			db	?	; window B attributes
-	USHORT    WinGranularity;  //			dw	?	; window granularity
-	USHORT    WinSize;         //			dw	?	; window size
-	USHORT    WinASegment;     //			dw	?	; window A start segment
-	USHORT    WinBSegment;     //			dw	?	; window B start segment
-	ULONG     WinFuncPtr;      //			dd	?	; real mode pointer to window function
-	USHORT    BytesPerScanLine;//			dw	?	; bytes per scan line
-
-//; Mandatory information for VBE 1.2 and above
-  USHORT    XResolution;      //			dw	?	; horizontal resolution in pixels or characters
-	USHORT    YResolution;      //			dw	?	; vertical resolution in pixels or characters
-	UCHAR     XCharSize;        //			db	?	; character cell width in pixels
-	UCHAR     YCharSize;        //			db	?	; character cell height in pixels
-	UCHAR     NumberOfPlanes;   //			db	?	; number of memory planes
-	UCHAR     BitsPerPixel;     //			db	?	; bits per pixel
-	UCHAR     NumberOfBanks;    //			db	?	; number of banks
-	UCHAR     MemoryModel;      //			db	?	; memory model type
-	UCHAR     BankSize;         //			db	?	; bank size in KB
-	UCHAR     NumberOfImagePages;//		  db	?	; number of images
-	UCHAR     ReservedForPageFunction;//db	1	; reserved for page function
-
-//; Direct Color fields(required for direct/6 and YUV/7 memory models)
-	UCHAR			RedMaskSize;        //		db	?	; size of direct color red mask in bits
-	UCHAR			RedFieldPosition;   //		db	?	; bit position of lsb of red mask
-	UCHAR			GreenMaskSize;      //		db	?	; size of direct color green mask in bits
-	UCHAR			GreenFieldPosition; //		db	?	; bit position of lsb of green mask
-	UCHAR			BlueMaskSize;       //		db	?	; size of direct color blue mask in bits
-	UCHAR			BlueFieldPosition;  //		db	?	; bit position of lsb of blue mask
-	UCHAR			RsvdMaskSize;       //		db	?	; size of direct color reserved mask in bits
-	UCHAR			RsvdFieldPosition;  //		db	?	; bit position of lsb of reserved mask
-	UCHAR			DirectColorModeInfo;//		db	?	; direct color mode attributes
-
-//; Mandatory information for VBE 2.0 and above
-	ULONG			PhysBasePtr;        //		dd	?	; physical address for flat memory frame buffer
-	ULONG			Reserved_1;         //		dd	0	; reserved - always set to 0
-	USHORT		Reserved_2;         //	  dw	0	; reserved - always set to 0
-
-//; Mandatory information for VBE 3.0 and above
-	USHORT		LinBytesPerScanLine;  //	dw	?	; bytes per scan line for linear modes
-	UCHAR			BnkNumberOfImagePages;//	db	?	; number of images for banked modes
-	UCHAR			LinNumberOfImagPages; //	db	?	; number of images for linear modes
-	UCHAR			LinRedMaskSize;       //	db	?	; size of direct color red mask(linear modes)
-	UCHAR			LinRedFieldPosition;  //	db	?	; bit position of lsb of red mask(linear modes)
-	UCHAR			LinGreenMaskSize;     //	db	?	; size of direct color green mask(linear modes)
-	UCHAR			LinGreenFieldPosition;//	db	?	; bit position of lsb of green mask(linear modes)
-	UCHAR			LinBlueMaskSize;      //	db	?	; size of direct color blue mask(linear modes)
-	UCHAR			LinBlueFieldPosition; //	db	?	; bit position of lsb of blue mask(linear modes)
-	UCHAR			LinRsvdMaskSize;      //	db	?	; size of direct color reserved mask(linear modes)
-	UCHAR			LinRsvdFieldPosition; //	db	?	; bit position of lsb of reserved mask(linear modes)
-	ULONG			MaxPixelClock;        //	dd	?	; maximum pixel clock(in Hz) for graphics mode
-	UCHAR			Reserved;             //	db	190 dup (0)
-} VESA_MODE_INFO_BLOCK;
-
-// BIOS function CALLS
-#define ATOM_BIOS_EXTENDED_FUNCTION_CODE        0xA0	        // ATI Extended Function code
-#define ATOM_BIOS_FUNCTION_COP_MODE             0x00
-#define ATOM_BIOS_FUNCTION_SHORT_QUERY1         0x04
-#define ATOM_BIOS_FUNCTION_SHORT_QUERY2         0x05
-#define ATOM_BIOS_FUNCTION_SHORT_QUERY3         0x06
-#define ATOM_BIOS_FUNCTION_GET_DDC              0x0B   
-#define ATOM_BIOS_FUNCTION_ASIC_DSTATE          0x0E
-#define ATOM_BIOS_FUNCTION_DEBUG_PLAY           0x0F
-#define ATOM_BIOS_FUNCTION_STV_STD              0x16
-#define ATOM_BIOS_FUNCTION_DEVICE_DET           0x17
-#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH        0x18
-
-#define ATOM_BIOS_FUNCTION_PANEL_CONTROL        0x82
-#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET       0x83
-#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH    0x84
-#define ATOM_BIOS_FUNCTION_HW_ICON              0x8A 
-#define ATOM_BIOS_FUNCTION_SET_CMOS             0x8B
-#define SUB_FUNCTION_UPDATE_DISPLAY_INFO        0x8000          // Sub function 80
-#define SUB_FUNCTION_UPDATE_EXPANSION_INFO      0x8100          // Sub function 80
-
-#define ATOM_BIOS_FUNCTION_DISPLAY_INFO         0x8D
-#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF        0x8E
-#define ATOM_BIOS_FUNCTION_VIDEO_STATE          0x8F 
-#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE    0x0300          // Sub function 03  
-#define ATOM_SUB_FUNCTION_GET_LIDSTATE          0x0700          // Sub function 7
-#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE  0x1400          // Notify caller the current thermal state
-#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300          // Notify caller the current critical state
-#define ATOM_SUB_FUNCTION_SET_LIDSTATE          0x8500          // Sub function 85
-#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
-#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT    0x9400          // Notify caller that ADC is supported
-     
-
-#define ATOM_BIOS_FUNCTION_VESA_DPMS            0x4F10          // Set DPMS 
-#define ATOM_SUB_FUNCTION_SET_DPMS              0x0001          // BL: Sub function 01 
-#define ATOM_SUB_FUNCTION_GET_DPMS              0x0002          // BL: Sub function 02 
-#define ATOM_PARAMETER_VESA_DPMS_ON             0x0000          // BH Parameter for DPMS ON.  
-#define ATOM_PARAMETER_VESA_DPMS_STANDBY        0x0100          // BH Parameter for DPMS STANDBY  
-#define ATOM_PARAMETER_VESA_DPMS_SUSPEND        0x0200          // BH Parameter for DPMS SUSPEND
-#define ATOM_PARAMETER_VESA_DPMS_OFF            0x0400          // BH Parameter for DPMS OFF
-#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON      0x0800          // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
-
-#define ATOM_BIOS_RETURN_CODE_MASK              0x0000FF00L
-#define ATOM_BIOS_REG_HIGH_MASK                 0x0000FF00L
-#define ATOM_BIOS_REG_LOW_MASK                  0x000000FFL
-
-// structure used for VBIOS only
-
-//DispOutInfoTable
-typedef struct _ASIC_TRANSMITTER_INFO
-{
-	USHORT usTransmitterObjId;
-	USHORT usSupportDevice;
-  UCHAR  ucTransmitterCmdTblId;
-	UCHAR  ucConfig;
-	UCHAR  ucEncoderID;					 //available 1st encoder ( default )
-	UCHAR  ucOptionEncoderID;    //available 2nd encoder ( optional )
-	UCHAR  uc2ndEncoderID;
-	UCHAR  ucReserved;
-}ASIC_TRANSMITTER_INFO;
-
-#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE          0x01
-#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE         0x02
-#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK    0xc4
-#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A             0x00
-#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B             0x04
-#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C             0x40
-#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D             0x44
-#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E             0x80
-#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F             0x84
-
-typedef struct _ASIC_ENCODER_INFO
-{
-	UCHAR ucEncoderID;
-	UCHAR ucEncoderConfig;
-  USHORT usEncoderCmdTblId;
-}ASIC_ENCODER_INFO;
-
-typedef struct _ATOM_DISP_OUT_INFO
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-	USHORT ptrTransmitterInfo;
-	USHORT ptrEncoderInfo;
-	ASIC_TRANSMITTER_INFO  asTransmitterInfo[1];
-	ASIC_ENCODER_INFO      asEncoderInfo[1];
-}ATOM_DISP_OUT_INFO;
-
-typedef struct _ATOM_DISP_OUT_INFO_V2
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-	USHORT ptrTransmitterInfo;
-	USHORT ptrEncoderInfo;
-  USHORT ptrMainCallParserFar;                  // direct address of main parser call in VBIOS binary. 
-	ASIC_TRANSMITTER_INFO  asTransmitterInfo[1];
-	ASIC_ENCODER_INFO      asEncoderInfo[1];
-}ATOM_DISP_OUT_INFO_V2;
-
-
-typedef struct _ATOM_DISP_CLOCK_ID {
-  UCHAR ucPpllId; 
-  UCHAR ucPpllAttribute;
-}ATOM_DISP_CLOCK_ID;
-
-// ucPpllAttribute
-#define CLOCK_SOURCE_SHAREABLE            0x01
-#define CLOCK_SOURCE_DP_MODE              0x02
-#define CLOCK_SOURCE_NONE_DP_MODE         0x04
-
-//DispOutInfoTable
-typedef struct _ASIC_TRANSMITTER_INFO_V2
-{
-	USHORT usTransmitterObjId;
-	USHORT usDispClkIdOffset;    // point to clock source id list supported by Encoder Object
-  UCHAR  ucTransmitterCmdTblId;
-	UCHAR  ucConfig;
-	UCHAR  ucEncoderID;					 // available 1st encoder ( default )
-	UCHAR  ucOptionEncoderID;    // available 2nd encoder ( optional )
-	UCHAR  uc2ndEncoderID;
-	UCHAR  ucReserved;
-}ASIC_TRANSMITTER_INFO_V2;
-
-typedef struct _ATOM_DISP_OUT_INFO_V3
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-	USHORT ptrTransmitterInfo;
-	USHORT ptrEncoderInfo;
-  USHORT ptrMainCallParserFar;                  // direct address of main parser call in VBIOS binary. 
-  USHORT usReserved;
-  UCHAR  ucDCERevision;   
-  UCHAR  ucMaxDispEngineNum;
-  UCHAR  ucMaxActiveDispEngineNum;
-  UCHAR  ucMaxPPLLNum;
-  UCHAR  ucCoreRefClkSource;                    // value of CORE_REF_CLK_SOURCE
-  UCHAR  ucDispCaps;
-  UCHAR  ucReserved[2];
-  ASIC_TRANSMITTER_INFO_V2  asTransmitterInfo[1];     // for alligment only
-}ATOM_DISP_OUT_INFO_V3;
-
-//ucDispCaps
-#define DISPLAY_CAPS__DP_PCLK_FROM_PPLL        0x01
-#define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED  0x02
-
-typedef enum CORE_REF_CLK_SOURCE{
-  CLOCK_SRC_XTALIN=0,
-  CLOCK_SRC_XO_IN=1,
-  CLOCK_SRC_XO_IN2=2,
-}CORE_REF_CLK_SOURCE;
-
-// DispDevicePriorityInfo
-typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-	USHORT asDevicePriority[16];
-}ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
-
-//ProcessAuxChannelTransactionTable
-typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
-{
-	USHORT	lpAuxRequest;
-	USHORT  lpDataOut;
-	UCHAR		ucChannelID;
-	union
-	{
-  UCHAR   ucReplyStatus;
-	UCHAR   ucDelay;
-	};
-  UCHAR   ucDataOutLen;
-	UCHAR   ucReserved;
-}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
-
-//ProcessAuxChannelTransactionTable
-typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
-{
-	USHORT	lpAuxRequest;
-	USHORT  lpDataOut;
-	UCHAR		ucChannelID;
-	union
-	{
-  UCHAR   ucReplyStatus;
-	UCHAR   ucDelay;
-	};
-  UCHAR   ucDataOutLen;
-	UCHAR   ucHPD_ID;                                       //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
-}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
-
-#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION			PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
-
-//GetSinkType
-
-typedef struct _DP_ENCODER_SERVICE_PARAMETERS
-{
-	USHORT ucLinkClock;
-	union 
-	{
-	UCHAR ucConfig;				// for DP training command
-	UCHAR ucI2cId;				// use for GET_SINK_TYPE command
-	};
-	UCHAR ucAction;
-	UCHAR ucStatus;
-	UCHAR ucLaneNum;
-	UCHAR ucReserved[2];
-}DP_ENCODER_SERVICE_PARAMETERS;
-
-// ucAction
-#define ATOM_DP_ACTION_GET_SINK_TYPE							0x01
-/* obselete */
-#define ATOM_DP_ACTION_TRAINING_START							0x02
-#define ATOM_DP_ACTION_TRAINING_COMPLETE					0x03
-#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL				0x04
-#define ATOM_DP_ACTION_SET_VSWING_PREEMP					0x05
-#define ATOM_DP_ACTION_GET_VSWING_PREEMP					0x06
-#define ATOM_DP_ACTION_BLANKING                   0x07
-
-// ucConfig
-#define ATOM_DP_CONFIG_ENCODER_SEL_MASK						0x03
-#define ATOM_DP_CONFIG_DIG1_ENCODER								0x00
-#define ATOM_DP_CONFIG_DIG2_ENCODER								0x01
-#define ATOM_DP_CONFIG_EXTERNAL_ENCODER						0x02
-#define ATOM_DP_CONFIG_LINK_SEL_MASK							0x04
-#define ATOM_DP_CONFIG_LINK_A											0x00
-#define ATOM_DP_CONFIG_LINK_B											0x04
-/* /obselete */
-#define DP_ENCODER_SERVICE_PS_ALLOCATION				WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
-
-
-typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2
-{
-	USHORT usExtEncoderObjId;   // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
-  UCHAR  ucAuxId;
-  UCHAR  ucAction;
-  UCHAR  ucSinkType;          // Iput and Output parameters. 
-  UCHAR  ucHPDId;             // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
-	UCHAR  ucReserved[2];
-}DP_ENCODER_SERVICE_PARAMETERS_V2;
-
-typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
-{
-  DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;
-  PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;
-}DP_ENCODER_SERVICE_PS_ALLOCATION_V2;
-
-// ucAction
-#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE							0x01
-#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION			    0x02
-
-
-// DP_TRAINING_TABLE
-#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR				ATOM_DP_TRAINING_TBL_ADDR		
-#define DPCD_SET_SS_CNTL_TBL_ADDR													(ATOM_DP_TRAINING_TBL_ADDR + 8 )
-#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR							(ATOM_DP_TRAINING_TBL_ADDR + 16 )
-#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR								(ATOM_DP_TRAINING_TBL_ADDR + 24 )
-#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR								(ATOM_DP_TRAINING_TBL_ADDR + 32)
-#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR							(ATOM_DP_TRAINING_TBL_ADDR + 40)
-#define	DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR							(ATOM_DP_TRAINING_TBL_ADDR + 48)
-#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR								(ATOM_DP_TRAINING_TBL_ADDR + 60)
-#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR											(ATOM_DP_TRAINING_TBL_ADDR + 64)
-#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR								(ATOM_DP_TRAINING_TBL_ADDR + 72)
-#define DP_I2C_AUX_DDC_READ_TBL_ADDR											(ATOM_DP_TRAINING_TBL_ADDR + 76)
-#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR                 (ATOM_DP_TRAINING_TBL_ADDR + 80) 
-#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR									(ATOM_DP_TRAINING_TBL_ADDR + 84)
-
-typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
-{
-	UCHAR   ucI2CSpeed;
- 	union
-	{
-   UCHAR ucRegIndex;
-   UCHAR ucStatus;
-	};
-	USHORT  lpI2CDataOut;
-  UCHAR   ucFlag;               
-  UCHAR   ucTransBytes;
-  UCHAR   ucSlaveAddr;
-  UCHAR   ucLineNumber;
-}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
-
-#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION       PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
-
-//ucFlag
-#define HW_I2C_WRITE        1
-#define HW_I2C_READ         0
-#define I2C_2BYTE_ADDR      0x02
-
-/****************************************************************************/	
-// Structures used by HW_Misc_OperationTable
-/****************************************************************************/	
-typedef struct  _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 
-{
-  UCHAR  ucCmd;                //  Input: To tell which action to take
-  UCHAR  ucReserved[3];
-  ULONG  ulReserved;
-}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 
-
-typedef struct  _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 
-{
-  UCHAR  ucReturnCode;        // Output: Return value base on action was taken
-  UCHAR  ucReserved[3];
-  ULONG  ulReserved;
-}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1;
-
-// Actions code
-#define  ATOM_GET_SDI_SUPPORT              0xF0
-
-// Return code 
-#define  ATOM_UNKNOWN_CMD                   0
-#define  ATOM_FEATURE_NOT_SUPPORTED         1
-#define  ATOM_FEATURE_SUPPORTED             2
-
-typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION
-{
-	ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1        sInput_Output;
-	PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS         sReserved; 
-}ATOM_HW_MISC_OPERATION_PS_ALLOCATION;
-
-/****************************************************************************/	
-
-typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
-{
-   UCHAR ucHWBlkInst;                // HW block instance, 0, 1, 2, ...
-   UCHAR ucReserved[3]; 
-}SET_HWBLOCK_INSTANCE_PARAMETER_V2;
-
-#define HWBLKINST_INSTANCE_MASK       0x07
-#define HWBLKINST_HWBLK_MASK          0xF0
-#define HWBLKINST_HWBLK_SHIFT         0x04
-
-//ucHWBlock
-#define SELECT_DISP_ENGINE            0
-#define SELECT_DISP_PLL               1
-#define SELECT_DCIO_UNIPHY_LINK0      2
-#define SELECT_DCIO_UNIPHY_LINK1      3
-#define SELECT_DCIO_IMPCAL            4
-#define SELECT_DCIO_DIG               6
-#define SELECT_CRTC_PIXEL_RATE        7
-#define SELECT_VGA_BLK                8
-
-// DIGTransmitterInfoTable structure used to program UNIPHY settings 
-typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{  
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  USHORT usDPVsPreEmphSettingOffset;     // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 
-  USHORT usPhyAnalogRegListOffset;       // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 
-  USHORT usPhyAnalogSettingOffset;       // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
-  USHORT usPhyPllRegListOffset;          // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 
-  USHORT usPhyPllSettingOffset;          // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
-}DIG_TRANSMITTER_INFO_HEADER_V3_1;
-
-typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{  
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  USHORT usDPVsPreEmphSettingOffset;     // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 
-  USHORT usPhyAnalogRegListOffset;       // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 
-  USHORT usPhyAnalogSettingOffset;       // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
-  USHORT usPhyPllRegListOffset;          // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 
-  USHORT usPhyPllSettingOffset;          // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
-  USHORT usDPSSRegListOffset;            // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 
-  USHORT usDPSSSettingOffset;            // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
-}DIG_TRANSMITTER_INFO_HEADER_V3_2;
-
-typedef struct _CLOCK_CONDITION_REGESTER_INFO{
-  USHORT usRegisterIndex;
-  UCHAR  ucStartBit;
-  UCHAR  ucEndBit;
-}CLOCK_CONDITION_REGESTER_INFO;
-
-typedef struct _CLOCK_CONDITION_SETTING_ENTRY{
-  USHORT usMaxClockFreq;
-  UCHAR  ucEncodeMode;
-  UCHAR  ucPhySel;
-  ULONG  ulAnalogSetting[1];
-}CLOCK_CONDITION_SETTING_ENTRY;
-
-typedef struct _CLOCK_CONDITION_SETTING_INFO{
-  USHORT usEntrySize;
-  CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];
-}CLOCK_CONDITION_SETTING_INFO;
-
-typedef struct _PHY_CONDITION_REG_VAL{
-  ULONG  ulCondition;
-  ULONG  ulRegVal;
-}PHY_CONDITION_REG_VAL;
-
-typedef struct _PHY_CONDITION_REG_VAL_V2{
-  ULONG  ulCondition;
-  UCHAR  ucCondition2;
-  ULONG  ulRegVal;
-}PHY_CONDITION_REG_VAL_V2;
-
-typedef struct _PHY_CONDITION_REG_INFO{
-  USHORT usRegIndex;
-  USHORT usSize;
-  PHY_CONDITION_REG_VAL asRegVal[1];
-}PHY_CONDITION_REG_INFO;
-
-typedef struct _PHY_CONDITION_REG_INFO_V2{
-  USHORT usRegIndex;
-  USHORT usSize;
-  PHY_CONDITION_REG_VAL_V2 asRegVal[1];
-}PHY_CONDITION_REG_INFO_V2;
-
-typedef struct _PHY_ANALOG_SETTING_INFO{
-  UCHAR  ucEncodeMode;
-  UCHAR  ucPhySel;
-  USHORT usSize;
-  PHY_CONDITION_REG_INFO  asAnalogSetting[1];
-}PHY_ANALOG_SETTING_INFO;
-
-typedef struct _PHY_ANALOG_SETTING_INFO_V2{
-  UCHAR  ucEncodeMode;
-  UCHAR  ucPhySel;
-  USHORT usSize;
-  PHY_CONDITION_REG_INFO_V2  asAnalogSetting[1];
-}PHY_ANALOG_SETTING_INFO_V2;
-
-typedef struct _GFX_HAVESTING_PARAMETERS {
-  UCHAR ucGfxBlkId;                        //GFX blk id to be harvested, like CU, RB or PRIM
-  UCHAR ucReserved;                        //reserved 
-  UCHAR ucActiveUnitNumPerSH;              //requested active CU/RB/PRIM number per shader array
-  UCHAR ucMaxUnitNumPerSH;                 //max CU/RB/PRIM number per shader array   
-} GFX_HAVESTING_PARAMETERS;
-
-//ucGfxBlkId
-#define GFX_HARVESTING_CU_ID               0
-#define GFX_HARVESTING_RB_ID               1
-#define GFX_HARVESTING_PRIM_ID             2
-
-/****************************************************************************/	
-//Portion VI: Definitinos for vbios MC scratch registers that driver used
-/****************************************************************************/
-
-#define MC_MISC0__MEMORY_TYPE_MASK    0xF0000000
-#define MC_MISC0__MEMORY_TYPE__GDDR1  0x10000000
-#define MC_MISC0__MEMORY_TYPE__DDR2   0x20000000
-#define MC_MISC0__MEMORY_TYPE__GDDR3  0x30000000
-#define MC_MISC0__MEMORY_TYPE__GDDR4  0x40000000
-#define MC_MISC0__MEMORY_TYPE__GDDR5  0x50000000
-#define MC_MISC0__MEMORY_TYPE__HBM    0x60000000
-#define MC_MISC0__MEMORY_TYPE__DDR3   0xB0000000
-
-#define ATOM_MEM_TYPE_DDR_STRING      "DDR"
-#define ATOM_MEM_TYPE_DDR2_STRING     "DDR2"
-#define ATOM_MEM_TYPE_GDDR3_STRING    "GDDR3"
-#define ATOM_MEM_TYPE_GDDR4_STRING    "GDDR4"
-#define ATOM_MEM_TYPE_GDDR5_STRING    "GDDR5"
-#define ATOM_MEM_TYPE_HBM_STRING      "HBM"
-#define ATOM_MEM_TYPE_DDR3_STRING     "DDR3"
-
-/****************************************************************************/	
-//Portion VI: Definitinos being oboselete
-/****************************************************************************/
-
-//==========================================================================================
-//Remove the definitions below when driver is ready!
-typedef struct _ATOM_DAC_INFO
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  USHORT                   usMaxFrequency;      // in 10kHz unit
-  USHORT                   usReserved;
-}ATOM_DAC_INFO;
-
-
-typedef struct  _COMPASSIONATE_DATA           
-{
-  ATOM_COMMON_TABLE_HEADER sHeader; 
-
-  //==============================  DAC1 portion
-  UCHAR   ucDAC1_BG_Adjustment;
-  UCHAR   ucDAC1_DAC_Adjustment;
-  USHORT  usDAC1_FORCE_Data;
-  //==============================  DAC2 portion
-  UCHAR   ucDAC2_CRT2_BG_Adjustment;
-  UCHAR   ucDAC2_CRT2_DAC_Adjustment;
-  USHORT  usDAC2_CRT2_FORCE_Data;
-  USHORT  usDAC2_CRT2_MUX_RegisterIndex;
-  UCHAR   ucDAC2_CRT2_MUX_RegisterInfo;     //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
-  UCHAR   ucDAC2_NTSC_BG_Adjustment;
-  UCHAR   ucDAC2_NTSC_DAC_Adjustment;
-  USHORT  usDAC2_TV1_FORCE_Data;
-  USHORT  usDAC2_TV1_MUX_RegisterIndex;
-  UCHAR   ucDAC2_TV1_MUX_RegisterInfo;      //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
-  UCHAR   ucDAC2_CV_BG_Adjustment;
-  UCHAR   ucDAC2_CV_DAC_Adjustment;
-  USHORT  usDAC2_CV_FORCE_Data;
-  USHORT  usDAC2_CV_MUX_RegisterIndex;
-  UCHAR   ucDAC2_CV_MUX_RegisterInfo;       //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
-  UCHAR   ucDAC2_PAL_BG_Adjustment;
-  UCHAR   ucDAC2_PAL_DAC_Adjustment;
-  USHORT  usDAC2_TV2_FORCE_Data;
-}COMPASSIONATE_DATA;
-
-/****************************Supported Device Info Table Definitions**********************/
-//  ucConnectInfo:
-//    [7:4] - connector type
-//      = 1   - VGA connector   
-//      = 2   - DVI-I
-//      = 3   - DVI-D
-//      = 4   - DVI-A
-//      = 5   - SVIDEO
-//      = 6   - COMPOSITE
-//      = 7   - LVDS
-//      = 8   - DIGITAL LINK
-//      = 9   - SCART
-//      = 0xA - HDMI_type A
-//      = 0xB - HDMI_type B
-//      = 0xE - Special case1 (DVI+DIN)
-//      Others=TBD
-//    [3:0] - DAC Associated
-//      = 0   - no DAC
-//      = 1   - DACA
-//      = 2   - DACB
-//      = 3   - External DAC
-//      Others=TBD
-//    
-
-typedef struct _ATOM_CONNECTOR_INFO
-{
-#if ATOM_BIG_ENDIAN
-  UCHAR   bfConnectorType:4;
-  UCHAR   bfAssociatedDAC:4;
-#else
-  UCHAR   bfAssociatedDAC:4;
-  UCHAR   bfConnectorType:4;
-#endif
-}ATOM_CONNECTOR_INFO;
-
-typedef union _ATOM_CONNECTOR_INFO_ACCESS
-{
-  ATOM_CONNECTOR_INFO sbfAccess;
-  UCHAR               ucAccess;
-}ATOM_CONNECTOR_INFO_ACCESS;
-
-typedef struct _ATOM_CONNECTOR_INFO_I2C
-{
-  ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
-  ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;
-}ATOM_CONNECTOR_INFO_I2C;
-
-
-typedef struct _ATOM_SUPPORTED_DEVICES_INFO
-{ 
-  ATOM_COMMON_TABLE_HEADER	sHeader;
-  USHORT                    usDeviceSupport;
-  ATOM_CONNECTOR_INFO_I2C   asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
-}ATOM_SUPPORTED_DEVICES_INFO;
-
-#define NO_INT_SRC_MAPPED       0xFF
-
-typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
-{
-  UCHAR   ucIntSrcBitmap;
-}ATOM_CONNECTOR_INC_SRC_BITMAP;
-
-typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
-{ 
-  ATOM_COMMON_TABLE_HEADER      sHeader;
-  USHORT                        usDeviceSupport;
-  ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
-  ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
-}ATOM_SUPPORTED_DEVICES_INFO_2;
-
-typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
-{ 
-  ATOM_COMMON_TABLE_HEADER      sHeader;
-  USHORT                        usDeviceSupport;
-  ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
-  ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
-}ATOM_SUPPORTED_DEVICES_INFO_2d1;
-
-#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
-
-
-
-typedef struct _ATOM_MISC_CONTROL_INFO
-{
-   USHORT usFrequency;
-   UCHAR  ucPLL_ChargePump;				                // PLL charge-pump gain control
-   UCHAR  ucPLL_DutyCycle;				                // PLL duty cycle control
-   UCHAR  ucPLL_VCO_Gain;				                  // PLL VCO gain control
-   UCHAR  ucPLL_VoltageSwing;			                // PLL driver voltage swing control
-}ATOM_MISC_CONTROL_INFO;  
-
-
-#define ATOM_MAX_MISC_INFO       4
-
-typedef struct _ATOM_TMDS_INFO
-{
-  ATOM_COMMON_TABLE_HEADER sHeader;  
-  USHORT							usMaxFrequency;             // in 10Khz
-  ATOM_MISC_CONTROL_INFO				asMiscInfo[ATOM_MAX_MISC_INFO];
-}ATOM_TMDS_INFO;
-
-
-typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
-{
-  UCHAR ucTVStandard;     //Same as TV standards defined above, 
-  UCHAR ucPadding[1];
-}ATOM_ENCODER_ANALOG_ATTRIBUTE;
-
-typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
-{
-  UCHAR ucAttribute;      //Same as other digital encoder attributes defined above
-  UCHAR ucPadding[1];		
-}ATOM_ENCODER_DIGITAL_ATTRIBUTE;
-
-typedef union _ATOM_ENCODER_ATTRIBUTE
-{
-  ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
-  ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
-}ATOM_ENCODER_ATTRIBUTE;
-
-
-typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
-{
-  USHORT usPixelClock; 
-  USHORT usEncoderID; 
-  UCHAR  ucDeviceType;												//Use ATOM_DEVICE_xxx1_Index to indicate device type only.	
-  UCHAR  ucAction;														//ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
-  ATOM_ENCODER_ATTRIBUTE usDevAttr;     		
-}DVO_ENCODER_CONTROL_PARAMETERS;
-
-typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
-{                               
-  DVO_ENCODER_CONTROL_PARAMETERS    sDVOEncoder;
-  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
-}DVO_ENCODER_CONTROL_PS_ALLOCATION;
-
-
-#define ATOM_XTMDS_ASIC_SI164_ID        1
-#define ATOM_XTMDS_ASIC_SI178_ID        2
-#define ATOM_XTMDS_ASIC_TFP513_ID       3
-#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
-#define ATOM_XTMDS_SUPPORTED_DUALLINK   0x00000002
-#define ATOM_XTMDS_MVPU_FPGA            0x00000004
-
-                           
-typedef struct _ATOM_XTMDS_INFO
-{
-  ATOM_COMMON_TABLE_HEADER   sHeader;  
-  USHORT                     usSingleLinkMaxFrequency; 
-  ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;           //Point the ID on which I2C is used to control external chip
-  UCHAR                      ucXtransimitterID;          
-  UCHAR                      ucSupportedLink;    // Bit field, bit0=1, single link supported;bit1=1,dual link supported
-  UCHAR                      ucSequnceAlterID;   // Even with the same external TMDS asic, it's possible that the program seqence alters 
-                                                 // due to design. This ID is used to alert driver that the sequence is not "standard"!              
-  UCHAR                      ucMasterAddress;    // Address to control Master xTMDS Chip
-  UCHAR                      ucSlaveAddress;     // Address to control Slave xTMDS Chip
-}ATOM_XTMDS_INFO;
-
-typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
-{  
-  UCHAR ucEnable;                     // ATOM_ENABLE=On or ATOM_DISABLE=Off
-  UCHAR ucDevice;                     // ATOM_DEVICE_DFP1_INDEX....
-  UCHAR ucPadding[2];             
-}DFP_DPMS_STATUS_CHANGE_PARAMETERS;
-
-/****************************Legacy Power Play Table Definitions **********************/
-
-//Definitions for ulPowerPlayMiscInfo
-#define ATOM_PM_MISCINFO_SPLIT_CLOCK                     0x00000000L
-#define ATOM_PM_MISCINFO_USING_MCLK_SRC                  0x00000001L
-#define ATOM_PM_MISCINFO_USING_SCLK_SRC                  0x00000002L
-
-#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT            0x00000004L
-#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH        0x00000008L
-
-#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN             0x00000010L
-
-#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN          0x00000020L
-#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN          0x00000040L
-#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE                 0x00000080L  //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program  
- 
-#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN      0x00000100L
-#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN         0x00000200L
-#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN              0x00000400L
-#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN                 0x00000800L
-#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE     0x00001000L
-#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
-#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE            0x00004000L
-
-#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE             0x00008000L
-#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE                 0x00010000L 
-#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE                 0x00020000L
-#define ATOM_PM_MISCINFO_POWER_SAVING_MODE               0x00040000L
-#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE              0x00080000L
-
-#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK           0x00300000L  //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
-#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT          20 
-
-#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE                 0x00400000L
-#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2      0x00800000L
-#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4      0x01000000L
-#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN            0x02000000L  //When set, Dynamic 
-#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN        0x04000000L  //When set, Dynamic
-#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN              0x08000000L  //When set, This mode is for acceleated 3D mode
-
-#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK   0x70000000L  //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 
-#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT  28
-#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS                0x80000000L
-
-#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE            0x00000001L
-#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT          0x00000002L
-#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN           0x00000004L
-#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO            0x00000008L
-#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE              0x00000010L
-#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN       0x00000020L
-#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE         0x00000040L  //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 
-                                                                      //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
-#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC                0x00000080L
-#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN                0x00000100L
-#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE               0x00000200L 
-
-//ucTableFormatRevision=1
-//ucTableContentRevision=1
-typedef struct  _ATOM_POWERMODE_INFO
-{
-  ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
-  ULONG     ulReserved1;                // must set to 0
-  ULONG     ulReserved2;                // must set to 0
-  USHORT    usEngineClock;
-  USHORT    usMemoryClock;
-  UCHAR     ucVoltageDropIndex;         // index to GPIO table
-  UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
-  UCHAR     ucMinTemperature;
-  UCHAR     ucMaxTemperature;
-  UCHAR     ucNumPciELanes;             // number of PCIE lanes
-}ATOM_POWERMODE_INFO;
-
-//ucTableFormatRevision=2
-//ucTableContentRevision=1
-typedef struct  _ATOM_POWERMODE_INFO_V2
-{
-  ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
-  ULONG     ulMiscInfo2;                
-  ULONG     ulEngineClock;                
-  ULONG     ulMemoryClock;
-  UCHAR     ucVoltageDropIndex;         // index to GPIO table
-  UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
-  UCHAR     ucMinTemperature;
-  UCHAR     ucMaxTemperature;
-  UCHAR     ucNumPciELanes;             // number of PCIE lanes
-}ATOM_POWERMODE_INFO_V2;
-
-//ucTableFormatRevision=2
-//ucTableContentRevision=2
-typedef struct  _ATOM_POWERMODE_INFO_V3
-{
-  ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
-  ULONG     ulMiscInfo2;                
-  ULONG     ulEngineClock;                
-  ULONG     ulMemoryClock;
-  UCHAR     ucVoltageDropIndex;         // index to Core (VDDC) votage table
-  UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
-  UCHAR     ucMinTemperature;
-  UCHAR     ucMaxTemperature;
-  UCHAR     ucNumPciELanes;             // number of PCIE lanes
-  UCHAR     ucVDDCI_VoltageDropIndex;   // index to VDDCI votage table
-}ATOM_POWERMODE_INFO_V3;
-
-
-#define ATOM_MAX_NUMBEROF_POWER_BLOCK  8
-
-#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN            0x01
-#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE         0x02
-
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63      0x01
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032   0x02
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030   0x03
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649   0x04
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64      0x05
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375    0x06
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512   0x07	// Andigilog
-
-
-typedef struct  _ATOM_POWERPLAY_INFO
-{
-  ATOM_COMMON_TABLE_HEADER	sHeader; 
-  UCHAR    ucOverdriveThermalController;
-  UCHAR    ucOverdriveI2cLine;
-  UCHAR    ucOverdriveIntBitmap;
-  UCHAR    ucOverdriveControllerAddress;
-  UCHAR    ucSizeOfPowerModeEntry;
-  UCHAR    ucNumOfPowerModeEntries;
-  ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
-}ATOM_POWERPLAY_INFO;
-
-typedef struct  _ATOM_POWERPLAY_INFO_V2
-{
-  ATOM_COMMON_TABLE_HEADER	sHeader; 
-  UCHAR    ucOverdriveThermalController;
-  UCHAR    ucOverdriveI2cLine;
-  UCHAR    ucOverdriveIntBitmap;
-  UCHAR    ucOverdriveControllerAddress;
-  UCHAR    ucSizeOfPowerModeEntry;
-  UCHAR    ucNumOfPowerModeEntries;
-  ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
-}ATOM_POWERPLAY_INFO_V2;
-  
-typedef struct  _ATOM_POWERPLAY_INFO_V3
-{
-  ATOM_COMMON_TABLE_HEADER	sHeader; 
-  UCHAR    ucOverdriveThermalController;
-  UCHAR    ucOverdriveI2cLine;
-  UCHAR    ucOverdriveIntBitmap;
-  UCHAR    ucOverdriveControllerAddress;
-  UCHAR    ucSizeOfPowerModeEntry;
-  UCHAR    ucNumOfPowerModeEntries;
-  ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
-}ATOM_POWERPLAY_INFO_V3;
-
-
-// Following definitions are for compatibility issue in different SW components. 
-#define ATOM_MASTER_DATA_TABLE_REVISION   0x01
-#define Object_Info												Object_Header			
-#define	AdjustARB_SEQ											MC_InitParameter
-#define	VRAM_GPIO_DetectionInfo						VoltageObjectInfo
-#define	ASIC_VDDCI_Info                   ASIC_ProfilingInfo														
-#define ASIC_MVDDQ_Info										MemoryTrainingInfo
-#define SS_Info                           PPLL_SS_Info                      
-#define ASIC_MVDDC_Info                   ASIC_InternalSS_Info
-#define DispDevicePriorityInfo						SaveRestoreInfo
-#define DispOutInfo												TV_VideoMode
-
-
-#define ATOM_ENCODER_OBJECT_TABLE         ATOM_OBJECT_TABLE
-#define ATOM_CONNECTOR_OBJECT_TABLE       ATOM_OBJECT_TABLE
-
-//New device naming, remove them when both DAL/VBIOS is ready
-#define DFP2I_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
-#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
-
-#define DFP1X_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
-#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
-
-#define DFP1I_OUTPUT_CONTROL_PARAMETERS    DFP1_OUTPUT_CONTROL_PARAMETERS
-#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define ATOM_DEVICE_DFP1I_SUPPORT          ATOM_DEVICE_DFP1_SUPPORT
-#define ATOM_DEVICE_DFP1X_SUPPORT          ATOM_DEVICE_DFP2_SUPPORT
-
-#define ATOM_DEVICE_DFP1I_INDEX            ATOM_DEVICE_DFP1_INDEX
-#define ATOM_DEVICE_DFP1X_INDEX            ATOM_DEVICE_DFP2_INDEX
- 
-#define ATOM_DEVICE_DFP2I_INDEX            0x00000009
-#define ATOM_DEVICE_DFP2I_SUPPORT          (0x1L << ATOM_DEVICE_DFP2I_INDEX)
-
-#define ATOM_S0_DFP1I                      ATOM_S0_DFP1
-#define ATOM_S0_DFP1X                      ATOM_S0_DFP2
-
-#define ATOM_S0_DFP2I                      0x00200000L
-#define ATOM_S0_DFP2Ib2                    0x20
-
-#define ATOM_S2_DFP1I_DPMS_STATE           ATOM_S2_DFP1_DPMS_STATE
-#define ATOM_S2_DFP1X_DPMS_STATE           ATOM_S2_DFP2_DPMS_STATE
-
-#define ATOM_S2_DFP2I_DPMS_STATE           0x02000000L
-#define ATOM_S2_DFP2I_DPMS_STATEb3         0x02
-
-#define ATOM_S3_DFP2I_ACTIVEb1             0x02
-
-#define ATOM_S3_DFP1I_ACTIVE               ATOM_S3_DFP1_ACTIVE 
-#define ATOM_S3_DFP1X_ACTIVE               ATOM_S3_DFP2_ACTIVE
-
-#define ATOM_S3_DFP2I_ACTIVE               0x00000200L
-
-#define ATOM_S3_DFP1I_CRTC_ACTIVE          ATOM_S3_DFP1_CRTC_ACTIVE
-#define ATOM_S3_DFP1X_CRTC_ACTIVE          ATOM_S3_DFP2_CRTC_ACTIVE
-#define ATOM_S3_DFP2I_CRTC_ACTIVE          0x02000000L
-
-#define ATOM_S3_DFP2I_CRTC_ACTIVEb3        0x02
-#define ATOM_S5_DOS_REQ_DFP2Ib1            0x02
-
-#define ATOM_S5_DOS_REQ_DFP2I              0x0200
-#define ATOM_S6_ACC_REQ_DFP1I              ATOM_S6_ACC_REQ_DFP1
-#define ATOM_S6_ACC_REQ_DFP1X              ATOM_S6_ACC_REQ_DFP2
-
-#define ATOM_S6_ACC_REQ_DFP2Ib3            0x02
-#define ATOM_S6_ACC_REQ_DFP2I              0x02000000L
-
-#define TMDS1XEncoderControl               DVOEncoderControl           
-#define DFP1XOutputControl                 DVOOutputControl
-
-#define ExternalDFPOutputControl           DFP1XOutputControl
-#define EnableExternalTMDS_Encoder         TMDS1XEncoderControl
-
-#define DFP1IOutputControl                 TMDSAOutputControl
-#define DFP2IOutputControl                 LVTMAOutputControl      
-
-#define DAC1_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
-#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
-
-#define DAC2_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
-#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
-
-#define ucDac1Standard  ucDacStandard
-#define ucDac2Standard  ucDacStandard  
-
-#define TMDS1EncoderControl TMDSAEncoderControl
-#define TMDS2EncoderControl LVTMAEncoderControl
-
-#define DFP1OutputControl   TMDSAOutputControl
-#define DFP2OutputControl   LVTMAOutputControl
-#define CRT1OutputControl   DAC1OutputControl
-#define CRT2OutputControl   DAC2OutputControl
-
-//These two lines will be removed for sure in a few days, will follow up with Michael V.
-#define EnableLVDS_SS   EnableSpreadSpectrumOnPPLL
-#define ENABLE_LVDS_SS_PARAMETERS_V3  ENABLE_SPREAD_SPECTRUM_ON_PPLL  
-
-//#define ATOM_S2_CRT1_DPMS_STATE         0x00010000L
-//#define ATOM_S2_LCD1_DPMS_STATE	        ATOM_S2_CRT1_DPMS_STATE
-//#define ATOM_S2_TV1_DPMS_STATE          ATOM_S2_CRT1_DPMS_STATE
-//#define ATOM_S2_DFP1_DPMS_STATE         ATOM_S2_CRT1_DPMS_STATE
-//#define ATOM_S2_CRT2_DPMS_STATE         ATOM_S2_CRT1_DPMS_STATE
-
-#define ATOM_S6_ACC_REQ_TV2             0x00400000L
-#define ATOM_DEVICE_TV2_INDEX           0x00000006
-#define ATOM_DEVICE_TV2_SUPPORT         (0x1L << ATOM_DEVICE_TV2_INDEX)
-#define ATOM_S0_TV2                     0x00100000L
-#define ATOM_S3_TV2_ACTIVE              ATOM_S3_DFP6_ACTIVE
-#define ATOM_S3_TV2_CRTC_ACTIVE         ATOM_S3_DFP6_CRTC_ACTIVE
-
-//
-#define ATOM_S2_CRT1_DPMS_STATE         0x00010000L
-#define ATOM_S2_LCD1_DPMS_STATE	        0x00020000L
-#define ATOM_S2_TV1_DPMS_STATE          0x00040000L
-#define ATOM_S2_DFP1_DPMS_STATE         0x00080000L
-#define ATOM_S2_CRT2_DPMS_STATE         0x00100000L
-#define ATOM_S2_LCD2_DPMS_STATE         0x00200000L
-#define ATOM_S2_TV2_DPMS_STATE          0x00400000L
-#define ATOM_S2_DFP2_DPMS_STATE         0x00800000L
-#define ATOM_S2_CV_DPMS_STATE           0x01000000L
-#define ATOM_S2_DFP3_DPMS_STATE					0x02000000L
-#define ATOM_S2_DFP4_DPMS_STATE					0x04000000L
-#define ATOM_S2_DFP5_DPMS_STATE					0x08000000L
-
-#define ATOM_S2_CRT1_DPMS_STATEb2       0x01
-#define ATOM_S2_LCD1_DPMS_STATEb2       0x02
-#define ATOM_S2_TV1_DPMS_STATEb2        0x04
-#define ATOM_S2_DFP1_DPMS_STATEb2       0x08
-#define ATOM_S2_CRT2_DPMS_STATEb2       0x10
-#define ATOM_S2_LCD2_DPMS_STATEb2       0x20
-#define ATOM_S2_TV2_DPMS_STATEb2        0x40
-#define ATOM_S2_DFP2_DPMS_STATEb2       0x80
-#define ATOM_S2_CV_DPMS_STATEb3         0x01
-#define ATOM_S2_DFP3_DPMS_STATEb3				0x02
-#define ATOM_S2_DFP4_DPMS_STATEb3				0x04
-#define ATOM_S2_DFP5_DPMS_STATEb3				0x08
-
-#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3	0x20
-#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
-#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3  0x80
-
-/*********************************************************************************/
-
-#pragma pack() // BIOS data must use byte alignment
-
-//
-// AMD ACPI Table
-//
-#pragma pack(1)
-
-typedef struct {
-  ULONG Signature;
-  ULONG TableLength;      //Length
-  UCHAR Revision;
-  UCHAR Checksum;
-  UCHAR OemId[6];
-  UCHAR OemTableId[8];    //UINT64  OemTableId;
-  ULONG OemRevision;
-  ULONG CreatorId;
-  ULONG CreatorRevision;
-} AMD_ACPI_DESCRIPTION_HEADER;
-/*
-//EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h
-typedef struct {
-  UINT32  Signature;       //0x0
-  UINT32  Length;          //0x4
-  UINT8   Revision;        //0x8
-  UINT8   Checksum;        //0x9
-  UINT8   OemId[6];        //0xA
-  UINT64  OemTableId;      //0x10
-  UINT32  OemRevision;     //0x18
-  UINT32  CreatorId;       //0x1C
-  UINT32  CreatorRevision; //0x20
-}EFI_ACPI_DESCRIPTION_HEADER;
-*/
-typedef struct {
-  AMD_ACPI_DESCRIPTION_HEADER SHeader;
-  UCHAR TableUUID[16];    //0x24
-  ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure.
-  ULONG Lib1ImageOffset;  //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure.
-  ULONG Reserved[4];      //0x3C
-}UEFI_ACPI_VFCT;
-
-typedef struct {
-  ULONG  PCIBus;          //0x4C
-  ULONG  PCIDevice;       //0x50
-  ULONG  PCIFunction;     //0x54
-  USHORT VendorID;        //0x58
-  USHORT DeviceID;        //0x5A
-  USHORT SSVID;           //0x5C
-  USHORT SSID;            //0x5E
-  ULONG  Revision;        //0x60
-  ULONG  ImageLength;     //0x64
-}VFCT_IMAGE_HEADER;
-
-
-typedef struct {
-  VFCT_IMAGE_HEADER	VbiosHeader;
-  UCHAR	VbiosContent[1];
-}GOP_VBIOS_CONTENT;
-
-typedef struct {
-  VFCT_IMAGE_HEADER	Lib1Header;
-  UCHAR	Lib1Content[1];
-}GOP_LIB1_CONTENT;
-
-#pragma pack()
-
-
-#endif /* _ATOMBIOS_H */
-
-#include "pptable.h"
-
diff --git a/hw/display/avivod.h b/hw/display/avivod.h
deleted file mode 100644
index 3c391e7e9f..0000000000
--- a/hw/display/avivod.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2009 Advanced Micro Devices, Inc.
- * Copyright 2009 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef AVIVOD_H
-#define AVIVOD_H
-
-
-#define	D1CRTC_CONTROL					0x6080
-#define		CRTC_EN						(1 << 0)
-#define	D1CRTC_STATUS					0x609c
-#define	D1CRTC_UPDATE_LOCK				0x60E8
-#define	D1GRPH_PRIMARY_SURFACE_ADDRESS			0x6110
-#define	D1GRPH_SECONDARY_SURFACE_ADDRESS		0x6118
-
-#define	D2CRTC_CONTROL					0x6880
-#define	D2CRTC_STATUS					0x689c
-#define	D2CRTC_UPDATE_LOCK				0x68E8
-#define	D2GRPH_PRIMARY_SURFACE_ADDRESS			0x6910
-#define	D2GRPH_SECONDARY_SURFACE_ADDRESS		0x6918
-
-#define	D1VGA_CONTROL					0x0330
-#define		DVGA_CONTROL_MODE_ENABLE			(1 << 0)
-#define		DVGA_CONTROL_TIMING_SELECT			(1 << 8)
-#define		DVGA_CONTROL_SYNC_POLARITY_SELECT		(1 << 9)
-#define		DVGA_CONTROL_OVERSCAN_TIMING_SELECT		(1 << 10)
-#define		DVGA_CONTROL_OVERSCAN_COLOR_EN			(1 << 16)
-#define		DVGA_CONTROL_ROTATE				(1 << 24)
-#define D2VGA_CONTROL					0x0338
-
-#define	VGA_HDP_CONTROL					0x328
-#define		VGA_MEM_PAGE_SELECT_EN				(1 << 0)
-#define		VGA_MEMORY_DISABLE				(1 << 4)
-#define		VGA_RBBM_LOCK_DISABLE				(1 << 8)
-#define		VGA_SOFT_RESET					(1 << 16)
-#define	VGA_MEMORY_BASE_ADDRESS				0x0310
-#define	VGA_RENDER_CONTROL				0x0300
-#define		VGA_VSTATUS_CNTL_MASK				0x00030000
-
-#endif
diff --git a/hw/display/cayman_blit_shaders.h b/hw/display/cayman_blit_shaders.h
deleted file mode 100644
index f5d0e9a602..0000000000
--- a/hw/display/cayman_blit_shaders.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef CAYMAN_BLIT_SHADERS_H
-#define CAYMAN_BLIT_SHADERS_H
-
-extern const u32 cayman_ps[];
-extern const u32 cayman_vs[];
-extern const u32 cayman_default_state[];
-
-extern const u32 cayman_ps_size, cayman_vs_size;
-extern const u32 cayman_default_size;
-
-#endif
diff --git a/hw/display/ci_dpm.h b/hw/display/ci_dpm.h
deleted file mode 100644
index ac12db5f2c..0000000000
--- a/hw/display/ci_dpm.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/*
- * Copyright 2013 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __CI_DPM_H__
-#define __CI_DPM_H__
-
-#include "ppsmc.h"
-#include "radeon.h"
-
-#define SMU__NUM_SCLK_DPM_STATE  8
-#define SMU__NUM_MCLK_DPM_LEVELS 6
-#define SMU__NUM_LCLK_DPM_LEVELS 8
-#define SMU__NUM_PCIE_DPM_LEVELS 8
-#include "smu7_discrete.h"
-
-#define CISLANDS_MAX_HARDWARE_POWERLEVELS 2
-
-#define CISLANDS_UNUSED_GPIO_PIN 0x7F
-
-struct ci_pl {
-	u32 mclk;
-	u32 sclk;
-	enum radeon_pcie_gen pcie_gen;
-	u16 pcie_lane;
-};
-
-struct ci_ps {
-	u16 performance_level_count;
-	bool dc_compatible;
-	u32 sclk_t;
-	struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS];
-};
-
-struct ci_dpm_level {
-	bool enabled;
-	u32 value;
-	u32 param1;
-};
-
-#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
-#define MAX_REGULAR_DPM_NUMBER 8
-#define CISLAND_MINIMUM_ENGINE_CLOCK 800
-
-struct ci_single_dpm_table {
-	u32 count;
-	struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
-};
-
-struct ci_dpm_table {
-	struct ci_single_dpm_table sclk_table;
-	struct ci_single_dpm_table mclk_table;
-	struct ci_single_dpm_table pcie_speed_table;
-	struct ci_single_dpm_table vddc_table;
-	struct ci_single_dpm_table vddci_table;
-	struct ci_single_dpm_table mvdd_table;
-};
-
-struct ci_mc_reg_entry {
-	u32 mclk_max;
-	u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-};
-
-struct ci_mc_reg_table {
-	u8 last;
-	u8 num_entries;
-	u16 valid_flag;
-	struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
-	SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-};
-
-struct ci_ulv_parm
-{
-	bool supported;
-	u32 cg_ulv_parameter;
-	u32 volt_change_delay;
-	struct ci_pl pl;
-};
-
-#define CISLANDS_MAX_LEAKAGE_COUNT  8
-
-struct ci_leakage_voltage {
-	u16 count;
-	u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT];
-	u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT];
-};
-
-struct ci_dpm_level_enable_mask {
-	u32 uvd_dpm_enable_mask;
-	u32 vce_dpm_enable_mask;
-	u32 acp_dpm_enable_mask;
-	u32 samu_dpm_enable_mask;
-	u32 sclk_dpm_enable_mask;
-	u32 mclk_dpm_enable_mask;
-	u32 pcie_dpm_enable_mask;
-};
-
-struct ci_vbios_boot_state
-{
-	u16 mvdd_bootup_value;
-	u16 vddc_bootup_value;
-	u16 vddci_bootup_value;
-	u32 sclk_bootup_value;
-	u32 mclk_bootup_value;
-	u16 pcie_gen_bootup_value;
-	u16 pcie_lane_bootup_value;
-};
-
-struct ci_clock_registers {
-	u32 cg_spll_func_cntl;
-	u32 cg_spll_func_cntl_2;
-	u32 cg_spll_func_cntl_3;
-	u32 cg_spll_func_cntl_4;
-	u32 cg_spll_spread_spectrum;
-	u32 cg_spll_spread_spectrum_2;
-	u32 dll_cntl;
-	u32 mclk_pwrmgt_cntl;
-	u32 mpll_ad_func_cntl;
-	u32 mpll_dq_func_cntl;
-	u32 mpll_func_cntl;
-	u32 mpll_func_cntl_1;
-	u32 mpll_func_cntl_2;
-	u32 mpll_ss1;
-	u32 mpll_ss2;
-};
-
-struct ci_thermal_temperature_setting {
-	s32 temperature_low;
-	s32 temperature_high;
-	s32 temperature_shutdown;
-};
-
-struct ci_pcie_perf_range {
-	u16 max;
-	u16 min;
-};
-
-enum ci_pt_config_reg_type {
-	CISLANDS_CONFIGREG_MMR = 0,
-	CISLANDS_CONFIGREG_SMC_IND,
-	CISLANDS_CONFIGREG_DIDT_IND,
-	CISLANDS_CONFIGREG_CACHE,
-	CISLANDS_CONFIGREG_MAX
-};
-
-#define POWERCONTAINMENT_FEATURE_BAPM            0x00000001
-#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
-#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
-
-struct ci_pt_config_reg {
-	u32 offset;
-	u32 mask;
-	u32 shift;
-	u32 value;
-	enum ci_pt_config_reg_type type;
-};
-
-struct ci_pt_defaults {
-	u8 svi_load_line_en;
-	u8 svi_load_line_vddc;
-	u8 tdc_vddc_throttle_release_limit_perc;
-	u8 tdc_mawt;
-	u8 tdc_waterfall_ctl;
-	u8 dte_ambient_temp_base;
-	u32 display_cac;
-	u32 bapm_temp_gradient;
-	u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
-	u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
-};
-
-#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
-#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
-#define DPMTABLE_UPDATE_SCLK        0x00000004
-#define DPMTABLE_UPDATE_MCLK        0x00000008
-
-struct ci_power_info {
-	struct ci_dpm_table dpm_table;
-	u32 voltage_control;
-	u32 mvdd_control;
-	u32 vddci_control;
-	u32 active_auto_throttle_sources;
-	struct ci_clock_registers clock_registers;
-	u16 acpi_vddc;
-	u16 acpi_vddci;
-	enum radeon_pcie_gen force_pcie_gen;
-	enum radeon_pcie_gen acpi_pcie_gen;
-	struct ci_leakage_voltage vddc_leakage;
-	struct ci_leakage_voltage vddci_leakage;
-	u16 max_vddc_in_pp_table;
-	u16 min_vddc_in_pp_table;
-	u16 max_vddci_in_pp_table;
-	u16 min_vddci_in_pp_table;
-	u32 mclk_strobe_mode_threshold;
-	u32 mclk_stutter_mode_threshold;
-	u32 mclk_edc_enable_threshold;
-	u32 mclk_edc_wr_enable_threshold;
-	struct ci_vbios_boot_state vbios_boot_state;
-	/* smc offsets */
-	u32 sram_end;
-	u32 dpm_table_start;
-	u32 soft_regs_start;
-	u32 mc_reg_table_start;
-	u32 fan_table_start;
-	u32 arb_table_start;
-	/* smc tables */
-	SMU7_Discrete_DpmTable smc_state_table;
-	SMU7_Discrete_MCRegisters smc_mc_reg_table;
-	SMU7_Discrete_PmFuses smc_powertune_table;
-	/* other stuff */
-	struct ci_mc_reg_table mc_reg_table;
-	struct atom_voltage_table vddc_voltage_table;
-	struct atom_voltage_table vddci_voltage_table;
-	struct atom_voltage_table mvdd_voltage_table;
-	struct ci_ulv_parm ulv;
-	u32 power_containment_features;
-	const struct ci_pt_defaults *powertune_defaults;
-	u32 dte_tj_offset;
-	bool vddc_phase_shed_control;
-	struct ci_thermal_temperature_setting thermal_temp_setting;
-	struct ci_dpm_level_enable_mask dpm_level_enable_mask;
-	u32 need_update_smu7_dpm_table;
-	u32 sclk_dpm_key_disabled;
-	u32 mclk_dpm_key_disabled;
-	u32 pcie_dpm_key_disabled;
-	u32 thermal_sclk_dpm_enabled;
-	struct ci_pcie_perf_range pcie_gen_performance;
-	struct ci_pcie_perf_range pcie_lane_performance;
-	struct ci_pcie_perf_range pcie_gen_powersaving;
-	struct ci_pcie_perf_range pcie_lane_powersaving;
-	u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];
-	u32 mclk_activity_target;
-	u32 low_sclk_interrupt_t;
-	u32 last_mclk_dpm_enable_mask;
-	u32 sys_pcie_mask;
-	/* caps */
-	bool caps_power_containment;
-	bool caps_cac;
-	bool caps_sq_ramping;
-	bool caps_db_ramping;
-	bool caps_td_ramping;
-	bool caps_tcp_ramping;
-	bool caps_fps;
-	bool caps_sclk_ds;
-	bool caps_sclk_ss_support;
-	bool caps_mclk_ss_support;
-	bool caps_uvd_dpm;
-	bool caps_vce_dpm;
-	bool caps_samu_dpm;
-	bool caps_acp_dpm;
-	bool caps_automatic_dc_transition;
-	bool caps_sclk_throttle_low_notification;
-	bool caps_dynamic_ac_timing;
-	bool caps_od_fuzzy_fan_control_support;
-	/* flags */
-	bool thermal_protection;
-	bool pcie_performance_request;
-	bool dynamic_ss;
-	bool dll_default_on;
-	bool cac_enabled;
-	bool uvd_enabled;
-	bool battery_state;
-	bool pspp_notify_required;
-	bool mem_gddr5;
-	bool enable_bapm_feature;
-	bool enable_tdc_limit_feature;
-	bool enable_pkg_pwr_tracking_feature;
-	bool use_pcie_performance_levels;
-	bool use_pcie_powersaving_levels;
-	bool uvd_power_gated;
-	/* driver states */
-	struct radeon_ps current_rps;
-	struct ci_ps current_ps;
-	struct radeon_ps requested_rps;
-	struct ci_ps requested_ps;
-	/* fan control */
-	bool fan_ctrl_is_in_default_mode;
-	bool fan_is_controlled_by_smc;
-	u32 t_min;
-	u32 fan_ctrl_default_mode;
-};
-
-#define CISLANDS_VOLTAGE_CONTROL_NONE                   0x0
-#define CISLANDS_VOLTAGE_CONTROL_BY_GPIO                0x1
-#define CISLANDS_VOLTAGE_CONTROL_BY_SVID2               0x2
-
-#define CISLANDS_Q88_FORMAT_CONVERSION_UNIT             256
-
-#define CISLANDS_VRC_DFLT0                              0x3FFFC000
-#define CISLANDS_VRC_DFLT1                              0x000400
-#define CISLANDS_VRC_DFLT2                              0xC00080
-#define CISLANDS_VRC_DFLT3                              0xC00200
-#define CISLANDS_VRC_DFLT4                              0xC01680
-#define CISLANDS_VRC_DFLT5                              0xC00033
-#define CISLANDS_VRC_DFLT6                              0xC00033
-#define CISLANDS_VRC_DFLT7                              0x3FFFC000
-
-#define CISLANDS_CGULVPARAMETER_DFLT                    0x00040035
-#define CISLAND_TARGETACTIVITY_DFLT                     30
-#define CISLAND_MCLK_TARGETACTIVITY_DFLT                10
-
-#define PCIE_PERF_REQ_REMOVE_REGISTRY   0
-#define PCIE_PERF_REQ_FORCE_LOWPOWER    1
-#define PCIE_PERF_REQ_PECI_GEN1         2
-#define PCIE_PERF_REQ_PECI_GEN2         3
-#define PCIE_PERF_REQ_PECI_GEN3         4
-
-int ci_copy_bytes_to_smc(struct radeon_device *rdev,
-			 u32 smc_start_address,
-			 const u8 *src, u32 byte_count, u32 limit);
-void ci_start_smc(struct radeon_device *rdev);
-void ci_reset_smc(struct radeon_device *rdev);
-int ci_program_jump_on_start(struct radeon_device *rdev);
-void ci_stop_smc_clock(struct radeon_device *rdev);
-void ci_start_smc_clock(struct radeon_device *rdev);
-bool ci_is_smc_running(struct radeon_device *rdev);
-PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev);
-int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit);
-int ci_read_smc_sram_dword(struct radeon_device *rdev,
-			   u32 smc_address, u32 *value, u32 limit);
-int ci_write_smc_sram_dword(struct radeon_device *rdev,
-			    u32 smc_address, u32 value, u32 limit);
-
-#endif
diff --git a/hw/display/cik_blit_shaders.h b/hw/display/cik_blit_shaders.h
deleted file mode 100644
index dfe7314f9f..0000000000
--- a/hw/display/cik_blit_shaders.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2012 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef CIK_BLIT_SHADERS_H
-#define CIK_BLIT_SHADERS_H
-
-extern const u32 cik_default_state[];
-
-extern const u32 cik_default_size;
-
-#endif
diff --git a/hw/display/cikd.h b/hw/display/cikd.h
deleted file mode 100644
index cda16fcd43..0000000000
--- a/hw/display/cikd.h
+++ /dev/null
@@ -1,2172 +0,0 @@
-/*
- * Copyright 2012 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Alex Deucher
- */
-#ifndef CIK_H
-#define CIK_H
-
-#define BONAIRE_GB_ADDR_CONFIG_GOLDEN        0x12010001
-#define HAWAII_GB_ADDR_CONFIG_GOLDEN         0x12011003
-
-#define CIK_RB_BITMAP_WIDTH_PER_SH     2
-#define HAWAII_RB_BITMAP_WIDTH_PER_SH  4
-
-/* DIDT IND registers */
-#define DIDT_SQ_CTRL0                                     0x0
-#       define DIDT_CTRL_EN                               (1 << 0)
-#define DIDT_DB_CTRL0                                     0x20
-#define DIDT_TD_CTRL0                                     0x40
-#define DIDT_TCP_CTRL0                                    0x60
-
-/* SMC IND registers */
-#define DPM_TABLE_475                                     0x3F768
-#       define SamuBootLevel(x)                           ((x) << 0)
-#       define SamuBootLevel_MASK                         0x000000ff
-#       define SamuBootLevel_SHIFT                        0
-#       define AcpBootLevel(x)                            ((x) << 8)
-#       define AcpBootLevel_MASK                          0x0000ff00
-#       define AcpBootLevel_SHIFT                         8
-#       define VceBootLevel(x)                            ((x) << 16)
-#       define VceBootLevel_MASK                          0x00ff0000
-#       define VceBootLevel_SHIFT                         16
-#       define UvdBootLevel(x)                            ((x) << 24)
-#       define UvdBootLevel_MASK                          0xff000000
-#       define UvdBootLevel_SHIFT                         24
-
-#define FIRMWARE_FLAGS                                    0x3F800
-#       define INTERRUPTS_ENABLED                         (1 << 0)
-
-#define NB_DPM_CONFIG_1                                   0x3F9E8
-#       define Dpm0PgNbPsLo(x)                            ((x) << 0)
-#       define Dpm0PgNbPsLo_MASK                          0x000000ff
-#       define Dpm0PgNbPsLo_SHIFT                         0
-#       define Dpm0PgNbPsHi(x)                            ((x) << 8)
-#       define Dpm0PgNbPsHi_MASK                          0x0000ff00
-#       define Dpm0PgNbPsHi_SHIFT                         8
-#       define DpmXNbPsLo(x)                              ((x) << 16)
-#       define DpmXNbPsLo_MASK                            0x00ff0000
-#       define DpmXNbPsLo_SHIFT                           16
-#       define DpmXNbPsHi(x)                              ((x) << 24)
-#       define DpmXNbPsHi_MASK                            0xff000000
-#       define DpmXNbPsHi_SHIFT                           24
-
-#define	SMC_SYSCON_RESET_CNTL				0x80000000
-#       define RST_REG                                  (1 << 0)
-#define	SMC_SYSCON_CLOCK_CNTL_0				0x80000004
-#       define CK_DISABLE                               (1 << 0)
-#       define CKEN                                     (1 << 24)
-
-#define	SMC_SYSCON_MISC_CNTL				0x80000010
-
-#define SMC_SYSCON_MSG_ARG_0                              0x80000068
-
-#define SMC_PC_C                                          0x80000370
-
-#define SMC_SCRATCH9                                      0x80000424
-
-#define RCU_UC_EVENTS                                     0xC0000004
-#       define BOOT_SEQ_DONE                              (1 << 7)
-
-#define GENERAL_PWRMGT                                    0xC0200000
-#       define GLOBAL_PWRMGT_EN                           (1 << 0)
-#       define STATIC_PM_EN                               (1 << 1)
-#       define THERMAL_PROTECTION_DIS                     (1 << 2)
-#       define THERMAL_PROTECTION_TYPE                    (1 << 3)
-#       define SW_SMIO_INDEX(x)                           ((x) << 6)
-#       define SW_SMIO_INDEX_MASK                         (1 << 6)
-#       define SW_SMIO_INDEX_SHIFT                        6
-#       define VOLT_PWRMGT_EN                             (1 << 10)
-#       define GPU_COUNTER_CLK                            (1 << 15)
-#       define DYN_SPREAD_SPECTRUM_EN                     (1 << 23)
-
-#define CNB_PWRMGT_CNTL                                   0xC0200004
-#       define GNB_SLOW_MODE(x)                           ((x) << 0)
-#       define GNB_SLOW_MODE_MASK                         (3 << 0)
-#       define GNB_SLOW_MODE_SHIFT                        0
-#       define GNB_SLOW                                   (1 << 2)
-#       define FORCE_NB_PS1                               (1 << 3)
-#       define DPM_ENABLED                                (1 << 4)
-
-#define SCLK_PWRMGT_CNTL                                  0xC0200008
-#       define SCLK_PWRMGT_OFF                            (1 << 0)
-#       define RESET_BUSY_CNT                             (1 << 4)
-#       define RESET_SCLK_CNT                             (1 << 5)
-#       define DYNAMIC_PM_EN                              (1 << 21)
-
-#define TARGET_AND_CURRENT_PROFILE_INDEX                  0xC0200014
-#       define CURRENT_STATE_MASK                         (0xf << 4)
-#       define CURRENT_STATE_SHIFT                        4
-#       define CURR_MCLK_INDEX_MASK                       (0xf << 8)
-#       define CURR_MCLK_INDEX_SHIFT                      8
-#       define CURR_SCLK_INDEX_MASK                       (0x1f << 16)
-#       define CURR_SCLK_INDEX_SHIFT                      16
-
-#define CG_SSP                                            0xC0200044
-#       define SST(x)                                     ((x) << 0)
-#       define SST_MASK                                   (0xffff << 0)
-#       define SSTU(x)                                    ((x) << 16)
-#       define SSTU_MASK                                  (0xf << 16)
-
-#define CG_DISPLAY_GAP_CNTL                               0xC0200060
-#       define DISP_GAP(x)                                ((x) << 0)
-#       define DISP_GAP_MASK                              (3 << 0)
-#       define VBI_TIMER_COUNT(x)                         ((x) << 4)
-#       define VBI_TIMER_COUNT_MASK                       (0x3fff << 4)
-#       define VBI_TIMER_UNIT(x)                          ((x) << 20)
-#       define VBI_TIMER_UNIT_MASK                        (7 << 20)
-#       define DISP_GAP_MCHG(x)                           ((x) << 24)
-#       define DISP_GAP_MCHG_MASK                         (3 << 24)
-
-#define SMU_VOLTAGE_STATUS                                0xC0200094
-#       define SMU_VOLTAGE_CURRENT_LEVEL_MASK             (0xff << 1)
-#       define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT            1
-
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1                0xC02000F0
-#       define CURR_PCIE_INDEX_MASK                       (0xf << 24)
-#       define CURR_PCIE_INDEX_SHIFT                      24
-
-#define CG_ULV_PARAMETER                                  0xC0200158
-
-#define CG_FTV_0                                          0xC02001A8
-#define CG_FTV_1                                          0xC02001AC
-#define CG_FTV_2                                          0xC02001B0
-#define CG_FTV_3                                          0xC02001B4
-#define CG_FTV_4                                          0xC02001B8
-#define CG_FTV_5                                          0xC02001BC
-#define CG_FTV_6                                          0xC02001C0
-#define CG_FTV_7                                          0xC02001C4
-
-#define CG_DISPLAY_GAP_CNTL2                              0xC0200230
-
-#define LCAC_SX0_OVR_SEL                                  0xC0400D04
-#define LCAC_SX0_OVR_VAL                                  0xC0400D08
-
-#define LCAC_MC0_CNTL                                     0xC0400D30
-#define LCAC_MC0_OVR_SEL                                  0xC0400D34
-#define LCAC_MC0_OVR_VAL                                  0xC0400D38
-#define LCAC_MC1_CNTL                                     0xC0400D3C
-#define LCAC_MC1_OVR_SEL                                  0xC0400D40
-#define LCAC_MC1_OVR_VAL                                  0xC0400D44
-
-#define LCAC_MC2_OVR_SEL                                  0xC0400D4C
-#define LCAC_MC2_OVR_VAL                                  0xC0400D50
-
-#define LCAC_MC3_OVR_SEL                                  0xC0400D58
-#define LCAC_MC3_OVR_VAL                                  0xC0400D5C
-
-#define LCAC_CPL_CNTL                                     0xC0400D80
-#define LCAC_CPL_OVR_SEL                                  0xC0400D84
-#define LCAC_CPL_OVR_VAL                                  0xC0400D88
-
-/* dGPU */
-#define	CG_THERMAL_CTRL					0xC0300004
-#define 	DPM_EVENT_SRC(x)			((x) << 0)
-#define 	DPM_EVENT_SRC_MASK			(7 << 0)
-#define		DIG_THERM_DPM(x)			((x) << 14)
-#define		DIG_THERM_DPM_MASK			0x003FC000
-#define		DIG_THERM_DPM_SHIFT			14
-#define	CG_THERMAL_STATUS				0xC0300008
-#define		FDO_PWM_DUTY(x)				((x) << 9)
-#define		FDO_PWM_DUTY_MASK			(0xff << 9)
-#define		FDO_PWM_DUTY_SHIFT			9
-#define	CG_THERMAL_INT					0xC030000C
-#define		CI_DIG_THERM_INTH(x)			((x) << 8)
-#define		CI_DIG_THERM_INTH_MASK			0x0000FF00
-#define		CI_DIG_THERM_INTH_SHIFT			8
-#define		CI_DIG_THERM_INTL(x)			((x) << 16)
-#define		CI_DIG_THERM_INTL_MASK			0x00FF0000
-#define		CI_DIG_THERM_INTL_SHIFT			16
-#define 	THERM_INT_MASK_HIGH			(1 << 24)
-#define 	THERM_INT_MASK_LOW			(1 << 25)
-#define	CG_MULT_THERMAL_CTRL				0xC0300010
-#define		TEMP_SEL(x)				((x) << 20)
-#define		TEMP_SEL_MASK				(0xff << 20)
-#define		TEMP_SEL_SHIFT				20
-#define	CG_MULT_THERMAL_STATUS				0xC0300014
-#define		ASIC_MAX_TEMP(x)			((x) << 0)
-#define		ASIC_MAX_TEMP_MASK			0x000001ff
-#define		ASIC_MAX_TEMP_SHIFT			0
-#define		CTF_TEMP(x)				((x) << 9)
-#define		CTF_TEMP_MASK				0x0003fe00
-#define		CTF_TEMP_SHIFT				9
-
-#define	CG_FDO_CTRL0					0xC0300064
-#define		FDO_STATIC_DUTY(x)			((x) << 0)
-#define		FDO_STATIC_DUTY_MASK			0x000000FF
-#define		FDO_STATIC_DUTY_SHIFT			0
-#define	CG_FDO_CTRL1					0xC0300068
-#define		FMAX_DUTY100(x)				((x) << 0)
-#define		FMAX_DUTY100_MASK			0x000000FF
-#define		FMAX_DUTY100_SHIFT			0
-#define	CG_FDO_CTRL2					0xC030006C
-#define		TMIN(x)					((x) << 0)
-#define		TMIN_MASK				0x000000FF
-#define		TMIN_SHIFT				0
-#define		FDO_PWM_MODE(x)				((x) << 11)
-#define		FDO_PWM_MODE_MASK			(7 << 11)
-#define		FDO_PWM_MODE_SHIFT			11
-#define		TACH_PWM_RESP_RATE(x)			((x) << 25)
-#define		TACH_PWM_RESP_RATE_MASK			(0x7f << 25)
-#define		TACH_PWM_RESP_RATE_SHIFT		25
-#define CG_TACH_CTRL                                    0xC0300070
-#       define EDGE_PER_REV(x)                          ((x) << 0)
-#       define EDGE_PER_REV_MASK                        (0x7 << 0)
-#       define EDGE_PER_REV_SHIFT                       0
-#       define TARGET_PERIOD(x)                         ((x) << 3)
-#       define TARGET_PERIOD_MASK                       0xfffffff8
-#       define TARGET_PERIOD_SHIFT                      3
-#define CG_TACH_STATUS                                  0xC0300074
-#       define TACH_PERIOD(x)                           ((x) << 0)
-#       define TACH_PERIOD_MASK                         0xffffffff
-#       define TACH_PERIOD_SHIFT                        0
-
-#define CG_ECLK_CNTL                                    0xC05000AC
-#       define ECLK_DIVIDER_MASK                        0x7f
-#       define ECLK_DIR_CNTL_EN                         (1 << 8)
-#define CG_ECLK_STATUS                                  0xC05000B0
-#       define ECLK_STATUS                              (1 << 0)
-
-#define	CG_SPLL_FUNC_CNTL				0xC0500140
-#define		SPLL_RESET				(1 << 0)
-#define		SPLL_PWRON				(1 << 1)
-#define		SPLL_BYPASS_EN				(1 << 3)
-#define		SPLL_REF_DIV(x)				((x) << 5)
-#define		SPLL_REF_DIV_MASK			(0x3f << 5)
-#define		SPLL_PDIV_A(x)				((x) << 20)
-#define		SPLL_PDIV_A_MASK			(0x7f << 20)
-#define		SPLL_PDIV_A_SHIFT			20
-#define	CG_SPLL_FUNC_CNTL_2				0xC0500144
-#define		SCLK_MUX_SEL(x)				((x) << 0)
-#define		SCLK_MUX_SEL_MASK			(0x1ff << 0)
-#define	CG_SPLL_FUNC_CNTL_3				0xC0500148
-#define		SPLL_FB_DIV(x)				((x) << 0)
-#define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)
-#define		SPLL_FB_DIV_SHIFT			0
-#define		SPLL_DITHEN				(1 << 28)
-#define	CG_SPLL_FUNC_CNTL_4				0xC050014C
-
-#define	CG_SPLL_SPREAD_SPECTRUM				0xC0500164
-#define		SSEN					(1 << 0)
-#define		CLK_S(x)				((x) << 4)
-#define		CLK_S_MASK				(0xfff << 4)
-#define		CLK_S_SHIFT				4
-#define	CG_SPLL_SPREAD_SPECTRUM_2			0xC0500168
-#define		CLK_V(x)				((x) << 0)
-#define		CLK_V_MASK				(0x3ffffff << 0)
-#define		CLK_V_SHIFT				0
-
-#define	MPLL_BYPASSCLK_SEL				0xC050019C
-#	define MPLL_CLKOUT_SEL(x)			((x) << 8)
-#	define MPLL_CLKOUT_SEL_MASK			0xFF00
-#define CG_CLKPIN_CNTL                                    0xC05001A0
-#       define XTALIN_DIVIDE                              (1 << 1)
-#       define BCLK_AS_XCLK                               (1 << 2)
-#define CG_CLKPIN_CNTL_2                                  0xC05001A4
-#       define FORCE_BIF_REFCLK_EN                        (1 << 3)
-#       define MUX_TCLK_TO_XCLK                           (1 << 8)
-#define	THM_CLK_CNTL					0xC05001A8
-#	define CMON_CLK_SEL(x)				((x) << 0)
-#	define CMON_CLK_SEL_MASK			0xFF
-#	define TMON_CLK_SEL(x)				((x) << 8)
-#	define TMON_CLK_SEL_MASK			0xFF00
-#define	MISC_CLK_CTRL					0xC05001AC
-#	define DEEP_SLEEP_CLK_SEL(x)			((x) << 0)
-#	define DEEP_SLEEP_CLK_SEL_MASK			0xFF
-#	define ZCLK_SEL(x)				((x) << 8)
-#	define ZCLK_SEL_MASK				0xFF00
-
-/* KV/KB */
-#define	CG_THERMAL_INT_CTRL				0xC2100028
-#define		DIG_THERM_INTH(x)			((x) << 0)
-#define		DIG_THERM_INTH_MASK			0x000000FF
-#define		DIG_THERM_INTH_SHIFT			0
-#define		DIG_THERM_INTL(x)			((x) << 8)
-#define		DIG_THERM_INTL_MASK			0x0000FF00
-#define		DIG_THERM_INTL_SHIFT			8
-#define 	THERM_INTH_MASK				(1 << 24)
-#define 	THERM_INTL_MASK				(1 << 25)
-
-/* PCIE registers idx/data 0x38/0x3c */
-#define PB0_PIF_PWRDOWN_0                                 0x1100012 /* PCIE */
-#       define PLL_POWER_STATE_IN_TXS2_0(x)               ((x) << 7)
-#       define PLL_POWER_STATE_IN_TXS2_0_MASK             (0x7 << 7)
-#       define PLL_POWER_STATE_IN_TXS2_0_SHIFT            7
-#       define PLL_POWER_STATE_IN_OFF_0(x)                ((x) << 10)
-#       define PLL_POWER_STATE_IN_OFF_0_MASK              (0x7 << 10)
-#       define PLL_POWER_STATE_IN_OFF_0_SHIFT             10
-#       define PLL_RAMP_UP_TIME_0(x)                      ((x) << 24)
-#       define PLL_RAMP_UP_TIME_0_MASK                    (0x7 << 24)
-#       define PLL_RAMP_UP_TIME_0_SHIFT                   24
-#define PB0_PIF_PWRDOWN_1                                 0x1100013 /* PCIE */
-#       define PLL_POWER_STATE_IN_TXS2_1(x)               ((x) << 7)
-#       define PLL_POWER_STATE_IN_TXS2_1_MASK             (0x7 << 7)
-#       define PLL_POWER_STATE_IN_TXS2_1_SHIFT            7
-#       define PLL_POWER_STATE_IN_OFF_1(x)                ((x) << 10)
-#       define PLL_POWER_STATE_IN_OFF_1_MASK              (0x7 << 10)
-#       define PLL_POWER_STATE_IN_OFF_1_SHIFT             10
-#       define PLL_RAMP_UP_TIME_1(x)                      ((x) << 24)
-#       define PLL_RAMP_UP_TIME_1_MASK                    (0x7 << 24)
-#       define PLL_RAMP_UP_TIME_1_SHIFT                   24
-
-#define PCIE_CNTL2                                        0x1001001c /* PCIE */
-#       define SLV_MEM_LS_EN                              (1 << 16)
-#       define SLV_MEM_AGGRESSIVE_LS_EN                   (1 << 17)
-#       define MST_MEM_LS_EN                              (1 << 18)
-#       define REPLAY_MEM_LS_EN                           (1 << 19)
-
-#define PCIE_LC_STATUS1                                   0x1400028 /* PCIE */
-#       define LC_REVERSE_RCVR                            (1 << 0)
-#       define LC_REVERSE_XMIT                            (1 << 1)
-#       define LC_OPERATING_LINK_WIDTH_MASK               (0x7 << 2)
-#       define LC_OPERATING_LINK_WIDTH_SHIFT              2
-#       define LC_DETECTED_LINK_WIDTH_MASK                (0x7 << 5)
-#       define LC_DETECTED_LINK_WIDTH_SHIFT               5
-
-#define PCIE_P_CNTL                                       0x1400040 /* PCIE */
-#       define P_IGNORE_EDB_ERR                           (1 << 6)
-
-#define PB1_PIF_PWRDOWN_0                                 0x2100012 /* PCIE */
-#define PB1_PIF_PWRDOWN_1                                 0x2100013 /* PCIE */
-
-#define PCIE_LC_CNTL                                      0x100100A0 /* PCIE */
-#       define LC_L0S_INACTIVITY(x)                       ((x) << 8)
-#       define LC_L0S_INACTIVITY_MASK                     (0xf << 8)
-#       define LC_L0S_INACTIVITY_SHIFT                    8
-#       define LC_L1_INACTIVITY(x)                        ((x) << 12)
-#       define LC_L1_INACTIVITY_MASK                      (0xf << 12)
-#       define LC_L1_INACTIVITY_SHIFT                     12
-#       define LC_PMI_TO_L1_DIS                           (1 << 16)
-#       define LC_ASPM_TO_L1_DIS                          (1 << 24)
-
-#define PCIE_LC_LINK_WIDTH_CNTL                           0x100100A2 /* PCIE */
-#       define LC_LINK_WIDTH_SHIFT                        0
-#       define LC_LINK_WIDTH_MASK                         0x7
-#       define LC_LINK_WIDTH_X0                           0
-#       define LC_LINK_WIDTH_X1                           1
-#       define LC_LINK_WIDTH_X2                           2
-#       define LC_LINK_WIDTH_X4                           3
-#       define LC_LINK_WIDTH_X8                           4
-#       define LC_LINK_WIDTH_X16                          6
-#       define LC_LINK_WIDTH_RD_SHIFT                     4
-#       define LC_LINK_WIDTH_RD_MASK                      0x70
-#       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)
-#       define LC_RECONFIG_NOW                            (1 << 8)
-#       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)
-#       define LC_RENEGOTIATE_EN                          (1 << 10)
-#       define LC_SHORT_RECONFIG_EN                       (1 << 11)
-#       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)
-#       define LC_UPCONFIGURE_DIS                         (1 << 13)
-#       define LC_DYN_LANES_PWR_STATE(x)                  ((x) << 21)
-#       define LC_DYN_LANES_PWR_STATE_MASK                (0x3 << 21)
-#       define LC_DYN_LANES_PWR_STATE_SHIFT               21
-#define PCIE_LC_N_FTS_CNTL                                0x100100a3 /* PCIE */
-#       define LC_XMIT_N_FTS(x)                           ((x) << 0)
-#       define LC_XMIT_N_FTS_MASK                         (0xff << 0)
-#       define LC_XMIT_N_FTS_SHIFT                        0
-#       define LC_XMIT_N_FTS_OVERRIDE_EN                  (1 << 8)
-#       define LC_N_FTS_MASK                              (0xff << 24)
-#define PCIE_LC_SPEED_CNTL                                0x100100A4 /* PCIE */
-#       define LC_GEN2_EN_STRAP                           (1 << 0)
-#       define LC_GEN3_EN_STRAP                           (1 << 1)
-#       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 2)
-#       define LC_TARGET_LINK_SPEED_OVERRIDE_MASK         (0x3 << 3)
-#       define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT        3
-#       define LC_FORCE_EN_SW_SPEED_CHANGE                (1 << 5)
-#       define LC_FORCE_DIS_SW_SPEED_CHANGE               (1 << 6)
-#       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 7)
-#       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 8)
-#       define LC_INITIATE_LINK_SPEED_CHANGE              (1 << 9)
-#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 10)
-#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     10
-#       define LC_CURRENT_DATA_RATE_MASK                  (0x3 << 13) /* 0/1/2 = gen1/2/3 */
-#       define LC_CURRENT_DATA_RATE_SHIFT                 13
-#       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 16)
-#       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 18)
-#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 19)
-#       define LC_OTHER_SIDE_EVER_SENT_GEN3               (1 << 20)
-#       define LC_OTHER_SIDE_SUPPORTS_GEN3                (1 << 21)
-
-#define PCIE_LC_CNTL2                                     0x100100B1 /* PCIE */
-#       define LC_ALLOW_PDWN_IN_L1                        (1 << 17)
-#       define LC_ALLOW_PDWN_IN_L23                       (1 << 18)
-
-#define PCIE_LC_CNTL3                                     0x100100B5 /* PCIE */
-#       define LC_GO_TO_RECOVERY                          (1 << 30)
-#define PCIE_LC_CNTL4                                     0x100100B6 /* PCIE */
-#       define LC_REDO_EQ                                 (1 << 5)
-#       define LC_SET_QUIESCE                             (1 << 13)
-
-/* direct registers */
-#define PCIE_INDEX  					0x38
-#define PCIE_DATA  					0x3C
-
-#define SMC_IND_INDEX_0  				0x200
-#define SMC_IND_DATA_0  				0x204
-
-#define SMC_IND_ACCESS_CNTL  				0x240
-#define		AUTO_INCREMENT_IND_0			(1 << 0)
-
-#define SMC_MESSAGE_0  					0x250
-#define		SMC_MSG_MASK				0xffff
-#define SMC_RESP_0  					0x254
-#define		SMC_RESP_MASK				0xffff
-
-#define SMC_MSG_ARG_0  					0x290
-
-#define VGA_HDP_CONTROL  				0x328
-#define		VGA_MEMORY_DISABLE				(1 << 4)
-
-#define DMIF_ADDR_CALC  				0xC00
-
-#define	PIPE0_DMIF_BUFFER_CONTROL			  0x0ca0
-#       define DMIF_BUFFERS_ALLOCATED(x)                  ((x) << 0)
-#       define DMIF_BUFFERS_ALLOCATED_COMPLETED           (1 << 4)
-
-#define	SRBM_GFX_CNTL				        0xE44
-#define		PIPEID(x)					((x) << 0)
-#define		MEID(x)						((x) << 2)
-#define		VMID(x)						((x) << 4)
-#define		QUEUEID(x)					((x) << 8)
-
-#define	SRBM_STATUS2				        0xE4C
-#define		SDMA_BUSY 				(1 << 5)
-#define		SDMA1_BUSY 				(1 << 6)
-#define	SRBM_STATUS				        0xE50
-#define		UVD_RQ_PENDING 				(1 << 1)
-#define		GRBM_RQ_PENDING 			(1 << 5)
-#define		VMC_BUSY 				(1 << 8)
-#define		MCB_BUSY 				(1 << 9)
-#define		MCB_NON_DISPLAY_BUSY 			(1 << 10)
-#define		MCC_BUSY 				(1 << 11)
-#define		MCD_BUSY 				(1 << 12)
-#define		SEM_BUSY 				(1 << 14)
-#define		IH_BUSY 				(1 << 17)
-#define		UVD_BUSY 				(1 << 19)
-
-#define	SRBM_SOFT_RESET				        0xE60
-#define		SOFT_RESET_BIF				(1 << 1)
-#define		SOFT_RESET_R0PLL			(1 << 4)
-#define		SOFT_RESET_DC				(1 << 5)
-#define		SOFT_RESET_SDMA1			(1 << 6)
-#define		SOFT_RESET_GRBM				(1 << 8)
-#define		SOFT_RESET_HDP				(1 << 9)
-#define		SOFT_RESET_IH				(1 << 10)
-#define		SOFT_RESET_MC				(1 << 11)
-#define		SOFT_RESET_ROM				(1 << 14)
-#define		SOFT_RESET_SEM				(1 << 15)
-#define		SOFT_RESET_VMC				(1 << 17)
-#define		SOFT_RESET_SDMA				(1 << 20)
-#define		SOFT_RESET_TST				(1 << 21)
-#define		SOFT_RESET_REGBB		       	(1 << 22)
-#define		SOFT_RESET_ORB				(1 << 23)
-#define		SOFT_RESET_VCE				(1 << 24)
-
-#define SRBM_READ_ERROR					0xE98
-#define SRBM_INT_CNTL					0xEA0
-#define SRBM_INT_ACK					0xEA8
-
-#define VM_L2_CNTL					0x1400
-#define		ENABLE_L2_CACHE					(1 << 0)
-#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
-#define		L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)		((x) << 2)
-#define		L2_CACHE_PDE_ENDIAN_SWAP_MODE(x)		((x) << 4)
-#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)
-#define		ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE	(1 << 10)
-#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 15)
-#define		CONTEXT1_IDENTITY_ACCESS_MODE(x)		(((x) & 3) << 19)
-#define VM_L2_CNTL2					0x1404
-#define		INVALIDATE_ALL_L1_TLBS				(1 << 0)
-#define		INVALIDATE_L2_CACHE				(1 << 1)
-#define		INVALIDATE_CACHE_MODE(x)			((x) << 26)
-#define			INVALIDATE_PTE_AND_PDE_CACHES		0
-#define			INVALIDATE_ONLY_PTE_CACHES		1
-#define			INVALIDATE_ONLY_PDE_CACHES		2
-#define VM_L2_CNTL3					0x1408
-#define		BANK_SELECT(x)					((x) << 0)
-#define		L2_CACHE_UPDATE_MODE(x)				((x) << 6)
-#define		L2_CACHE_BIGK_FRAGMENT_SIZE(x)			((x) << 15)
-#define		L2_CACHE_BIGK_ASSOCIATIVITY			(1 << 20)
-#define	VM_L2_STATUS					0x140C
-#define		L2_BUSY						(1 << 0)
-#define VM_CONTEXT0_CNTL				0x1410
-#define		ENABLE_CONTEXT					(1 << 0)
-#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
-#define		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 3)
-#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
-#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT	(1 << 6)
-#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT	(1 << 7)
-#define		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 9)
-#define		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 10)
-#define		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 12)
-#define		VALID_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 13)
-#define		READ_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 15)
-#define		READ_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 16)
-#define		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 18)
-#define		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 19)
-#define		PAGE_TABLE_BLOCK_SIZE(x)			(((x) & 0xF) << 24)
-#define VM_CONTEXT1_CNTL				0x1414
-#define VM_CONTEXT0_CNTL2				0x1430
-#define VM_CONTEXT1_CNTL2				0x1434
-#define	VM_CONTEXT8_PAGE_TABLE_BASE_ADDR		0x1438
-#define	VM_CONTEXT9_PAGE_TABLE_BASE_ADDR		0x143c
-#define	VM_CONTEXT10_PAGE_TABLE_BASE_ADDR		0x1440
-#define	VM_CONTEXT11_PAGE_TABLE_BASE_ADDR		0x1444
-#define	VM_CONTEXT12_PAGE_TABLE_BASE_ADDR		0x1448
-#define	VM_CONTEXT13_PAGE_TABLE_BASE_ADDR		0x144c
-#define	VM_CONTEXT14_PAGE_TABLE_BASE_ADDR		0x1450
-#define	VM_CONTEXT15_PAGE_TABLE_BASE_ADDR		0x1454
-
-#define VM_INVALIDATE_REQUEST				0x1478
-#define VM_INVALIDATE_RESPONSE				0x147c
-
-#define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x14DC
-#define		PROTECTIONS_MASK			(0xf << 0)
-#define		PROTECTIONS_SHIFT			0
-		/* bit 0: range
-		 * bit 1: pde0
-		 * bit 2: valid
-		 * bit 3: read
-		 * bit 4: write
-		 */
-#define		MEMORY_CLIENT_ID_MASK			(0xff << 12)
-#define		HAWAII_MEMORY_CLIENT_ID_MASK		(0x1ff << 12)
-#define		MEMORY_CLIENT_ID_SHIFT			12
-#define		MEMORY_CLIENT_RW_MASK			(1 << 24)
-#define		MEMORY_CLIENT_RW_SHIFT			24
-#define		FAULT_VMID_MASK				(0xf << 25)
-#define		FAULT_VMID_SHIFT			25
-
-#define	VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT		0x14E4
-
-#define	VM_CONTEXT1_PROTECTION_FAULT_ADDR		0x14FC
-
-#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x1518
-#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR	0x151c
-
-#define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x153c
-#define	VM_CONTEXT1_PAGE_TABLE_BASE_ADDR		0x1540
-#define	VM_CONTEXT2_PAGE_TABLE_BASE_ADDR		0x1544
-#define	VM_CONTEXT3_PAGE_TABLE_BASE_ADDR		0x1548
-#define	VM_CONTEXT4_PAGE_TABLE_BASE_ADDR		0x154c
-#define	VM_CONTEXT5_PAGE_TABLE_BASE_ADDR		0x1550
-#define	VM_CONTEXT6_PAGE_TABLE_BASE_ADDR		0x1554
-#define	VM_CONTEXT7_PAGE_TABLE_BASE_ADDR		0x1558
-#define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x155c
-#define	VM_CONTEXT1_PAGE_TABLE_START_ADDR		0x1560
-
-#define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x157C
-#define	VM_CONTEXT1_PAGE_TABLE_END_ADDR			0x1580
-
-#define VM_L2_CG           				0x15c0
-#define		MC_CG_ENABLE				(1 << 18)
-#define		MC_LS_ENABLE				(1 << 19)
-
-#define MC_SHARED_CHMAP						0x2004
-#define		NOOFCHAN_SHIFT					12
-#define		NOOFCHAN_MASK					0x0000f000
-#define MC_SHARED_CHREMAP					0x2008
-
-#define CHUB_CONTROL					0x1864
-#define		BYPASS_VM					(1 << 0)
-
-#define	MC_VM_FB_LOCATION				0x2024
-#define	MC_VM_AGP_TOP					0x2028
-#define	MC_VM_AGP_BOT					0x202C
-#define	MC_VM_AGP_BASE					0x2030
-#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2034
-#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2038
-#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x203C
-
-#define	MC_VM_MX_L1_TLB_CNTL				0x2064
-#define		ENABLE_L1_TLB					(1 << 0)
-#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)
-#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)
-#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)
-#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)
-#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)
-#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)
-#define		ENABLE_ADVANCED_DRIVER_MODEL			(1 << 6)
-#define	MC_VM_FB_OFFSET					0x2068
-
-#define MC_SHARED_BLACKOUT_CNTL           		0x20ac
-
-#define MC_HUB_MISC_HUB_CG           			0x20b8
-#define MC_HUB_MISC_VM_CG           			0x20bc
-
-#define MC_HUB_MISC_SIP_CG           			0x20c0
-
-#define MC_XPB_CLK_GAT           			0x2478
-
-#define MC_CITF_MISC_RD_CG           			0x2648
-#define MC_CITF_MISC_WR_CG           			0x264c
-#define MC_CITF_MISC_VM_CG           			0x2650
-
-#define	MC_ARB_RAMCFG					0x2760
-#define		NOOFBANK_SHIFT					0
-#define		NOOFBANK_MASK					0x00000003
-#define		NOOFRANK_SHIFT					2
-#define		NOOFRANK_MASK					0x00000004
-#define		NOOFROWS_SHIFT					3
-#define		NOOFROWS_MASK					0x00000038
-#define		NOOFCOLS_SHIFT					6
-#define		NOOFCOLS_MASK					0x000000C0
-#define		CHANSIZE_SHIFT					8
-#define		CHANSIZE_MASK					0x00000100
-#define		NOOFGROUPS_SHIFT				12
-#define		NOOFGROUPS_MASK					0x00001000
-
-#define	MC_ARB_DRAM_TIMING				0x2774
-#define	MC_ARB_DRAM_TIMING2				0x2778
-
-#define MC_ARB_BURST_TIME                               0x2808
-#define		STATE0(x)				((x) << 0)
-#define		STATE0_MASK				(0x1f << 0)
-#define		STATE0_SHIFT				0
-#define		STATE1(x)				((x) << 5)
-#define		STATE1_MASK				(0x1f << 5)
-#define		STATE1_SHIFT				5
-#define		STATE2(x)				((x) << 10)
-#define		STATE2_MASK				(0x1f << 10)
-#define		STATE2_SHIFT				10
-#define		STATE3(x)				((x) << 15)
-#define		STATE3_MASK				(0x1f << 15)
-#define		STATE3_SHIFT				15
-
-#define MC_SEQ_RAS_TIMING                               0x28a0
-#define MC_SEQ_CAS_TIMING                               0x28a4
-#define MC_SEQ_MISC_TIMING                              0x28a8
-#define MC_SEQ_MISC_TIMING2                             0x28ac
-#define MC_SEQ_PMG_TIMING                               0x28b0
-#define MC_SEQ_RD_CTL_D0                                0x28b4
-#define MC_SEQ_RD_CTL_D1                                0x28b8
-#define MC_SEQ_WR_CTL_D0                                0x28bc
-#define MC_SEQ_WR_CTL_D1                                0x28c0
-
-#define MC_SEQ_SUP_CNTL           			0x28c8
-#define		RUN_MASK      				(1 << 0)
-#define MC_SEQ_SUP_PGM           			0x28cc
-#define MC_PMG_AUTO_CMD           			0x28d0
-
-#define	MC_SEQ_TRAIN_WAKEUP_CNTL			0x28e8
-#define		TRAIN_DONE_D0      			(1 << 30)
-#define		TRAIN_DONE_D1      			(1 << 31)
-
-#define MC_IO_PAD_CNTL_D0           			0x29d0
-#define		MEM_FALL_OUT_CMD      			(1 << 8)
-
-#define MC_SEQ_MISC0           				0x2a00
-#define 	MC_SEQ_MISC0_VEN_ID_SHIFT               8
-#define 	MC_SEQ_MISC0_VEN_ID_MASK                0x00000f00
-#define 	MC_SEQ_MISC0_VEN_ID_VALUE               3
-#define 	MC_SEQ_MISC0_REV_ID_SHIFT               12
-#define 	MC_SEQ_MISC0_REV_ID_MASK                0x0000f000
-#define 	MC_SEQ_MISC0_REV_ID_VALUE               1
-#define 	MC_SEQ_MISC0_GDDR5_SHIFT                28
-#define 	MC_SEQ_MISC0_GDDR5_MASK                 0xf0000000
-#define 	MC_SEQ_MISC0_GDDR5_VALUE                5
-#define MC_SEQ_MISC1                                    0x2a04
-#define MC_SEQ_RESERVE_M                                0x2a08
-#define MC_PMG_CMD_EMRS                                 0x2a0c
-
-#define MC_SEQ_IO_DEBUG_INDEX           		0x2a44
-#define MC_SEQ_IO_DEBUG_DATA           			0x2a48
-
-#define MC_SEQ_MISC5                                    0x2a54
-#define MC_SEQ_MISC6                                    0x2a58
-
-#define MC_SEQ_MISC7                                    0x2a64
-
-#define MC_SEQ_RAS_TIMING_LP                            0x2a6c
-#define MC_SEQ_CAS_TIMING_LP                            0x2a70
-#define MC_SEQ_MISC_TIMING_LP                           0x2a74
-#define MC_SEQ_MISC_TIMING2_LP                          0x2a78
-#define MC_SEQ_WR_CTL_D0_LP                             0x2a7c
-#define MC_SEQ_WR_CTL_D1_LP                             0x2a80
-#define MC_SEQ_PMG_CMD_EMRS_LP                          0x2a84
-#define MC_SEQ_PMG_CMD_MRS_LP                           0x2a88
-
-#define MC_PMG_CMD_MRS                                  0x2aac
-
-#define MC_SEQ_RD_CTL_D0_LP                             0x2b1c
-#define MC_SEQ_RD_CTL_D1_LP                             0x2b20
-
-#define MC_PMG_CMD_MRS1                                 0x2b44
-#define MC_SEQ_PMG_CMD_MRS1_LP                          0x2b48
-#define MC_SEQ_PMG_TIMING_LP                            0x2b4c
-
-#define MC_SEQ_WR_CTL_2                                 0x2b54
-#define MC_SEQ_WR_CTL_2_LP                              0x2b58
-#define MC_PMG_CMD_MRS2                                 0x2b5c
-#define MC_SEQ_PMG_CMD_MRS2_LP                          0x2b60
-
-#define	MCLK_PWRMGT_CNTL				0x2ba0
-#       define DLL_SPEED(x)				((x) << 0)
-#       define DLL_SPEED_MASK				(0x1f << 0)
-#       define DLL_READY                                (1 << 6)
-#       define MC_INT_CNTL                              (1 << 7)
-#       define MRDCK0_PDNB                              (1 << 8)
-#       define MRDCK1_PDNB                              (1 << 9)
-#       define MRDCK0_RESET                             (1 << 16)
-#       define MRDCK1_RESET                             (1 << 17)
-#       define DLL_READY_READ                           (1 << 24)
-#define	DLL_CNTL					0x2ba4
-#       define MRDCK0_BYPASS                            (1 << 24)
-#       define MRDCK1_BYPASS                            (1 << 25)
-
-#define	MPLL_FUNC_CNTL					0x2bb4
-#define		BWCTRL(x)				((x) << 20)
-#define		BWCTRL_MASK				(0xff << 20)
-#define	MPLL_FUNC_CNTL_1				0x2bb8
-#define		VCO_MODE(x)				((x) << 0)
-#define		VCO_MODE_MASK				(3 << 0)
-#define		CLKFRAC(x)				((x) << 4)
-#define		CLKFRAC_MASK				(0xfff << 4)
-#define		CLKF(x)					((x) << 16)
-#define		CLKF_MASK				(0xfff << 16)
-#define	MPLL_FUNC_CNTL_2				0x2bbc
-#define	MPLL_AD_FUNC_CNTL				0x2bc0
-#define		YCLK_POST_DIV(x)			((x) << 0)
-#define		YCLK_POST_DIV_MASK			(7 << 0)
-#define	MPLL_DQ_FUNC_CNTL				0x2bc4
-#define		YCLK_SEL(x)				((x) << 4)
-#define		YCLK_SEL_MASK				(1 << 4)
-
-#define	MPLL_SS1					0x2bcc
-#define		CLKV(x)					((x) << 0)
-#define		CLKV_MASK				(0x3ffffff << 0)
-#define	MPLL_SS2					0x2bd0
-#define		CLKS(x)					((x) << 0)
-#define		CLKS_MASK				(0xfff << 0)
-
-#define	HDP_HOST_PATH_CNTL				0x2C00
-#define 	CLOCK_GATING_DIS			(1 << 23)
-#define	HDP_NONSURFACE_BASE				0x2C04
-#define	HDP_NONSURFACE_INFO				0x2C08
-#define	HDP_NONSURFACE_SIZE				0x2C0C
-
-#define HDP_ADDR_CONFIG  				0x2F48
-#define HDP_MISC_CNTL					0x2F4C
-#define 	HDP_FLUSH_INVALIDATE_CACHE			(1 << 0)
-#define HDP_MEM_POWER_LS				0x2F50
-#define 	HDP_LS_ENABLE				(1 << 0)
-
-#define ATC_MISC_CG           				0x3350
-
-#define GMCON_RENG_EXECUTE				0x3508
-#define 	RENG_EXECUTE_ON_PWR_UP			(1 << 0)
-#define GMCON_MISC					0x350c
-#define 	RENG_EXECUTE_ON_REG_UPDATE		(1 << 11)
-#define 	STCTRL_STUTTER_EN			(1 << 16)
-
-#define GMCON_PGFSM_CONFIG				0x3538
-#define GMCON_PGFSM_WRITE				0x353c
-#define GMCON_PGFSM_READ				0x3540
-#define GMCON_MISC3					0x3544
-
-#define MC_SEQ_CNTL_3                                     0x3600
-#       define CAC_EN                                     (1 << 31)
-#define MC_SEQ_G5PDX_CTRL                                 0x3604
-#define MC_SEQ_G5PDX_CTRL_LP                              0x3608
-#define MC_SEQ_G5PDX_CMD0                                 0x360c
-#define MC_SEQ_G5PDX_CMD0_LP                              0x3610
-#define MC_SEQ_G5PDX_CMD1                                 0x3614
-#define MC_SEQ_G5PDX_CMD1_LP                              0x3618
-
-#define MC_SEQ_PMG_DVS_CTL                                0x3628
-#define MC_SEQ_PMG_DVS_CTL_LP                             0x362c
-#define MC_SEQ_PMG_DVS_CMD                                0x3630
-#define MC_SEQ_PMG_DVS_CMD_LP                             0x3634
-#define MC_SEQ_DLL_STBY                                   0x3638
-#define MC_SEQ_DLL_STBY_LP                                0x363c
-
-#define IH_RB_CNTL                                        0x3e00
-#       define IH_RB_ENABLE                               (1 << 0)
-#       define IH_RB_SIZE(x)                              ((x) << 1) /* log2 */
-#       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
-#       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
-#       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
-#       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
-#       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)
-#define IH_RB_BASE                                        0x3e04
-#define IH_RB_RPTR                                        0x3e08
-#define IH_RB_WPTR                                        0x3e0c
-#       define RB_OVERFLOW                                (1 << 0)
-#       define WPTR_OFFSET_MASK                           0x3fffc
-#define IH_RB_WPTR_ADDR_HI                                0x3e10
-#define IH_RB_WPTR_ADDR_LO                                0x3e14
-#define IH_CNTL                                           0x3e18
-#       define ENABLE_INTR                                (1 << 0)
-#       define IH_MC_SWAP(x)                              ((x) << 1)
-#       define IH_MC_SWAP_NONE                            0
-#       define IH_MC_SWAP_16BIT                           1
-#       define IH_MC_SWAP_32BIT                           2
-#       define IH_MC_SWAP_64BIT                           3
-#       define RPTR_REARM                                 (1 << 4)
-#       define MC_WRREQ_CREDIT(x)                         ((x) << 15)
-#       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)
-#       define MC_VMID(x)                                 ((x) << 25)
-
-#define	BIF_LNCNT_RESET					0x5220
-#       define RESET_LNCNT_EN                           (1 << 0)
-
-#define	CONFIG_MEMSIZE					0x5428
-
-#define INTERRUPT_CNTL                                    0x5468
-#       define IH_DUMMY_RD_OVERRIDE                       (1 << 0)
-#       define IH_DUMMY_RD_EN                             (1 << 1)
-#       define IH_REQ_NONSNOOP_EN                         (1 << 3)
-#       define GEN_IH_INT_EN                              (1 << 8)
-#define INTERRUPT_CNTL2                                   0x546c
-
-#define HDP_MEM_COHERENCY_FLUSH_CNTL			0x5480
-
-#define	BIF_FB_EN						0x5490
-#define		FB_READ_EN					(1 << 0)
-#define		FB_WRITE_EN					(1 << 1)
-
-#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0
-
-#define GPU_HDP_FLUSH_REQ				0x54DC
-#define GPU_HDP_FLUSH_DONE				0x54E0
-#define		CP0					(1 << 0)
-#define		CP1					(1 << 1)
-#define		CP2					(1 << 2)
-#define		CP3					(1 << 3)
-#define		CP4					(1 << 4)
-#define		CP5					(1 << 5)
-#define		CP6					(1 << 6)
-#define		CP7					(1 << 7)
-#define		CP8					(1 << 8)
-#define		CP9					(1 << 9)
-#define		SDMA0					(1 << 10)
-#define		SDMA1					(1 << 11)
-
-/* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */
-#define	LB_MEMORY_CTRL					0x6b04
-#define		LB_MEMORY_SIZE(x)			((x) << 0)
-#define		LB_MEMORY_CONFIG(x)			((x) << 20)
-
-#define	DPG_WATERMARK_MASK_CONTROL			0x6cc8
-#       define LATENCY_WATERMARK_MASK(x)		((x) << 8)
-#define	DPG_PIPE_LATENCY_CONTROL			0x6ccc
-#       define LATENCY_LOW_WATERMARK(x)			((x) << 0)
-#       define LATENCY_HIGH_WATERMARK(x)		((x) << 16)
-
-/* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */
-#define LB_VLINE_STATUS                                 0x6b24
-#       define VLINE_OCCURRED                           (1 << 0)
-#       define VLINE_ACK                                (1 << 4)
-#       define VLINE_STAT                               (1 << 12)
-#       define VLINE_INTERRUPT                          (1 << 16)
-#       define VLINE_INTERRUPT_TYPE                     (1 << 17)
-/* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */
-#define LB_VBLANK_STATUS                                0x6b2c
-#       define VBLANK_OCCURRED                          (1 << 0)
-#       define VBLANK_ACK                               (1 << 4)
-#       define VBLANK_STAT                              (1 << 12)
-#       define VBLANK_INTERRUPT                         (1 << 16)
-#       define VBLANK_INTERRUPT_TYPE                    (1 << 17)
-
-/* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */
-#define LB_INTERRUPT_MASK                               0x6b20
-#       define VBLANK_INTERRUPT_MASK                    (1 << 0)
-#       define VLINE_INTERRUPT_MASK                     (1 << 4)
-#       define VLINE2_INTERRUPT_MASK                    (1 << 8)
-
-#define DISP_INTERRUPT_STATUS                           0x60f4
-#       define LB_D1_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D1_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD1_INTERRUPT                        (1 << 17)
-#       define DC_HPD1_RX_INTERRUPT                     (1 << 18)
-#       define DACA_AUTODETECT_INTERRUPT                (1 << 22)
-#       define DACB_AUTODETECT_INTERRUPT                (1 << 23)
-#       define DC_I2C_SW_DONE_INTERRUPT                 (1 << 24)
-#       define DC_I2C_HW_DONE_INTERRUPT                 (1 << 25)
-#define DISP_INTERRUPT_STATUS_CONTINUE                  0x60f8
-#       define LB_D2_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D2_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD2_INTERRUPT                        (1 << 17)
-#       define DC_HPD2_RX_INTERRUPT                     (1 << 18)
-#       define DISP_TIMER_INTERRUPT                     (1 << 24)
-#define DISP_INTERRUPT_STATUS_CONTINUE2                 0x60fc
-#       define LB_D3_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D3_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD3_INTERRUPT                        (1 << 17)
-#       define DC_HPD3_RX_INTERRUPT                     (1 << 18)
-#define DISP_INTERRUPT_STATUS_CONTINUE3                 0x6100
-#       define LB_D4_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D4_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD4_INTERRUPT                        (1 << 17)
-#       define DC_HPD4_RX_INTERRUPT                     (1 << 18)
-#define DISP_INTERRUPT_STATUS_CONTINUE4                 0x614c
-#       define LB_D5_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD5_INTERRUPT                        (1 << 17)
-#       define DC_HPD5_RX_INTERRUPT                     (1 << 18)
-#define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6150
-#       define LB_D6_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD6_INTERRUPT                        (1 << 17)
-#       define DC_HPD6_RX_INTERRUPT                     (1 << 18)
-#define DISP_INTERRUPT_STATUS_CONTINUE6                 0x6780
-
-/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
-#define GRPH_INT_STATUS                                 0x6858
-#       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
-#       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
-/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
-#define GRPH_INT_CONTROL                                0x685c
-#       define GRPH_PFLIP_INT_MASK                      (1 << 0)
-#       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
-
-#define	DAC_AUTODETECT_INT_CONTROL			0x67c8
-
-#define DC_HPD1_INT_STATUS                              0x601c
-#define DC_HPD2_INT_STATUS                              0x6028
-#define DC_HPD3_INT_STATUS                              0x6034
-#define DC_HPD4_INT_STATUS                              0x6040
-#define DC_HPD5_INT_STATUS                              0x604c
-#define DC_HPD6_INT_STATUS                              0x6058
-#       define DC_HPDx_INT_STATUS                       (1 << 0)
-#       define DC_HPDx_SENSE                            (1 << 1)
-#       define DC_HPDx_SENSE_DELAYED                    (1 << 4)
-#       define DC_HPDx_RX_INT_STATUS                    (1 << 8)
-
-#define DC_HPD1_INT_CONTROL                             0x6020
-#define DC_HPD2_INT_CONTROL                             0x602c
-#define DC_HPD3_INT_CONTROL                             0x6038
-#define DC_HPD4_INT_CONTROL                             0x6044
-#define DC_HPD5_INT_CONTROL                             0x6050
-#define DC_HPD6_INT_CONTROL                             0x605c
-#       define DC_HPDx_INT_ACK                          (1 << 0)
-#       define DC_HPDx_INT_POLARITY                     (1 << 8)
-#       define DC_HPDx_INT_EN                           (1 << 16)
-#       define DC_HPDx_RX_INT_ACK                       (1 << 20)
-#       define DC_HPDx_RX_INT_EN                        (1 << 24)
-
-#define DC_HPD1_CONTROL                                   0x6024
-#define DC_HPD2_CONTROL                                   0x6030
-#define DC_HPD3_CONTROL                                   0x603c
-#define DC_HPD4_CONTROL                                   0x6048
-#define DC_HPD5_CONTROL                                   0x6054
-#define DC_HPD6_CONTROL                                   0x6060
-#       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)
-#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
-#       define DC_HPDx_EN                                 (1 << 28)
-
-#define DPG_PIPE_STUTTER_CONTROL                          0x6cd4
-#       define STUTTER_ENABLE                             (1 << 0)
-
-/* DCE8 FMT blocks */
-#define FMT_DYNAMIC_EXP_CNTL                 0x6fb4
-#       define FMT_DYNAMIC_EXP_EN            (1 << 0)
-#       define FMT_DYNAMIC_EXP_MODE          (1 << 4)
-        /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
-#define FMT_CONTROL                          0x6fb8
-#       define FMT_PIXEL_ENCODING            (1 << 16)
-        /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
-#define FMT_BIT_DEPTH_CONTROL                0x6fc8
-#       define FMT_TRUNCATE_EN               (1 << 0)
-#       define FMT_TRUNCATE_MODE             (1 << 1)
-#       define FMT_TRUNCATE_DEPTH(x)         ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
-#       define FMT_SPATIAL_DITHER_EN         (1 << 8)
-#       define FMT_SPATIAL_DITHER_MODE(x)    ((x) << 9)
-#       define FMT_SPATIAL_DITHER_DEPTH(x)   ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
-#       define FMT_FRAME_RANDOM_ENABLE       (1 << 13)
-#       define FMT_RGB_RANDOM_ENABLE         (1 << 14)
-#       define FMT_HIGHPASS_RANDOM_ENABLE    (1 << 15)
-#       define FMT_TEMPORAL_DITHER_EN        (1 << 16)
-#       define FMT_TEMPORAL_DITHER_DEPTH(x)  ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
-#       define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
-#       define FMT_TEMPORAL_LEVEL            (1 << 24)
-#       define FMT_TEMPORAL_DITHER_RESET     (1 << 25)
-#       define FMT_25FRC_SEL(x)              ((x) << 26)
-#       define FMT_50FRC_SEL(x)              ((x) << 28)
-#       define FMT_75FRC_SEL(x)              ((x) << 30)
-#define FMT_CLAMP_CONTROL                    0x6fe4
-#       define FMT_CLAMP_DATA_EN             (1 << 0)
-#       define FMT_CLAMP_COLOR_FORMAT(x)     ((x) << 16)
-#       define FMT_CLAMP_6BPC                0
-#       define FMT_CLAMP_8BPC                1
-#       define FMT_CLAMP_10BPC               2
-
-#define	GRBM_CNTL					0x8000
-#define		GRBM_READ_TIMEOUT(x)				((x) << 0)
-
-#define	GRBM_STATUS2					0x8008
-#define		ME0PIPE1_CMDFIFO_AVAIL_MASK			0x0000000F
-#define		ME0PIPE1_CF_RQ_PENDING				(1 << 4)
-#define		ME0PIPE1_PF_RQ_PENDING				(1 << 5)
-#define		ME1PIPE0_RQ_PENDING				(1 << 6)
-#define		ME1PIPE1_RQ_PENDING				(1 << 7)
-#define		ME1PIPE2_RQ_PENDING				(1 << 8)
-#define		ME1PIPE3_RQ_PENDING				(1 << 9)
-#define		ME2PIPE0_RQ_PENDING				(1 << 10)
-#define		ME2PIPE1_RQ_PENDING				(1 << 11)
-#define		ME2PIPE2_RQ_PENDING				(1 << 12)
-#define		ME2PIPE3_RQ_PENDING				(1 << 13)
-#define		RLC_RQ_PENDING 					(1 << 14)
-#define		RLC_BUSY 					(1 << 24)
-#define		TC_BUSY 					(1 << 25)
-#define		CPF_BUSY 					(1 << 28)
-#define		CPC_BUSY 					(1 << 29)
-#define		CPG_BUSY 					(1 << 30)
-
-#define	GRBM_STATUS					0x8010
-#define		ME0PIPE0_CMDFIFO_AVAIL_MASK			0x0000000F
-#define		SRBM_RQ_PENDING					(1 << 5)
-#define		ME0PIPE0_CF_RQ_PENDING				(1 << 7)
-#define		ME0PIPE0_PF_RQ_PENDING				(1 << 8)
-#define		GDS_DMA_RQ_PENDING				(1 << 9)
-#define		DB_CLEAN					(1 << 12)
-#define		CB_CLEAN					(1 << 13)
-#define		TA_BUSY 					(1 << 14)
-#define		GDS_BUSY 					(1 << 15)
-#define		WD_BUSY_NO_DMA 					(1 << 16)
-#define		VGT_BUSY					(1 << 17)
-#define		IA_BUSY_NO_DMA					(1 << 18)
-#define		IA_BUSY						(1 << 19)
-#define		SX_BUSY 					(1 << 20)
-#define		WD_BUSY 					(1 << 21)
-#define		SPI_BUSY					(1 << 22)
-#define		BCI_BUSY					(1 << 23)
-#define		SC_BUSY 					(1 << 24)
-#define		PA_BUSY 					(1 << 25)
-#define		DB_BUSY 					(1 << 26)
-#define		CP_COHERENCY_BUSY      				(1 << 28)
-#define		CP_BUSY 					(1 << 29)
-#define		CB_BUSY 					(1 << 30)
-#define		GUI_ACTIVE					(1 << 31)
-#define	GRBM_STATUS_SE0					0x8014
-#define	GRBM_STATUS_SE1					0x8018
-#define	GRBM_STATUS_SE2					0x8038
-#define	GRBM_STATUS_SE3					0x803C
-#define		SE_DB_CLEAN					(1 << 1)
-#define		SE_CB_CLEAN					(1 << 2)
-#define		SE_BCI_BUSY					(1 << 22)
-#define		SE_VGT_BUSY					(1 << 23)
-#define		SE_PA_BUSY					(1 << 24)
-#define		SE_TA_BUSY					(1 << 25)
-#define		SE_SX_BUSY					(1 << 26)
-#define		SE_SPI_BUSY					(1 << 27)
-#define		SE_SC_BUSY					(1 << 29)
-#define		SE_DB_BUSY					(1 << 30)
-#define		SE_CB_BUSY					(1 << 31)
-
-#define	GRBM_SOFT_RESET					0x8020
-#define		SOFT_RESET_CP					(1 << 0)  /* All CP blocks */
-#define		SOFT_RESET_RLC					(1 << 2)  /* RLC */
-#define		SOFT_RESET_GFX					(1 << 16) /* GFX */
-#define		SOFT_RESET_CPF					(1 << 17) /* CP fetcher shared by gfx and compute */
-#define		SOFT_RESET_CPC					(1 << 18) /* CP Compute (MEC1/2) */
-#define		SOFT_RESET_CPG					(1 << 19) /* CP GFX (PFP, ME, CE) */
-
-#define GRBM_INT_CNTL                                   0x8060
-#       define RDERR_INT_ENABLE                         (1 << 0)
-#       define GUI_IDLE_INT_ENABLE                      (1 << 19)
-
-#define CP_CPC_STATUS					0x8210
-#define CP_CPC_BUSY_STAT				0x8214
-#define CP_CPC_STALLED_STAT1				0x8218
-#define CP_CPF_STATUS					0x821c
-#define CP_CPF_BUSY_STAT				0x8220
-#define CP_CPF_STALLED_STAT1				0x8224
-
-#define CP_MEC_CNTL					0x8234
-#define		MEC_ME2_HALT					(1 << 28)
-#define		MEC_ME1_HALT					(1 << 30)
-
-#define CP_MEC_CNTL					0x8234
-#define		MEC_ME2_HALT					(1 << 28)
-#define		MEC_ME1_HALT					(1 << 30)
-
-#define CP_STALLED_STAT3				0x8670
-#define CP_STALLED_STAT1				0x8674
-#define CP_STALLED_STAT2				0x8678
-
-#define CP_STAT						0x8680
-
-#define CP_ME_CNTL					0x86D8
-#define		CP_CE_HALT					(1 << 24)
-#define		CP_PFP_HALT					(1 << 26)
-#define		CP_ME_HALT					(1 << 28)
-
-#define	CP_RB0_RPTR					0x8700
-#define	CP_RB_WPTR_DELAY				0x8704
-#define	CP_RB_WPTR_POLL_CNTL				0x8708
-#define		IDLE_POLL_COUNT(x)			((x) << 16)
-#define		IDLE_POLL_COUNT_MASK			(0xffff << 16)
-
-#define CP_MEQ_THRESHOLDS				0x8764
-#define		MEQ1_START(x)				((x) << 0)
-#define		MEQ2_START(x)				((x) << 8)
-
-#define	VGT_VTX_VECT_EJECT_REG				0x88B0
-
-#define	VGT_CACHE_INVALIDATION				0x88C4
-#define		CACHE_INVALIDATION(x)				((x) << 0)
-#define			VC_ONLY						0
-#define			TC_ONLY						1
-#define			VC_AND_TC					2
-#define		AUTO_INVLD_EN(x)				((x) << 6)
-#define			NO_AUTO						0
-#define			ES_AUTO						1
-#define			GS_AUTO						2
-#define			ES_AND_GS_AUTO					3
-
-#define	VGT_GS_VERTEX_REUSE				0x88D4
-
-#define CC_GC_SHADER_ARRAY_CONFIG			0x89bc
-#define		INACTIVE_CUS_MASK			0xFFFF0000
-#define		INACTIVE_CUS_SHIFT			16
-#define GC_USER_SHADER_ARRAY_CONFIG			0x89c0
-
-#define	PA_CL_ENHANCE					0x8A14
-#define		CLIP_VTX_REORDER_ENA				(1 << 0)
-#define		NUM_CLIP_SEQ(x)					((x) << 1)
-
-#define	PA_SC_FORCE_EOV_MAX_CNTS			0x8B24
-#define		FORCE_EOV_MAX_CLK_CNT(x)			((x) << 0)
-#define		FORCE_EOV_MAX_REZ_CNT(x)			((x) << 16)
-
-#define	PA_SC_FIFO_SIZE					0x8BCC
-#define		SC_FRONTEND_PRIM_FIFO_SIZE(x)			((x) << 0)
-#define		SC_BACKEND_PRIM_FIFO_SIZE(x)			((x) << 6)
-#define		SC_HIZ_TILE_FIFO_SIZE(x)			((x) << 15)
-#define		SC_EARLYZ_TILE_FIFO_SIZE(x)			((x) << 23)
-
-#define	PA_SC_ENHANCE					0x8BF0
-#define		ENABLE_PA_SC_OUT_OF_ORDER			(1 << 0)
-#define		DISABLE_PA_SC_GUIDANCE				(1 << 13)
-
-#define	SQ_CONFIG					0x8C00
-
-#define	SH_MEM_BASES					0x8C28
-/* if PTR32, these are the bases for scratch and lds */
-#define		PRIVATE_BASE(x)					((x) << 0) /* scratch */
-#define		SHARED_BASE(x)					((x) << 16) /* LDS */
-#define	SH_MEM_APE1_BASE				0x8C2C
-/* if PTR32, this is the base location of GPUVM */
-#define	SH_MEM_APE1_LIMIT				0x8C30
-/* if PTR32, this is the upper limit of GPUVM */
-#define	SH_MEM_CONFIG					0x8C34
-#define		PTR32						(1 << 0)
-#define		ALIGNMENT_MODE(x)				((x) << 2)
-#define			SH_MEM_ALIGNMENT_MODE_DWORD			0
-#define			SH_MEM_ALIGNMENT_MODE_DWORD_STRICT		1
-#define			SH_MEM_ALIGNMENT_MODE_STRICT			2
-#define			SH_MEM_ALIGNMENT_MODE_UNALIGNED			3
-#define		DEFAULT_MTYPE(x)				((x) << 4)
-#define		APE1_MTYPE(x)					((x) << 7)
-/* valid for both DEFAULT_MTYPE and APE1_MTYPE */
-#define	MTYPE_CACHED					0
-#define	MTYPE_NONCACHED					3
-
-#define	SX_DEBUG_1					0x9060
-
-#define	SPI_CONFIG_CNTL					0x9100
-
-#define	SPI_CONFIG_CNTL_1				0x913C
-#define		VTX_DONE_DELAY(x)				((x) << 0)
-#define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)
-
-#define	TA_CNTL_AUX					0x9508
-
-#define DB_DEBUG					0x9830
-#define DB_DEBUG2					0x9834
-#define DB_DEBUG3					0x9838
-
-#define CC_RB_BACKEND_DISABLE				0x98F4
-#define		BACKEND_DISABLE(x)     			((x) << 16)
-#define GB_ADDR_CONFIG  				0x98F8
-#define		NUM_PIPES(x)				((x) << 0)
-#define		NUM_PIPES_MASK				0x00000007
-#define		NUM_PIPES_SHIFT				0
-#define		PIPE_INTERLEAVE_SIZE(x)			((x) << 4)
-#define		PIPE_INTERLEAVE_SIZE_MASK		0x00000070
-#define		PIPE_INTERLEAVE_SIZE_SHIFT		4
-#define		NUM_SHADER_ENGINES(x)			((x) << 12)
-#define		NUM_SHADER_ENGINES_MASK			0x00003000
-#define		NUM_SHADER_ENGINES_SHIFT		12
-#define		SHADER_ENGINE_TILE_SIZE(x)     		((x) << 16)
-#define		SHADER_ENGINE_TILE_SIZE_MASK		0x00070000
-#define		SHADER_ENGINE_TILE_SIZE_SHIFT		16
-#define		ROW_SIZE(x)             		((x) << 28)
-#define		ROW_SIZE_MASK				0x30000000
-#define		ROW_SIZE_SHIFT				28
-
-#define	GB_TILE_MODE0					0x9910
-#       define ARRAY_MODE(x)					((x) << 2)
-#              define	ARRAY_LINEAR_GENERAL			0
-#              define	ARRAY_LINEAR_ALIGNED			1
-#              define	ARRAY_1D_TILED_THIN1			2
-#              define	ARRAY_2D_TILED_THIN1			4
-#              define	ARRAY_PRT_TILED_THIN1			5
-#              define	ARRAY_PRT_2D_TILED_THIN1		6
-#       define PIPE_CONFIG(x)					((x) << 6)
-#              define	ADDR_SURF_P2				0
-#              define	ADDR_SURF_P4_8x16			4
-#              define	ADDR_SURF_P4_16x16			5
-#              define	ADDR_SURF_P4_16x32			6
-#              define	ADDR_SURF_P4_32x32			7
-#              define	ADDR_SURF_P8_16x16_8x16			8
-#              define	ADDR_SURF_P8_16x32_8x16			9
-#              define	ADDR_SURF_P8_32x32_8x16			10
-#              define	ADDR_SURF_P8_16x32_16x16		11
-#              define	ADDR_SURF_P8_32x32_16x16		12
-#              define	ADDR_SURF_P8_32x32_16x32		13
-#              define	ADDR_SURF_P8_32x64_32x32		14
-#              define	ADDR_SURF_P16_32x32_8x16		16
-#              define	ADDR_SURF_P16_32x32_16x16		17
-#       define TILE_SPLIT(x)					((x) << 11)
-#              define	ADDR_SURF_TILE_SPLIT_64B		0
-#              define	ADDR_SURF_TILE_SPLIT_128B		1
-#              define	ADDR_SURF_TILE_SPLIT_256B		2
-#              define	ADDR_SURF_TILE_SPLIT_512B		3
-#              define	ADDR_SURF_TILE_SPLIT_1KB		4
-#              define	ADDR_SURF_TILE_SPLIT_2KB		5
-#              define	ADDR_SURF_TILE_SPLIT_4KB		6
-#       define MICRO_TILE_MODE_NEW(x)				((x) << 22)
-#              define	ADDR_SURF_DISPLAY_MICRO_TILING		0
-#              define	ADDR_SURF_THIN_MICRO_TILING		1
-#              define	ADDR_SURF_DEPTH_MICRO_TILING		2
-#              define	ADDR_SURF_ROTATED_MICRO_TILING		3
-#       define SAMPLE_SPLIT(x)					((x) << 25)
-#              define	ADDR_SURF_SAMPLE_SPLIT_1		0
-#              define	ADDR_SURF_SAMPLE_SPLIT_2		1
-#              define	ADDR_SURF_SAMPLE_SPLIT_4		2
-#              define	ADDR_SURF_SAMPLE_SPLIT_8		3
-
-#define	GB_MACROTILE_MODE0					0x9990
-#       define BANK_WIDTH(x)					((x) << 0)
-#              define	ADDR_SURF_BANK_WIDTH_1			0
-#              define	ADDR_SURF_BANK_WIDTH_2			1
-#              define	ADDR_SURF_BANK_WIDTH_4			2
-#              define	ADDR_SURF_BANK_WIDTH_8			3
-#       define BANK_HEIGHT(x)					((x) << 2)
-#              define	ADDR_SURF_BANK_HEIGHT_1			0
-#              define	ADDR_SURF_BANK_HEIGHT_2			1
-#              define	ADDR_SURF_BANK_HEIGHT_4			2
-#              define	ADDR_SURF_BANK_HEIGHT_8			3
-#       define MACRO_TILE_ASPECT(x)				((x) << 4)
-#              define	ADDR_SURF_MACRO_ASPECT_1		0
-#              define	ADDR_SURF_MACRO_ASPECT_2		1
-#              define	ADDR_SURF_MACRO_ASPECT_4		2
-#              define	ADDR_SURF_MACRO_ASPECT_8		3
-#       define NUM_BANKS(x)					((x) << 6)
-#              define	ADDR_SURF_2_BANK			0
-#              define	ADDR_SURF_4_BANK			1
-#              define	ADDR_SURF_8_BANK			2
-#              define	ADDR_SURF_16_BANK			3
-
-#define	CB_HW_CONTROL					0x9A10
-
-#define	GC_USER_RB_BACKEND_DISABLE			0x9B7C
-#define		BACKEND_DISABLE_MASK			0x00FF0000
-#define		BACKEND_DISABLE_SHIFT			16
-
-#define	TCP_CHAN_STEER_LO				0xac0c
-#define	TCP_CHAN_STEER_HI				0xac10
-
-#define	TC_CFG_L1_LOAD_POLICY0				0xAC68
-#define	TC_CFG_L1_LOAD_POLICY1				0xAC6C
-#define	TC_CFG_L1_STORE_POLICY				0xAC70
-#define	TC_CFG_L2_LOAD_POLICY0				0xAC74
-#define	TC_CFG_L2_LOAD_POLICY1				0xAC78
-#define	TC_CFG_L2_STORE_POLICY0				0xAC7C
-#define	TC_CFG_L2_STORE_POLICY1				0xAC80
-#define	TC_CFG_L2_ATOMIC_POLICY				0xAC84
-#define	TC_CFG_L1_VOLATILE				0xAC88
-#define	TC_CFG_L2_VOLATILE				0xAC8C
-
-#define	CP_RB0_BASE					0xC100
-#define	CP_RB0_CNTL					0xC104
-#define		RB_BUFSZ(x)					((x) << 0)
-#define		RB_BLKSZ(x)					((x) << 8)
-#define		BUF_SWAP_32BIT					(2 << 16)
-#define		RB_NO_UPDATE					(1 << 27)
-#define		RB_RPTR_WR_ENA					(1 << 31)
-
-#define	CP_RB0_RPTR_ADDR				0xC10C
-#define		RB_RPTR_SWAP_32BIT				(2 << 0)
-#define	CP_RB0_RPTR_ADDR_HI				0xC110
-#define	CP_RB0_WPTR					0xC114
-
-#define	CP_DEVICE_ID					0xC12C
-#define	CP_ENDIAN_SWAP					0xC140
-#define	CP_RB_VMID					0xC144
-
-#define	CP_PFP_UCODE_ADDR				0xC150
-#define	CP_PFP_UCODE_DATA				0xC154
-#define	CP_ME_RAM_RADDR					0xC158
-#define	CP_ME_RAM_WADDR					0xC15C
-#define	CP_ME_RAM_DATA					0xC160
-
-#define	CP_CE_UCODE_ADDR				0xC168
-#define	CP_CE_UCODE_DATA				0xC16C
-#define	CP_MEC_ME1_UCODE_ADDR				0xC170
-#define	CP_MEC_ME1_UCODE_DATA				0xC174
-#define	CP_MEC_ME2_UCODE_ADDR				0xC178
-#define	CP_MEC_ME2_UCODE_DATA				0xC17C
-
-#define CP_INT_CNTL_RING0                               0xC1A8
-#       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
-#       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
-#       define PRIV_INSTR_INT_ENABLE                    (1 << 22)
-#       define PRIV_REG_INT_ENABLE                      (1 << 23)
-#       define OPCODE_ERROR_INT_ENABLE                  (1 << 24)
-#       define TIME_STAMP_INT_ENABLE                    (1 << 26)
-#       define CP_RINGID2_INT_ENABLE                    (1 << 29)
-#       define CP_RINGID1_INT_ENABLE                    (1 << 30)
-#       define CP_RINGID0_INT_ENABLE                    (1 << 31)
-
-#define CP_INT_STATUS_RING0                             0xC1B4
-#       define PRIV_INSTR_INT_STAT                      (1 << 22)
-#       define PRIV_REG_INT_STAT                        (1 << 23)
-#       define TIME_STAMP_INT_STAT                      (1 << 26)
-#       define CP_RINGID2_INT_STAT                      (1 << 29)
-#       define CP_RINGID1_INT_STAT                      (1 << 30)
-#       define CP_RINGID0_INT_STAT                      (1 << 31)
-
-#define CP_MEM_SLP_CNTL                                 0xC1E4
-#       define CP_MEM_LS_EN                             (1 << 0)
-
-#define CP_CPF_DEBUG                                    0xC200
-
-#define CP_PQ_WPTR_POLL_CNTL                            0xC20C
-#define		WPTR_POLL_EN      			(1 << 31)
-
-#define CP_ME1_PIPE0_INT_CNTL                           0xC214
-#define CP_ME1_PIPE1_INT_CNTL                           0xC218
-#define CP_ME1_PIPE2_INT_CNTL                           0xC21C
-#define CP_ME1_PIPE3_INT_CNTL                           0xC220
-#define CP_ME2_PIPE0_INT_CNTL                           0xC224
-#define CP_ME2_PIPE1_INT_CNTL                           0xC228
-#define CP_ME2_PIPE2_INT_CNTL                           0xC22C
-#define CP_ME2_PIPE3_INT_CNTL                           0xC230
-#       define DEQUEUE_REQUEST_INT_ENABLE               (1 << 13)
-#       define WRM_POLL_TIMEOUT_INT_ENABLE              (1 << 17)
-#       define PRIV_REG_INT_ENABLE                      (1 << 23)
-#       define TIME_STAMP_INT_ENABLE                    (1 << 26)
-#       define GENERIC2_INT_ENABLE                      (1 << 29)
-#       define GENERIC1_INT_ENABLE                      (1 << 30)
-#       define GENERIC0_INT_ENABLE                      (1 << 31)
-#define CP_ME1_PIPE0_INT_STATUS                         0xC214
-#define CP_ME1_PIPE1_INT_STATUS                         0xC218
-#define CP_ME1_PIPE2_INT_STATUS                         0xC21C
-#define CP_ME1_PIPE3_INT_STATUS                         0xC220
-#define CP_ME2_PIPE0_INT_STATUS                         0xC224
-#define CP_ME2_PIPE1_INT_STATUS                         0xC228
-#define CP_ME2_PIPE2_INT_STATUS                         0xC22C
-#define CP_ME2_PIPE3_INT_STATUS                         0xC230
-#       define DEQUEUE_REQUEST_INT_STATUS               (1 << 13)
-#       define WRM_POLL_TIMEOUT_INT_STATUS              (1 << 17)
-#       define PRIV_REG_INT_STATUS                      (1 << 23)
-#       define TIME_STAMP_INT_STATUS                    (1 << 26)
-#       define GENERIC2_INT_STATUS                      (1 << 29)
-#       define GENERIC1_INT_STATUS                      (1 << 30)
-#       define GENERIC0_INT_STATUS                      (1 << 31)
-
-#define	CP_MAX_CONTEXT					0xC2B8
-
-#define	CP_RB0_BASE_HI					0xC2C4
-
-#define RLC_CNTL                                          0xC300
-#       define RLC_ENABLE                                 (1 << 0)
-
-#define RLC_MC_CNTL                                       0xC30C
-
-#define RLC_MEM_SLP_CNTL                                  0xC318
-#       define RLC_MEM_LS_EN                              (1 << 0)
-
-#define RLC_LB_CNTR_MAX                                   0xC348
-
-#define RLC_LB_CNTL                                       0xC364
-#       define LOAD_BALANCE_ENABLE                        (1 << 0)
-
-#define RLC_LB_CNTR_INIT                                  0xC36C
-
-#define RLC_SAVE_AND_RESTORE_BASE                         0xC374
-#define RLC_DRIVER_DMA_STATUS                             0xC378 /* dGPU */
-#define RLC_CP_TABLE_RESTORE                              0xC378 /* APU */
-#define RLC_PG_DELAY_2                                    0xC37C
-
-#define RLC_GPM_UCODE_ADDR                                0xC388
-#define RLC_GPM_UCODE_DATA                                0xC38C
-#define RLC_GPU_CLOCK_COUNT_LSB                           0xC390
-#define RLC_GPU_CLOCK_COUNT_MSB                           0xC394
-#define RLC_CAPTURE_GPU_CLOCK_COUNT                       0xC398
-#define RLC_UCODE_CNTL                                    0xC39C
-
-#define RLC_GPM_STAT                                      0xC400
-#       define RLC_GPM_BUSY                               (1 << 0)
-#       define GFX_POWER_STATUS                           (1 << 1)
-#       define GFX_CLOCK_STATUS                           (1 << 2)
-
-#define RLC_PG_CNTL                                       0xC40C
-#       define GFX_PG_ENABLE                              (1 << 0)
-#       define GFX_PG_SRC                                 (1 << 1)
-#       define DYN_PER_CU_PG_ENABLE                       (1 << 2)
-#       define STATIC_PER_CU_PG_ENABLE                    (1 << 3)
-#       define DISABLE_GDS_PG                             (1 << 13)
-#       define DISABLE_CP_PG                              (1 << 15)
-#       define SMU_CLK_SLOWDOWN_ON_PU_ENABLE              (1 << 17)
-#       define SMU_CLK_SLOWDOWN_ON_PD_ENABLE              (1 << 18)
-
-#define RLC_CGTT_MGCG_OVERRIDE                            0xC420
-#define RLC_CGCG_CGLS_CTRL                                0xC424
-#       define CGCG_EN                                    (1 << 0)
-#       define CGLS_EN                                    (1 << 1)
-
-#define RLC_PG_DELAY                                      0xC434
-
-#define RLC_LB_INIT_CU_MASK                               0xC43C
-
-#define RLC_LB_PARAMS                                     0xC444
-
-#define RLC_PG_AO_CU_MASK                                 0xC44C
-
-#define	RLC_MAX_PG_CU					0xC450
-#	define MAX_PU_CU(x)				((x) << 0)
-#	define MAX_PU_CU_MASK				(0xff << 0)
-#define RLC_AUTO_PG_CTRL                                  0xC454
-#       define AUTO_PG_EN                                 (1 << 0)
-#	define GRBM_REG_SGIT(x)				((x) << 3)
-#	define GRBM_REG_SGIT_MASK			(0xffff << 3)
-
-#define RLC_SERDES_WR_CU_MASTER_MASK                      0xC474
-#define RLC_SERDES_WR_NONCU_MASTER_MASK                   0xC478
-#define RLC_SERDES_WR_CTRL                                0xC47C
-#define		BPM_ADDR(x)				((x) << 0)
-#define		BPM_ADDR_MASK      			(0xff << 0)
-#define		CGLS_ENABLE				(1 << 16)
-#define		CGCG_OVERRIDE_0				(1 << 20)
-#define		MGCG_OVERRIDE_0				(1 << 22)
-#define		MGCG_OVERRIDE_1				(1 << 23)
-
-#define RLC_SERDES_CU_MASTER_BUSY                         0xC484
-#define RLC_SERDES_NONCU_MASTER_BUSY                      0xC488
-#       define SE_MASTER_BUSY_MASK                        0x0000ffff
-#       define GC_MASTER_BUSY                             (1 << 16)
-#       define TC0_MASTER_BUSY                            (1 << 17)
-#       define TC1_MASTER_BUSY                            (1 << 18)
-
-#define RLC_GPM_SCRATCH_ADDR                              0xC4B0
-#define RLC_GPM_SCRATCH_DATA                              0xC4B4
-
-#define RLC_GPR_REG2                                      0xC4E8
-#define		REQ      				0x00000001
-#define		MESSAGE(x)      			((x) << 1)
-#define		MESSAGE_MASK      			0x0000001e
-#define		MSG_ENTER_RLC_SAFE_MODE      			1
-#define		MSG_EXIT_RLC_SAFE_MODE      			0
-
-#define CP_HPD_EOP_BASE_ADDR                              0xC904
-#define CP_HPD_EOP_BASE_ADDR_HI                           0xC908
-#define CP_HPD_EOP_VMID                                   0xC90C
-#define CP_HPD_EOP_CONTROL                                0xC910
-#define		EOP_SIZE(x)				((x) << 0)
-#define		EOP_SIZE_MASK      			(0x3f << 0)
-#define CP_MQD_BASE_ADDR                                  0xC914
-#define CP_MQD_BASE_ADDR_HI                               0xC918
-#define CP_HQD_ACTIVE                                     0xC91C
-#define CP_HQD_VMID                                       0xC920
-
-#define CP_HQD_PERSISTENT_STATE				0xC924u
-#define	DEFAULT_CP_HQD_PERSISTENT_STATE			(0x33U << 8)
-
-#define CP_HQD_PIPE_PRIORITY				0xC928u
-#define CP_HQD_QUEUE_PRIORITY				0xC92Cu
-#define CP_HQD_QUANTUM					0xC930u
-#define	QUANTUM_EN					1U
-#define	QUANTUM_SCALE_1MS				(1U << 4)
-#define	QUANTUM_DURATION(x)				((x) << 8)
-
-#define CP_HQD_PQ_BASE                                    0xC934
-#define CP_HQD_PQ_BASE_HI                                 0xC938
-#define CP_HQD_PQ_RPTR                                    0xC93C
-#define CP_HQD_PQ_RPTR_REPORT_ADDR                        0xC940
-#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI                     0xC944
-#define CP_HQD_PQ_WPTR_POLL_ADDR                          0xC948
-#define CP_HQD_PQ_WPTR_POLL_ADDR_HI                       0xC94C
-#define CP_HQD_PQ_DOORBELL_CONTROL                        0xC950
-#define		DOORBELL_OFFSET(x)			((x) << 2)
-#define		DOORBELL_OFFSET_MASK			(0x1fffff << 2)
-#define		DOORBELL_SOURCE      			(1 << 28)
-#define		DOORBELL_SCHD_HIT      			(1 << 29)
-#define		DOORBELL_EN      			(1 << 30)
-#define		DOORBELL_HIT      			(1 << 31)
-#define CP_HQD_PQ_WPTR                                    0xC954
-#define CP_HQD_PQ_CONTROL                                 0xC958
-#define		QUEUE_SIZE(x)				((x) << 0)
-#define		QUEUE_SIZE_MASK      			(0x3f << 0)
-#define		RPTR_BLOCK_SIZE(x)			((x) << 8)
-#define		RPTR_BLOCK_SIZE_MASK			(0x3f << 8)
-#define		PQ_VOLATILE      			(1 << 26)
-#define		NO_UPDATE_RPTR      			(1 << 27)
-#define		UNORD_DISPATCH      			(1 << 28)
-#define		ROQ_PQ_IB_FLIP      			(1 << 29)
-#define		PRIV_STATE      			(1 << 30)
-#define		KMD_QUEUE      				(1 << 31)
-
-#define CP_HQD_IB_BASE_ADDR				0xC95Cu
-#define CP_HQD_IB_BASE_ADDR_HI			0xC960u
-#define CP_HQD_IB_RPTR					0xC964u
-#define CP_HQD_IB_CONTROL				0xC968u
-#define	IB_ATC_EN					(1U << 23)
-#define	DEFAULT_MIN_IB_AVAIL_SIZE			(3U << 20)
-
-#define CP_HQD_DEQUEUE_REQUEST			0xC974
-#define	DEQUEUE_REQUEST_DRAIN				1
-#define DEQUEUE_REQUEST_RESET				2
-
-#define CP_MQD_CONTROL                                  0xC99C
-#define		MQD_VMID(x)				((x) << 0)
-#define		MQD_VMID_MASK      			(0xf << 0)
-
-#define CP_HQD_SEMA_CMD					0xC97Cu
-#define CP_HQD_MSG_TYPE					0xC980u
-#define CP_HQD_ATOMIC0_PREOP_LO			0xC984u
-#define CP_HQD_ATOMIC0_PREOP_HI			0xC988u
-#define CP_HQD_ATOMIC1_PREOP_LO			0xC98Cu
-#define CP_HQD_ATOMIC1_PREOP_HI			0xC990u
-#define CP_HQD_HQ_SCHEDULER0			0xC994u
-#define CP_HQD_HQ_SCHEDULER1			0xC998u
-
-#define SH_STATIC_MEM_CONFIG			0x9604u
-
-#define DB_RENDER_CONTROL                               0x28000
-
-#define PA_SC_RASTER_CONFIG                             0x28350
-#       define RASTER_CONFIG_RB_MAP_0                   0
-#       define RASTER_CONFIG_RB_MAP_1                   1
-#       define RASTER_CONFIG_RB_MAP_2                   2
-#       define RASTER_CONFIG_RB_MAP_3                   3
-#define		PKR_MAP(x)				((x) << 8)
-
-#define VGT_EVENT_INITIATOR                             0x28a90
-#       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)
-#       define SAMPLE_STREAMOUTSTATS2                   (2 << 0)
-#       define SAMPLE_STREAMOUTSTATS3                   (3 << 0)
-#       define CACHE_FLUSH_TS                           (4 << 0)
-#       define CACHE_FLUSH                              (6 << 0)
-#       define CS_PARTIAL_FLUSH                         (7 << 0)
-#       define VGT_STREAMOUT_RESET                      (10 << 0)
-#       define END_OF_PIPE_INCR_DE                      (11 << 0)
-#       define END_OF_PIPE_IB_END                       (12 << 0)
-#       define RST_PIX_CNT                              (13 << 0)
-#       define VS_PARTIAL_FLUSH                         (15 << 0)
-#       define PS_PARTIAL_FLUSH                         (16 << 0)
-#       define CACHE_FLUSH_AND_INV_TS_EVENT             (20 << 0)
-#       define ZPASS_DONE                               (21 << 0)
-#       define CACHE_FLUSH_AND_INV_EVENT                (22 << 0)
-#       define PERFCOUNTER_START                        (23 << 0)
-#       define PERFCOUNTER_STOP                         (24 << 0)
-#       define PIPELINESTAT_START                       (25 << 0)
-#       define PIPELINESTAT_STOP                        (26 << 0)
-#       define PERFCOUNTER_SAMPLE                       (27 << 0)
-#       define SAMPLE_PIPELINESTAT                      (30 << 0)
-#       define SO_VGT_STREAMOUT_FLUSH                   (31 << 0)
-#       define SAMPLE_STREAMOUTSTATS                    (32 << 0)
-#       define RESET_VTX_CNT                            (33 << 0)
-#       define VGT_FLUSH                                (36 << 0)
-#       define BOTTOM_OF_PIPE_TS                        (40 << 0)
-#       define DB_CACHE_FLUSH_AND_INV                   (42 << 0)
-#       define FLUSH_AND_INV_DB_DATA_TS                 (43 << 0)
-#       define FLUSH_AND_INV_DB_META                    (44 << 0)
-#       define FLUSH_AND_INV_CB_DATA_TS                 (45 << 0)
-#       define FLUSH_AND_INV_CB_META                    (46 << 0)
-#       define CS_DONE                                  (47 << 0)
-#       define PS_DONE                                  (48 << 0)
-#       define FLUSH_AND_INV_CB_PIXEL_DATA              (49 << 0)
-#       define THREAD_TRACE_START                       (51 << 0)
-#       define THREAD_TRACE_STOP                        (52 << 0)
-#       define THREAD_TRACE_FLUSH                       (54 << 0)
-#       define THREAD_TRACE_FINISH                      (55 << 0)
-#       define PIXEL_PIPE_STAT_CONTROL                  (56 << 0)
-#       define PIXEL_PIPE_STAT_DUMP                     (57 << 0)
-#       define PIXEL_PIPE_STAT_RESET                    (58 << 0)
-
-#define	SCRATCH_REG0					0x30100
-#define	SCRATCH_REG1					0x30104
-#define	SCRATCH_REG2					0x30108
-#define	SCRATCH_REG3					0x3010C
-#define	SCRATCH_REG4					0x30110
-#define	SCRATCH_REG5					0x30114
-#define	SCRATCH_REG6					0x30118
-#define	SCRATCH_REG7					0x3011C
-
-#define	SCRATCH_UMSK					0x30140
-#define	SCRATCH_ADDR					0x30144
-
-#define	CP_SEM_WAIT_TIMER				0x301BC
-
-#define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x301C8
-
-#define	CP_WAIT_REG_MEM_TIMEOUT				0x301D0
-
-#define GRBM_GFX_INDEX          			0x30800
-#define		INSTANCE_INDEX(x)			((x) << 0)
-#define		SH_INDEX(x)     			((x) << 8)
-#define		SE_INDEX(x)     			((x) << 16)
-#define		SH_BROADCAST_WRITES      		(1 << 29)
-#define		INSTANCE_BROADCAST_WRITES      		(1 << 30)
-#define		SE_BROADCAST_WRITES      		(1 << 31)
-
-#define	VGT_ESGS_RING_SIZE				0x30900
-#define	VGT_GSVS_RING_SIZE				0x30904
-#define	VGT_PRIMITIVE_TYPE				0x30908
-#define	VGT_INDEX_TYPE					0x3090C
-
-#define	VGT_NUM_INDICES					0x30930
-#define	VGT_NUM_INSTANCES				0x30934
-#define	VGT_TF_RING_SIZE				0x30938
-#define	VGT_HS_OFFCHIP_PARAM				0x3093C
-#define	VGT_TF_MEMORY_BASE				0x30940
-
-#define	PA_SU_LINE_STIPPLE_VALUE			0x30a00
-#define	PA_SC_LINE_STIPPLE_STATE			0x30a04
-
-#define	SQC_CACHES					0x30d20
-
-#define	CP_PERFMON_CNTL					0x36020
-
-#define	CGTS_SM_CTRL_REG				0x3c000
-#define		SM_MODE(x)				((x) << 17)
-#define		SM_MODE_MASK				(0x7 << 17)
-#define		SM_MODE_ENABLE				(1 << 20)
-#define		CGTS_OVERRIDE				(1 << 21)
-#define		CGTS_LS_OVERRIDE			(1 << 22)
-#define		ON_MONITOR_ADD_EN			(1 << 23)
-#define		ON_MONITOR_ADD(x)			((x) << 24)
-#define		ON_MONITOR_ADD_MASK			(0xff << 24)
-
-#define	CGTS_TCC_DISABLE				0x3c00c
-#define	CGTS_USER_TCC_DISABLE				0x3c010
-#define		TCC_DISABLE_MASK				0xFFFF0000
-#define		TCC_DISABLE_SHIFT				16
-
-#define	CB_CGTT_SCLK_CTRL				0x3c2a0
-
-/*
- * PM4
- */
-#define	PACKET_TYPE0	0
-#define	PACKET_TYPE1	1
-#define	PACKET_TYPE2	2
-#define	PACKET_TYPE3	3
-
-#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
-#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
-#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
-#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
-#define PACKET0(reg, n)	((PACKET_TYPE0 << 30) |				\
-			 (((reg) >> 2) & 0xFFFF) |			\
-			 ((n) & 0x3FFF) << 16)
-#define CP_PACKET2			0x80000000
-#define		PACKET2_PAD_SHIFT		0
-#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
-
-#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
-
-#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
-			 (((op) & 0xFF) << 8) |				\
-			 ((n) & 0x3FFF) << 16)
-
-#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
-
-/* Packet 3 types */
-#define	PACKET3_NOP					0x10
-#define	PACKET3_SET_BASE				0x11
-#define		PACKET3_BASE_INDEX(x)                  ((x) << 0)
-#define			CE_PARTITION_BASE		3
-#define	PACKET3_CLEAR_STATE				0x12
-#define	PACKET3_INDEX_BUFFER_SIZE			0x13
-#define	PACKET3_DISPATCH_DIRECT				0x15
-#define	PACKET3_DISPATCH_INDIRECT			0x16
-#define	PACKET3_ATOMIC_GDS				0x1D
-#define	PACKET3_ATOMIC_MEM				0x1E
-#define	PACKET3_OCCLUSION_QUERY				0x1F
-#define	PACKET3_SET_PREDICATION				0x20
-#define	PACKET3_REG_RMW					0x21
-#define	PACKET3_COND_EXEC				0x22
-#define	PACKET3_PRED_EXEC				0x23
-#define	PACKET3_DRAW_INDIRECT				0x24
-#define	PACKET3_DRAW_INDEX_INDIRECT			0x25
-#define	PACKET3_INDEX_BASE				0x26
-#define	PACKET3_DRAW_INDEX_2				0x27
-#define	PACKET3_CONTEXT_CONTROL				0x28
-#define	PACKET3_INDEX_TYPE				0x2A
-#define	PACKET3_DRAW_INDIRECT_MULTI			0x2C
-#define	PACKET3_DRAW_INDEX_AUTO				0x2D
-#define	PACKET3_NUM_INSTANCES				0x2F
-#define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30
-#define	PACKET3_INDIRECT_BUFFER_CONST			0x33
-#define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
-#define	PACKET3_DRAW_INDEX_OFFSET_2			0x35
-#define	PACKET3_DRAW_PREAMBLE				0x36
-#define	PACKET3_WRITE_DATA				0x37
-#define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
-                /* 0 - register
-		 * 1 - memory (sync - via GRBM)
-		 * 2 - gl2
-		 * 3 - gds
-		 * 4 - reserved
-		 * 5 - memory (async - direct)
-		 */
-#define		WR_ONE_ADDR                             (1 << 16)
-#define		WR_CONFIRM                              (1 << 20)
-#define		WRITE_DATA_CACHE_POLICY(x)              ((x) << 25)
-                /* 0 - LRU
-		 * 1 - Stream
-		 */
-#define		WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
-                /* 0 - me
-		 * 1 - pfp
-		 * 2 - ce
-		 */
-#define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38
-#define	PACKET3_MEM_SEMAPHORE				0x39
-#              define PACKET3_SEM_USE_MAILBOX       (0x1 << 16)
-#              define PACKET3_SEM_SEL_SIGNAL_TYPE   (0x1 << 20) /* 0 = increment, 1 = write 1 */
-#              define PACKET3_SEM_CLIENT_CODE	    ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
-#              define PACKET3_SEM_SEL_SIGNAL	    (0x6 << 29)
-#              define PACKET3_SEM_SEL_WAIT	    (0x7 << 29)
-#define	PACKET3_COPY_DW					0x3B
-#define	PACKET3_WAIT_REG_MEM				0x3C
-#define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
-                /* 0 - always
-		 * 1 - <
-		 * 2 - <=
-		 * 3 - ==
-		 * 4 - !=
-		 * 5 - >=
-		 * 6 - >
-		 */
-#define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
-                /* 0 - reg
-		 * 1 - mem
-		 */
-#define		WAIT_REG_MEM_OPERATION(x)               ((x) << 6)
-                /* 0 - wait_reg_mem
-		 * 1 - wr_wait_wr_reg
-		 */
-#define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
-                /* 0 - me
-		 * 1 - pfp
-		 */
-#define	PACKET3_INDIRECT_BUFFER				0x3F
-#define		INDIRECT_BUFFER_TCL2_VOLATILE           (1 << 22)
-#define		INDIRECT_BUFFER_VALID                   (1 << 23)
-#define		INDIRECT_BUFFER_CACHE_POLICY(x)         ((x) << 28)
-                /* 0 - LRU
-		 * 1 - Stream
-		 * 2 - Bypass
-		 */
-#define	PACKET3_COPY_DATA				0x40
-#define	PACKET3_PFP_SYNC_ME				0x42
-#define	PACKET3_SURFACE_SYNC				0x43
-#              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
-#              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
-#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
-#              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
-#              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
-#              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
-#              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
-#              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
-#              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
-#              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
-#              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
-#              define PACKET3_TCL1_VOL_ACTION_ENA  (1 << 15)
-#              define PACKET3_TC_VOL_ACTION_ENA    (1 << 16) /* L2 */
-#              define PACKET3_TC_WB_ACTION_ENA     (1 << 18) /* L2 */
-#              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
-#              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
-#              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
-#              define PACKET3_TC_ACTION_ENA        (1 << 23) /* L2 */
-#              define PACKET3_CB_ACTION_ENA        (1 << 25)
-#              define PACKET3_DB_ACTION_ENA        (1 << 26)
-#              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
-#              define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
-#              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
-#define	PACKET3_COND_WRITE				0x45
-#define	PACKET3_EVENT_WRITE				0x46
-#define		EVENT_TYPE(x)                           ((x) << 0)
-#define		EVENT_INDEX(x)                          ((x) << 8)
-                /* 0 - any non-TS event
-		 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
-		 * 2 - SAMPLE_PIPELINESTAT
-		 * 3 - SAMPLE_STREAMOUTSTAT*
-		 * 4 - *S_PARTIAL_FLUSH
-		 * 5 - EOP events
-		 * 6 - EOS events
-		 */
-#define	PACKET3_EVENT_WRITE_EOP				0x47
-#define		EOP_TCL1_VOL_ACTION_EN                  (1 << 12)
-#define		EOP_TC_VOL_ACTION_EN                    (1 << 13) /* L2 */
-#define		EOP_TC_WB_ACTION_EN                     (1 << 15) /* L2 */
-#define		EOP_TCL1_ACTION_EN                      (1 << 16)
-#define		EOP_TC_ACTION_EN                        (1 << 17) /* L2 */
-#define		EOP_TCL2_VOLATILE                       (1 << 24)
-#define		EOP_CACHE_POLICY(x)                     ((x) << 25)
-                /* 0 - LRU
-		 * 1 - Stream
-		 * 2 - Bypass
-		 */
-#define		DATA_SEL(x)                             ((x) << 29)
-                /* 0 - discard
-		 * 1 - send low 32bit data
-		 * 2 - send 64bit data
-		 * 3 - send 64bit GPU counter value
-		 * 4 - send 64bit sys counter value
-		 */
-#define		INT_SEL(x)                              ((x) << 24)
-                /* 0 - none
-		 * 1 - interrupt only (DATA_SEL = 0)
-		 * 2 - interrupt when data write is confirmed
-		 */
-#define		DST_SEL(x)                              ((x) << 16)
-                /* 0 - MC
-		 * 1 - TC/L2
-		 */
-#define	PACKET3_EVENT_WRITE_EOS				0x48
-#define	PACKET3_RELEASE_MEM				0x49
-#define	PACKET3_PREAMBLE_CNTL				0x4A
-#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
-#              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
-#define	PACKET3_DMA_DATA				0x50
-/* 1. header
- * 2. CONTROL
- * 3. SRC_ADDR_LO or DATA [31:0]
- * 4. SRC_ADDR_HI [31:0]
- * 5. DST_ADDR_LO [31:0]
- * 6. DST_ADDR_HI [7:0]
- * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
- */
-/* CONTROL */
-#              define PACKET3_DMA_DATA_ENGINE(x)     ((x) << 0)
-                /* 0 - ME
-		 * 1 - PFP
-		 */
-#              define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
-                /* 0 - LRU
-		 * 1 - Stream
-		 * 2 - Bypass
-		 */
-#              define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
-#              define PACKET3_DMA_DATA_DST_SEL(x)  ((x) << 20)
-                /* 0 - DST_ADDR using DAS
-		 * 1 - GDS
-		 * 3 - DST_ADDR using L2
-		 */
-#              define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
-                /* 0 - LRU
-		 * 1 - Stream
-		 * 2 - Bypass
-		 */
-#              define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
-#              define PACKET3_DMA_DATA_SRC_SEL(x)  ((x) << 29)
-                /* 0 - SRC_ADDR using SAS
-		 * 1 - GDS
-		 * 2 - DATA
-		 * 3 - SRC_ADDR using L2
-		 */
-#              define PACKET3_DMA_DATA_CP_SYNC     (1 << 31)
-/* COMMAND */
-#              define PACKET3_DMA_DATA_DIS_WC      (1 << 21)
-#              define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
-                /* 0 - none
-		 * 1 - 8 in 16
-		 * 2 - 8 in 32
-		 * 3 - 8 in 64
-		 */
-#              define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
-                /* 0 - none
-		 * 1 - 8 in 16
-		 * 2 - 8 in 32
-		 * 3 - 8 in 64
-		 */
-#              define PACKET3_DMA_DATA_CMD_SAS     (1 << 26)
-                /* 0 - memory
-		 * 1 - register
-		 */
-#              define PACKET3_DMA_DATA_CMD_DAS     (1 << 27)
-                /* 0 - memory
-		 * 1 - register
-		 */
-#              define PACKET3_DMA_DATA_CMD_SAIC    (1 << 28)
-#              define PACKET3_DMA_DATA_CMD_DAIC    (1 << 29)
-#              define PACKET3_DMA_DATA_CMD_RAW_WAIT  (1 << 30)
-#define	PACKET3_AQUIRE_MEM				0x58
-#define	PACKET3_REWIND					0x59
-#define	PACKET3_LOAD_UCONFIG_REG			0x5E
-#define	PACKET3_LOAD_SH_REG				0x5F
-#define	PACKET3_LOAD_CONFIG_REG				0x60
-#define	PACKET3_LOAD_CONTEXT_REG			0x61
-#define	PACKET3_SET_CONFIG_REG				0x68
-#define		PACKET3_SET_CONFIG_REG_START			0x00008000
-#define		PACKET3_SET_CONFIG_REG_END			0x0000b000
-#define	PACKET3_SET_CONTEXT_REG				0x69
-#define		PACKET3_SET_CONTEXT_REG_START			0x00028000
-#define		PACKET3_SET_CONTEXT_REG_END			0x00029000
-#define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
-#define	PACKET3_SET_SH_REG				0x76
-#define		PACKET3_SET_SH_REG_START			0x0000b000
-#define		PACKET3_SET_SH_REG_END				0x0000c000
-#define	PACKET3_SET_SH_REG_OFFSET			0x77
-#define	PACKET3_SET_QUEUE_REG				0x78
-#define	PACKET3_SET_UCONFIG_REG				0x79
-#define		PACKET3_SET_UCONFIG_REG_START			0x00030000
-#define		PACKET3_SET_UCONFIG_REG_END			0x00031000
-#define	PACKET3_SCRATCH_RAM_WRITE			0x7D
-#define	PACKET3_SCRATCH_RAM_READ			0x7E
-#define	PACKET3_LOAD_CONST_RAM				0x80
-#define	PACKET3_WRITE_CONST_RAM				0x81
-#define	PACKET3_DUMP_CONST_RAM				0x83
-#define	PACKET3_INCREMENT_CE_COUNTER			0x84
-#define	PACKET3_INCREMENT_DE_COUNTER			0x85
-#define	PACKET3_WAIT_ON_CE_COUNTER			0x86
-#define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
-#define	PACKET3_SWITCH_BUFFER				0x8B
-
-/* SDMA - first instance at 0xd000, second at 0xd800 */
-#define SDMA0_REGISTER_OFFSET                             0x0 /* not a register */
-#define SDMA1_REGISTER_OFFSET                             0x800 /* not a register */
-
-#define	SDMA0_UCODE_ADDR                                  0xD000
-#define	SDMA0_UCODE_DATA                                  0xD004
-#define	SDMA0_POWER_CNTL                                  0xD008
-#define	SDMA0_CLK_CTRL                                    0xD00C
-
-#define SDMA0_CNTL                                        0xD010
-#       define TRAP_ENABLE                                (1 << 0)
-#       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)
-#       define SEM_WAIT_INT_ENABLE                        (1 << 2)
-#       define DATA_SWAP_ENABLE                           (1 << 3)
-#       define FENCE_SWAP_ENABLE                          (1 << 4)
-#       define AUTO_CTXSW_ENABLE                          (1 << 18)
-#       define CTXEMPTY_INT_ENABLE                        (1 << 28)
-
-#define SDMA0_TILING_CONFIG  				  0xD018
-
-#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL                   0xD020
-#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL                    0xD024
-
-#define SDMA0_STATUS_REG                                  0xd034
-#       define SDMA_IDLE                                  (1 << 0)
-
-#define SDMA0_ME_CNTL                                     0xD048
-#       define SDMA_HALT                                  (1 << 0)
-
-#define SDMA0_GFX_RB_CNTL                                 0xD200
-#       define SDMA_RB_ENABLE                             (1 << 0)
-#       define SDMA_RB_SIZE(x)                            ((x) << 1) /* log2 */
-#       define SDMA_RB_SWAP_ENABLE                        (1 << 9) /* 8IN32 */
-#       define SDMA_RPTR_WRITEBACK_ENABLE                 (1 << 12)
-#       define SDMA_RPTR_WRITEBACK_SWAP_ENABLE            (1 << 13)  /* 8IN32 */
-#       define SDMA_RPTR_WRITEBACK_TIMER(x)               ((x) << 16) /* log2 */
-#define SDMA0_GFX_RB_BASE                                 0xD204
-#define SDMA0_GFX_RB_BASE_HI                              0xD208
-#define SDMA0_GFX_RB_RPTR                                 0xD20C
-#define SDMA0_GFX_RB_WPTR                                 0xD210
-
-#define SDMA0_GFX_RB_RPTR_ADDR_HI                         0xD220
-#define SDMA0_GFX_RB_RPTR_ADDR_LO                         0xD224
-#define SDMA0_GFX_IB_CNTL                                 0xD228
-#       define SDMA_IB_ENABLE                             (1 << 0)
-#       define SDMA_IB_SWAP_ENABLE                        (1 << 4)
-#       define SDMA_SWITCH_INSIDE_IB                      (1 << 8)
-#       define SDMA_CMD_VMID(x)                           ((x) << 16)
-
-#define SDMA0_GFX_VIRTUAL_ADDR                            0xD29C
-#define SDMA0_GFX_APE1_CNTL                               0xD2A0
-
-#define SDMA_PACKET(op, sub_op, e)	((((e) & 0xFFFF) << 16) |	\
-					 (((sub_op) & 0xFF) << 8) |	\
-					 (((op) & 0xFF) << 0))
-/* sDMA opcodes */
-#define	SDMA_OPCODE_NOP					  0
-#define	SDMA_OPCODE_COPY				  1
-#       define SDMA_COPY_SUB_OPCODE_LINEAR                0
-#       define SDMA_COPY_SUB_OPCODE_TILED                 1
-#       define SDMA_COPY_SUB_OPCODE_SOA                   3
-#       define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW     4
-#       define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW      5
-#       define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW        6
-#define	SDMA_OPCODE_WRITE				  2
-#       define SDMA_WRITE_SUB_OPCODE_LINEAR               0
-#       define SDMA_WRITE_SUB_OPCODE_TILED                1
-#define	SDMA_OPCODE_INDIRECT_BUFFER			  4
-#define	SDMA_OPCODE_FENCE				  5
-#define	SDMA_OPCODE_TRAP				  6
-#define	SDMA_OPCODE_SEMAPHORE				  7
-#       define SDMA_SEMAPHORE_EXTRA_O                     (1 << 13)
-                /* 0 - increment
-		 * 1 - write 1
-		 */
-#       define SDMA_SEMAPHORE_EXTRA_S                     (1 << 14)
-                /* 0 - wait
-		 * 1 - signal
-		 */
-#       define SDMA_SEMAPHORE_EXTRA_M                     (1 << 15)
-                /* mailbox */
-#define	SDMA_OPCODE_POLL_REG_MEM			  8
-#       define SDMA_POLL_REG_MEM_EXTRA_OP(x)              ((x) << 10)
-                /* 0 - wait_reg_mem
-		 * 1 - wr_wait_wr_reg
-		 */
-#       define SDMA_POLL_REG_MEM_EXTRA_FUNC(x)            ((x) << 12)
-                /* 0 - always
-		 * 1 - <
-		 * 2 - <=
-		 * 3 - ==
-		 * 4 - !=
-		 * 5 - >=
-		 * 6 - >
-		 */
-#       define SDMA_POLL_REG_MEM_EXTRA_M                  (1 << 15)
-                /* 0 = register
-		 * 1 = memory
-		 */
-#define	SDMA_OPCODE_COND_EXEC				  9
-#define	SDMA_OPCODE_CONSTANT_FILL			  11
-#       define SDMA_CONSTANT_FILL_EXTRA_SIZE(x)           ((x) << 14)
-                /* 0 = byte fill
-		 * 2 = DW fill
-		 */
-#define	SDMA_OPCODE_GENERATE_PTE_PDE			  12
-#define	SDMA_OPCODE_TIMESTAMP				  13
-#       define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL        0
-#       define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL        1
-#       define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL       2
-#define	SDMA_OPCODE_SRBM_WRITE				  14
-#       define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x)       ((x) << 12)
-                /* byte mask */
-
-/* UVD */
-
-#define UVD_UDEC_ADDR_CONFIG		0xef4c
-#define UVD_UDEC_DB_ADDR_CONFIG		0xef50
-#define UVD_UDEC_DBW_ADDR_CONFIG	0xef54
-#define UVD_NO_OP			0xeffc
-
-#define UVD_LMI_EXT40_ADDR		0xf498
-#define UVD_GP_SCRATCH4			0xf4e0
-#define UVD_LMI_ADDR_EXT		0xf594
-#define UVD_VCPU_CACHE_OFFSET0		0xf608
-#define UVD_VCPU_CACHE_SIZE0		0xf60c
-#define UVD_VCPU_CACHE_OFFSET1		0xf610
-#define UVD_VCPU_CACHE_SIZE1		0xf614
-#define UVD_VCPU_CACHE_OFFSET2		0xf618
-#define UVD_VCPU_CACHE_SIZE2		0xf61c
-
-#define UVD_RBC_RB_RPTR			0xf690
-#define UVD_RBC_RB_WPTR			0xf694
-
-#define	UVD_CGC_CTRL					0xF4B0
-#	define DCM					(1 << 0)
-#	define CG_DT(x)					((x) << 2)
-#	define CG_DT_MASK				(0xf << 2)
-#	define CLK_OD(x)				((x) << 6)
-#	define CLK_OD_MASK				(0x1f << 6)
-
-#define UVD_STATUS					0xf6bc
-
-/* UVD clocks */
-
-#define CG_DCLK_CNTL			0xC050009C
-#	define DCLK_DIVIDER_MASK	0x7f
-#	define DCLK_DIR_CNTL_EN		(1 << 8)
-#define CG_DCLK_STATUS			0xC05000A0
-#	define DCLK_STATUS		(1 << 0)
-#define CG_VCLK_CNTL			0xC05000A4
-#define CG_VCLK_STATUS			0xC05000A8
-
-/* UVD CTX indirect */
-#define	UVD_CGC_MEM_CTRL				0xC0
-
-/* VCE */
-
-#define VCE_VCPU_CACHE_OFFSET0		0x20024
-#define VCE_VCPU_CACHE_SIZE0		0x20028
-#define VCE_VCPU_CACHE_OFFSET1		0x2002c
-#define VCE_VCPU_CACHE_SIZE1		0x20030
-#define VCE_VCPU_CACHE_OFFSET2		0x20034
-#define VCE_VCPU_CACHE_SIZE2		0x20038
-#define VCE_RB_RPTR2			0x20178
-#define VCE_RB_WPTR2			0x2017c
-#define VCE_RB_RPTR			0x2018c
-#define VCE_RB_WPTR			0x20190
-#define VCE_CLOCK_GATING_A		0x202f8
-#	define CGC_CLK_GATE_DLY_TIMER_MASK	(0xf << 0)
-#	define CGC_CLK_GATE_DLY_TIMER(x)	((x) << 0)
-#	define CGC_CLK_GATER_OFF_DLY_TIMER_MASK	(0xff << 4)
-#	define CGC_CLK_GATER_OFF_DLY_TIMER(x)	((x) << 4)
-#	define CGC_UENC_WAIT_AWAKE	(1 << 18)
-#define VCE_CLOCK_GATING_B		0x202fc
-#define VCE_CGTT_CLK_OVERRIDE		0x207a0
-#define VCE_UENC_CLOCK_GATING		0x207bc
-#	define CLOCK_ON_DELAY_MASK	(0xf << 0)
-#	define CLOCK_ON_DELAY(x)	((x) << 0)
-#	define CLOCK_OFF_DELAY_MASK	(0xff << 4)
-#	define CLOCK_OFF_DELAY(x)	((x) << 4)
-#define VCE_UENC_REG_CLOCK_GATING	0x207c0
-#define VCE_SYS_INT_EN			0x21300
-#	define VCE_SYS_INT_TRAP_INTERRUPT_EN	(1 << 3)
-#define VCE_LMI_VCPU_CACHE_40BIT_BAR	0x2145c
-#define VCE_LMI_CTRL2			0x21474
-#define VCE_LMI_CTRL			0x21498
-#define VCE_LMI_VM_CTRL			0x214a0
-#define VCE_LMI_SWAP_CNTL		0x214b4
-#define VCE_LMI_SWAP_CNTL1		0x214b8
-#define VCE_LMI_CACHE_CTRL		0x214f4
-
-#define VCE_CMD_NO_OP		0x00000000
-#define VCE_CMD_END		0x00000001
-#define VCE_CMD_IB		0x00000002
-#define VCE_CMD_FENCE		0x00000003
-#define VCE_CMD_TRAP		0x00000004
-#define VCE_CMD_IB_AUTO		0x00000005
-#define VCE_CMD_SEMAPHORE	0x00000006
-
-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS		0x3398u
-#define ATC_VMID0_PASID_MAPPING				0x339Cu
-#define ATC_VMID_PASID_MAPPING_PASID_MASK		(0xFFFF)
-#define ATC_VMID_PASID_MAPPING_PASID_SHIFT		0
-#define ATC_VMID_PASID_MAPPING_VALID_MASK		(0x1 << 31)
-#define ATC_VMID_PASID_MAPPING_VALID_SHIFT		31
-
-#define ATC_VM_APERTURE0_CNTL					0x3310u
-#define	ATS_ACCESS_MODE_NEVER						0
-#define	ATS_ACCESS_MODE_ALWAYS						1
-
-#define ATC_VM_APERTURE0_CNTL2					0x3318u
-#define ATC_VM_APERTURE0_HIGH_ADDR				0x3308u
-#define ATC_VM_APERTURE0_LOW_ADDR				0x3300u
-#define ATC_VM_APERTURE1_CNTL					0x3314u
-#define ATC_VM_APERTURE1_CNTL2					0x331Cu
-#define ATC_VM_APERTURE1_HIGH_ADDR				0x330Cu
-#define ATC_VM_APERTURE1_LOW_ADDR				0x3304u
-
-#define IH_VMID_0_LUT						0x3D40u
-
-#endif
diff --git a/hw/display/r300d.h b/hw/display/r300d.h
deleted file mode 100644
index ff229a00d2..0000000000
--- a/hw/display/r300d.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __R300D_H__
-#define __R300D_H__
-
-#define CP_PACKET0			0x00000000
-#define		PACKET0_BASE_INDEX_SHIFT	0
-#define		PACKET0_BASE_INDEX_MASK		(0x1ffff << 0)
-#define		PACKET0_COUNT_SHIFT		16
-#define		PACKET0_COUNT_MASK		(0x3fff << 16)
-#define CP_PACKET1			0x40000000
-#define CP_PACKET2			0x80000000
-#define		PACKET2_PAD_SHIFT		0
-#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
-#define CP_PACKET3			0xC0000000
-#define		PACKET3_IT_OPCODE_SHIFT		8
-#define		PACKET3_IT_OPCODE_MASK		(0xff << 8)
-#define		PACKET3_COUNT_SHIFT		16
-#define		PACKET3_COUNT_MASK		(0x3fff << 16)
-/* PACKET3 op code */
-#define		PACKET3_NOP			0x10
-#define		PACKET3_3D_DRAW_VBUF		0x28
-#define		PACKET3_3D_DRAW_IMMD		0x29
-#define		PACKET3_3D_DRAW_INDX		0x2A
-#define		PACKET3_3D_LOAD_VBPNTR		0x2F
-#define		PACKET3_3D_CLEAR_ZMASK		0x32
-#define		PACKET3_INDX_BUFFER		0x33
-#define		PACKET3_3D_DRAW_VBUF_2		0x34
-#define		PACKET3_3D_DRAW_IMMD_2		0x35
-#define		PACKET3_3D_DRAW_INDX_2		0x36
-#define		PACKET3_3D_CLEAR_HIZ		0x37
-#define		PACKET3_3D_CLEAR_CMASK		0x38
-#define		PACKET3_BITBLT_MULTI		0x9B
-
-#define PACKET0(reg, n)	(CP_PACKET0 |					\
-			 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |	\
-			 REG_SET(PACKET0_COUNT, (n)))
-#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
-#define PACKET3(op, n)	(CP_PACKET3 |					\
-			 REG_SET(PACKET3_IT_OPCODE, (op)) |		\
-			 REG_SET(PACKET3_COUNT, (n)))
-
-/* Registers */
-#define R_000148_MC_FB_LOCATION                      0x000148
-#define   S_000148_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
-#define   G_000148_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
-#define   C_000148_MC_FB_START                         0xFFFF0000
-#define   S_000148_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
-#define   G_000148_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
-#define   C_000148_MC_FB_TOP                           0x0000FFFF
-#define R_00014C_MC_AGP_LOCATION                     0x00014C
-#define   S_00014C_MC_AGP_START(x)                     (((x) & 0xFFFF) << 0)
-#define   G_00014C_MC_AGP_START(x)                     (((x) >> 0) & 0xFFFF)
-#define   C_00014C_MC_AGP_START                        0xFFFF0000
-#define   S_00014C_MC_AGP_TOP(x)                       (((x) & 0xFFFF) << 16)
-#define   G_00014C_MC_AGP_TOP(x)                       (((x) >> 16) & 0xFFFF)
-#define   C_00014C_MC_AGP_TOP                          0x0000FFFF
-#define R_00015C_AGP_BASE_2                          0x00015C
-#define   S_00015C_AGP_BASE_ADDR_2(x)                  (((x) & 0xF) << 0)
-#define   G_00015C_AGP_BASE_ADDR_2(x)                  (((x) >> 0) & 0xF)
-#define   C_00015C_AGP_BASE_ADDR_2                     0xFFFFFFF0
-#define R_000170_AGP_BASE                            0x000170
-#define   S_000170_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
-#define   G_000170_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
-#define   C_000170_AGP_BASE_ADDR                       0x00000000
-#define R_0007C0_CP_STAT                             0x0007C0
-#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
-#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
-#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
-#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
-#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
-#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
-#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
-#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
-#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
-#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
-#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
-#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
-#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
-#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
-#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
-#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
-#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
-#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
-#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
-#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
-#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
-#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
-#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
-#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
-#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
-#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
-#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
-#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
-#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
-#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
-#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
-#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
-#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
-#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
-#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
-#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
-#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
-#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
-#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
-#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
-#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
-#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
-#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
-#define R_000E40_RBBM_STATUS                         0x000E40
-#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
-#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
-#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
-#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
-#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
-#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
-#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
-#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
-#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
-#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
-#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
-#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
-#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
-#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
-#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
-#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
-#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
-#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
-#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
-#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
-#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
-#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
-#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
-#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
-#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
-#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
-#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
-#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
-#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
-#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
-#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
-#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
-#define   C_000E40_E2_BUSY                             0xFFFDFFFF
-#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
-#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
-#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
-#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
-#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
-#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
-#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
-#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
-#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
-#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
-#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
-#define   C_000E40_RE_BUSY                             0xFFDFFFFF
-#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
-#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
-#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
-#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
-#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
-#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
-#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
-#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
-#define   C_000E40_PB_BUSY                             0xFEFFFFFF
-#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
-#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
-#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
-#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
-#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
-#define   C_000E40_GA_BUSY                             0xFBFFFFFF
-#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
-#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
-#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
-#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
-#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
-#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
-#define R_0000F0_RBBM_SOFT_RESET                     0x0000F0
-#define   S_0000F0_SOFT_RESET_CP(x)                    (((x) & 0x1) << 0)
-#define   G_0000F0_SOFT_RESET_CP(x)                    (((x) >> 0) & 0x1)
-#define   C_0000F0_SOFT_RESET_CP                       0xFFFFFFFE
-#define   S_0000F0_SOFT_RESET_HI(x)                    (((x) & 0x1) << 1)
-#define   G_0000F0_SOFT_RESET_HI(x)                    (((x) >> 1) & 0x1)
-#define   C_0000F0_SOFT_RESET_HI                       0xFFFFFFFD
-#define   S_0000F0_SOFT_RESET_VAP(x)                   (((x) & 0x1) << 2)
-#define   G_0000F0_SOFT_RESET_VAP(x)                   (((x) >> 2) & 0x1)
-#define   C_0000F0_SOFT_RESET_VAP                      0xFFFFFFFB
-#define   S_0000F0_SOFT_RESET_RE(x)                    (((x) & 0x1) << 3)
-#define   G_0000F0_SOFT_RESET_RE(x)                    (((x) >> 3) & 0x1)
-#define   C_0000F0_SOFT_RESET_RE                       0xFFFFFFF7
-#define   S_0000F0_SOFT_RESET_PP(x)                    (((x) & 0x1) << 4)
-#define   G_0000F0_SOFT_RESET_PP(x)                    (((x) >> 4) & 0x1)
-#define   C_0000F0_SOFT_RESET_PP                       0xFFFFFFEF
-#define   S_0000F0_SOFT_RESET_E2(x)                    (((x) & 0x1) << 5)
-#define   G_0000F0_SOFT_RESET_E2(x)                    (((x) >> 5) & 0x1)
-#define   C_0000F0_SOFT_RESET_E2                       0xFFFFFFDF
-#define   S_0000F0_SOFT_RESET_RB(x)                    (((x) & 0x1) << 6)
-#define   G_0000F0_SOFT_RESET_RB(x)                    (((x) >> 6) & 0x1)
-#define   C_0000F0_SOFT_RESET_RB                       0xFFFFFFBF
-#define   S_0000F0_SOFT_RESET_HDP(x)                   (((x) & 0x1) << 7)
-#define   G_0000F0_SOFT_RESET_HDP(x)                   (((x) >> 7) & 0x1)
-#define   C_0000F0_SOFT_RESET_HDP                      0xFFFFFF7F
-#define   S_0000F0_SOFT_RESET_MC(x)                    (((x) & 0x1) << 8)
-#define   G_0000F0_SOFT_RESET_MC(x)                    (((x) >> 8) & 0x1)
-#define   C_0000F0_SOFT_RESET_MC                       0xFFFFFEFF
-#define   S_0000F0_SOFT_RESET_AIC(x)                   (((x) & 0x1) << 9)
-#define   G_0000F0_SOFT_RESET_AIC(x)                   (((x) >> 9) & 0x1)
-#define   C_0000F0_SOFT_RESET_AIC                      0xFFFFFDFF
-#define   S_0000F0_SOFT_RESET_VIP(x)                   (((x) & 0x1) << 10)
-#define   G_0000F0_SOFT_RESET_VIP(x)                   (((x) >> 10) & 0x1)
-#define   C_0000F0_SOFT_RESET_VIP                      0xFFFFFBFF
-#define   S_0000F0_SOFT_RESET_DISP(x)                  (((x) & 0x1) << 11)
-#define   G_0000F0_SOFT_RESET_DISP(x)                  (((x) >> 11) & 0x1)
-#define   C_0000F0_SOFT_RESET_DISP                     0xFFFFF7FF
-#define   S_0000F0_SOFT_RESET_CG(x)                    (((x) & 0x1) << 12)
-#define   G_0000F0_SOFT_RESET_CG(x)                    (((x) >> 12) & 0x1)
-#define   C_0000F0_SOFT_RESET_CG                       0xFFFFEFFF
-#define   S_0000F0_SOFT_RESET_GA(x)                    (((x) & 0x1) << 13)
-#define   G_0000F0_SOFT_RESET_GA(x)                    (((x) >> 13) & 0x1)
-#define   C_0000F0_SOFT_RESET_GA                       0xFFFFDFFF
-#define   S_0000F0_SOFT_RESET_IDCT(x)                  (((x) & 0x1) << 14)
-#define   G_0000F0_SOFT_RESET_IDCT(x)                  (((x) >> 14) & 0x1)
-#define   C_0000F0_SOFT_RESET_IDCT                     0xFFFFBFFF
-
-#define R_00000D_SCLK_CNTL                           0x00000D
-#define   S_00000D_SCLK_SRC_SEL(x)                     (((x) & 0x7) << 0)
-#define   G_00000D_SCLK_SRC_SEL(x)                     (((x) >> 0) & 0x7)
-#define   C_00000D_SCLK_SRC_SEL                        0xFFFFFFF8
-#define   S_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 3)
-#define   G_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) >> 3) & 0x1)
-#define   C_00000D_CP_MAX_DYN_STOP_LAT                 0xFFFFFFF7
-#define   S_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 4)
-#define   G_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) >> 4) & 0x1)
-#define   C_00000D_HDP_MAX_DYN_STOP_LAT                0xFFFFFFEF
-#define   S_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 5)
-#define   G_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) >> 5) & 0x1)
-#define   C_00000D_TV_MAX_DYN_STOP_LAT                 0xFFFFFFDF
-#define   S_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 6)
-#define   G_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) >> 6) & 0x1)
-#define   C_00000D_E2_MAX_DYN_STOP_LAT                 0xFFFFFFBF
-#define   S_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 7)
-#define   G_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) >> 7) & 0x1)
-#define   C_00000D_SE_MAX_DYN_STOP_LAT                 0xFFFFFF7F
-#define   S_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) & 0x1) << 8)
-#define   G_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) >> 8) & 0x1)
-#define   C_00000D_IDCT_MAX_DYN_STOP_LAT               0xFFFFFEFF
-#define   S_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 9)
-#define   G_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) >> 9) & 0x1)
-#define   C_00000D_VIP_MAX_DYN_STOP_LAT                0xFFFFFDFF
-#define   S_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 10)
-#define   G_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) >> 10) & 0x1)
-#define   C_00000D_RE_MAX_DYN_STOP_LAT                 0xFFFFFBFF
-#define   S_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 11)
-#define   G_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) >> 11) & 0x1)
-#define   C_00000D_PB_MAX_DYN_STOP_LAT                 0xFFFFF7FF
-#define   S_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 12)
-#define   G_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) >> 12) & 0x1)
-#define   C_00000D_TAM_MAX_DYN_STOP_LAT                0xFFFFEFFF
-#define   S_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 13)
-#define   G_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) >> 13) & 0x1)
-#define   C_00000D_TDM_MAX_DYN_STOP_LAT                0xFFFFDFFF
-#define   S_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 14)
-#define   G_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) >> 14) & 0x1)
-#define   C_00000D_RB_MAX_DYN_STOP_LAT                 0xFFFFBFFF
-#define   S_00000D_FORCE_DISP2(x)                      (((x) & 0x1) << 15)
-#define   G_00000D_FORCE_DISP2(x)                      (((x) >> 15) & 0x1)
-#define   C_00000D_FORCE_DISP2                         0xFFFF7FFF
-#define   S_00000D_FORCE_CP(x)                         (((x) & 0x1) << 16)
-#define   G_00000D_FORCE_CP(x)                         (((x) >> 16) & 0x1)
-#define   C_00000D_FORCE_CP                            0xFFFEFFFF
-#define   S_00000D_FORCE_HDP(x)                        (((x) & 0x1) << 17)
-#define   G_00000D_FORCE_HDP(x)                        (((x) >> 17) & 0x1)
-#define   C_00000D_FORCE_HDP                           0xFFFDFFFF
-#define   S_00000D_FORCE_DISP1(x)                      (((x) & 0x1) << 18)
-#define   G_00000D_FORCE_DISP1(x)                      (((x) >> 18) & 0x1)
-#define   C_00000D_FORCE_DISP1                         0xFFFBFFFF
-#define   S_00000D_FORCE_TOP(x)                        (((x) & 0x1) << 19)
-#define   G_00000D_FORCE_TOP(x)                        (((x) >> 19) & 0x1)
-#define   C_00000D_FORCE_TOP                           0xFFF7FFFF
-#define   S_00000D_FORCE_E2(x)                         (((x) & 0x1) << 20)
-#define   G_00000D_FORCE_E2(x)                         (((x) >> 20) & 0x1)
-#define   C_00000D_FORCE_E2                            0xFFEFFFFF
-#define   S_00000D_FORCE_SE(x)                         (((x) & 0x1) << 21)
-#define   G_00000D_FORCE_SE(x)                         (((x) >> 21) & 0x1)
-#define   C_00000D_FORCE_SE                            0xFFDFFFFF
-#define   S_00000D_FORCE_IDCT(x)                       (((x) & 0x1) << 22)
-#define   G_00000D_FORCE_IDCT(x)                       (((x) >> 22) & 0x1)
-#define   C_00000D_FORCE_IDCT                          0xFFBFFFFF
-#define   S_00000D_FORCE_VIP(x)                        (((x) & 0x1) << 23)
-#define   G_00000D_FORCE_VIP(x)                        (((x) >> 23) & 0x1)
-#define   C_00000D_FORCE_VIP                           0xFF7FFFFF
-#define   S_00000D_FORCE_RE(x)                         (((x) & 0x1) << 24)
-#define   G_00000D_FORCE_RE(x)                         (((x) >> 24) & 0x1)
-#define   C_00000D_FORCE_RE                            0xFEFFFFFF
-#define   S_00000D_FORCE_PB(x)                         (((x) & 0x1) << 25)
-#define   G_00000D_FORCE_PB(x)                         (((x) >> 25) & 0x1)
-#define   C_00000D_FORCE_PB                            0xFDFFFFFF
-#define   S_00000D_FORCE_TAM(x)                        (((x) & 0x1) << 26)
-#define   G_00000D_FORCE_TAM(x)                        (((x) >> 26) & 0x1)
-#define   C_00000D_FORCE_TAM                           0xFBFFFFFF
-#define   S_00000D_FORCE_TDM(x)                        (((x) & 0x1) << 27)
-#define   G_00000D_FORCE_TDM(x)                        (((x) >> 27) & 0x1)
-#define   C_00000D_FORCE_TDM                           0xF7FFFFFF
-#define   S_00000D_FORCE_RB(x)                         (((x) & 0x1) << 28)
-#define   G_00000D_FORCE_RB(x)                         (((x) >> 28) & 0x1)
-#define   C_00000D_FORCE_RB                            0xEFFFFFFF
-#define   S_00000D_FORCE_TV_SCLK(x)                    (((x) & 0x1) << 29)
-#define   G_00000D_FORCE_TV_SCLK(x)                    (((x) >> 29) & 0x1)
-#define   C_00000D_FORCE_TV_SCLK                       0xDFFFFFFF
-#define   S_00000D_FORCE_SUBPIC(x)                     (((x) & 0x1) << 30)
-#define   G_00000D_FORCE_SUBPIC(x)                     (((x) >> 30) & 0x1)
-#define   C_00000D_FORCE_SUBPIC                        0xBFFFFFFF
-#define   S_00000D_FORCE_OV0(x)                        (((x) & 0x1) << 31)
-#define   G_00000D_FORCE_OV0(x)                        (((x) >> 31) & 0x1)
-#define   C_00000D_FORCE_OV0                           0x7FFFFFFF
-
-#endif
diff --git a/hw/display/r420d.h b/hw/display/r420d.h
deleted file mode 100644
index fc78d31a0b..0000000000
--- a/hw/display/r420d.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef R420D_H
-#define R420D_H
-
-#define R_0001F8_MC_IND_INDEX                        0x0001F8
-#define   S_0001F8_MC_IND_ADDR(x)                      (((x) & 0x7F) << 0)
-#define   G_0001F8_MC_IND_ADDR(x)                      (((x) >> 0) & 0x7F)
-#define   C_0001F8_MC_IND_ADDR                         0xFFFFFF80
-#define   S_0001F8_MC_IND_WR_EN(x)                     (((x) & 0x1) << 8)
-#define   G_0001F8_MC_IND_WR_EN(x)                     (((x) >> 8) & 0x1)
-#define   C_0001F8_MC_IND_WR_EN                        0xFFFFFEFF
-#define R_0001FC_MC_IND_DATA                         0x0001FC
-#define   S_0001FC_MC_IND_DATA(x)                      (((x) & 0xFFFFFFFF) << 0)
-#define   G_0001FC_MC_IND_DATA(x)                      (((x) >> 0) & 0xFFFFFFFF)
-#define   C_0001FC_MC_IND_DATA                         0x00000000
-#define R_0007C0_CP_STAT                             0x0007C0
-#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
-#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
-#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
-#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
-#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
-#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
-#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
-#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
-#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
-#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
-#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
-#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
-#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
-#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
-#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
-#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
-#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
-#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
-#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
-#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
-#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
-#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
-#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
-#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
-#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
-#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
-#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
-#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
-#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
-#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
-#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
-#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
-#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
-#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
-#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
-#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
-#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
-#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
-#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
-#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
-#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
-#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
-#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
-#define R_000E40_RBBM_STATUS                         0x000E40
-#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
-#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
-#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
-#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
-#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
-#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
-#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
-#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
-#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
-#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
-#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
-#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
-#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
-#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
-#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
-#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
-#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
-#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
-#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
-#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
-#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
-#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
-#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
-#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
-#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
-#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
-#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
-#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
-#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
-#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
-#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
-#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
-#define   C_000E40_E2_BUSY                             0xFFFDFFFF
-#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
-#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
-#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
-#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
-#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
-#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
-#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
-#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
-#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
-#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
-#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
-#define   C_000E40_RE_BUSY                             0xFFDFFFFF
-#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
-#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
-#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
-#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
-#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
-#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
-#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
-#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
-#define   C_000E40_PB_BUSY                             0xFEFFFFFF
-#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
-#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
-#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
-#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
-#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
-#define   C_000E40_GA_BUSY                             0xFBFFFFFF
-#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
-#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
-#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
-#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
-#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
-#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
-
-/* CLK registers */
-#define R_00000D_SCLK_CNTL                           0x00000D
-#define   S_00000D_SCLK_SRC_SEL(x)                     (((x) & 0x7) << 0)
-#define   G_00000D_SCLK_SRC_SEL(x)                     (((x) >> 0) & 0x7)
-#define   C_00000D_SCLK_SRC_SEL                        0xFFFFFFF8
-#define   S_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 3)
-#define   G_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) >> 3) & 0x1)
-#define   C_00000D_CP_MAX_DYN_STOP_LAT                 0xFFFFFFF7
-#define   S_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 4)
-#define   G_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) >> 4) & 0x1)
-#define   C_00000D_HDP_MAX_DYN_STOP_LAT                0xFFFFFFEF
-#define   S_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 5)
-#define   G_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) >> 5) & 0x1)
-#define   C_00000D_TV_MAX_DYN_STOP_LAT                 0xFFFFFFDF
-#define   S_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 6)
-#define   G_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) >> 6) & 0x1)
-#define   C_00000D_E2_MAX_DYN_STOP_LAT                 0xFFFFFFBF
-#define   S_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 7)
-#define   G_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) >> 7) & 0x1)
-#define   C_00000D_SE_MAX_DYN_STOP_LAT                 0xFFFFFF7F
-#define   S_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) & 0x1) << 8)
-#define   G_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) >> 8) & 0x1)
-#define   C_00000D_IDCT_MAX_DYN_STOP_LAT               0xFFFFFEFF
-#define   S_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 9)
-#define   G_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) >> 9) & 0x1)
-#define   C_00000D_VIP_MAX_DYN_STOP_LAT                0xFFFFFDFF
-#define   S_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 10)
-#define   G_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) >> 10) & 0x1)
-#define   C_00000D_RE_MAX_DYN_STOP_LAT                 0xFFFFFBFF
-#define   S_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 11)
-#define   G_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) >> 11) & 0x1)
-#define   C_00000D_PB_MAX_DYN_STOP_LAT                 0xFFFFF7FF
-#define   S_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 12)
-#define   G_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) >> 12) & 0x1)
-#define   C_00000D_TAM_MAX_DYN_STOP_LAT                0xFFFFEFFF
-#define   S_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 13)
-#define   G_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) >> 13) & 0x1)
-#define   C_00000D_TDM_MAX_DYN_STOP_LAT                0xFFFFDFFF
-#define   S_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 14)
-#define   G_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) >> 14) & 0x1)
-#define   C_00000D_RB_MAX_DYN_STOP_LAT                 0xFFFFBFFF
-#define   S_00000D_FORCE_DISP2(x)                      (((x) & 0x1) << 15)
-#define   G_00000D_FORCE_DISP2(x)                      (((x) >> 15) & 0x1)
-#define   C_00000D_FORCE_DISP2                         0xFFFF7FFF
-#define   S_00000D_FORCE_CP(x)                         (((x) & 0x1) << 16)
-#define   G_00000D_FORCE_CP(x)                         (((x) >> 16) & 0x1)
-#define   C_00000D_FORCE_CP                            0xFFFEFFFF
-#define   S_00000D_FORCE_HDP(x)                        (((x) & 0x1) << 17)
-#define   G_00000D_FORCE_HDP(x)                        (((x) >> 17) & 0x1)
-#define   C_00000D_FORCE_HDP                           0xFFFDFFFF
-#define   S_00000D_FORCE_DISP1(x)                      (((x) & 0x1) << 18)
-#define   G_00000D_FORCE_DISP1(x)                      (((x) >> 18) & 0x1)
-#define   C_00000D_FORCE_DISP1                         0xFFFBFFFF
-#define   S_00000D_FORCE_TOP(x)                        (((x) & 0x1) << 19)
-#define   G_00000D_FORCE_TOP(x)                        (((x) >> 19) & 0x1)
-#define   C_00000D_FORCE_TOP                           0xFFF7FFFF
-#define   S_00000D_FORCE_E2(x)                         (((x) & 0x1) << 20)
-#define   G_00000D_FORCE_E2(x)                         (((x) >> 20) & 0x1)
-#define   C_00000D_FORCE_E2                            0xFFEFFFFF
-#define   S_00000D_FORCE_VAP(x)                        (((x) & 0x1) << 21)
-#define   G_00000D_FORCE_VAP(x)                        (((x) >> 21) & 0x1)
-#define   C_00000D_FORCE_VAP                           0xFFDFFFFF
-#define   S_00000D_FORCE_IDCT(x)                       (((x) & 0x1) << 22)
-#define   G_00000D_FORCE_IDCT(x)                       (((x) >> 22) & 0x1)
-#define   C_00000D_FORCE_IDCT                          0xFFBFFFFF
-#define   S_00000D_FORCE_VIP(x)                        (((x) & 0x1) << 23)
-#define   G_00000D_FORCE_VIP(x)                        (((x) >> 23) & 0x1)
-#define   C_00000D_FORCE_VIP                           0xFF7FFFFF
-#define   S_00000D_FORCE_RE(x)                         (((x) & 0x1) << 24)
-#define   G_00000D_FORCE_RE(x)                         (((x) >> 24) & 0x1)
-#define   C_00000D_FORCE_RE                            0xFEFFFFFF
-#define   S_00000D_FORCE_SR(x)                         (((x) & 0x1) << 25)
-#define   G_00000D_FORCE_SR(x)                         (((x) >> 25) & 0x1)
-#define   C_00000D_FORCE_SR                            0xFDFFFFFF
-#define   S_00000D_FORCE_PX(x)                         (((x) & 0x1) << 26)
-#define   G_00000D_FORCE_PX(x)                         (((x) >> 26) & 0x1)
-#define   C_00000D_FORCE_PX                            0xFBFFFFFF
-#define   S_00000D_FORCE_TX(x)                         (((x) & 0x1) << 27)
-#define   G_00000D_FORCE_TX(x)                         (((x) >> 27) & 0x1)
-#define   C_00000D_FORCE_TX                            0xF7FFFFFF
-#define   S_00000D_FORCE_US(x)                         (((x) & 0x1) << 28)
-#define   G_00000D_FORCE_US(x)                         (((x) >> 28) & 0x1)
-#define   C_00000D_FORCE_US                            0xEFFFFFFF
-#define   S_00000D_FORCE_TV_SCLK(x)                    (((x) & 0x1) << 29)
-#define   G_00000D_FORCE_TV_SCLK(x)                    (((x) >> 29) & 0x1)
-#define   C_00000D_FORCE_TV_SCLK                       0xDFFFFFFF
-#define   S_00000D_FORCE_SU(x)                         (((x) & 0x1) << 30)
-#define   G_00000D_FORCE_SU(x)                         (((x) >> 30) & 0x1)
-#define   C_00000D_FORCE_SU                            0xBFFFFFFF
-#define   S_00000D_FORCE_OV0(x)                        (((x) & 0x1) << 31)
-#define   G_00000D_FORCE_OV0(x)                        (((x) >> 31) & 0x1)
-#define   C_00000D_FORCE_OV0                           0x7FFFFFFF
-
-#endif
diff --git a/hw/display/r520d.h b/hw/display/r520d.h
deleted file mode 100644
index 61af61f644..0000000000
--- a/hw/display/r520d.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __R520D_H__
-#define __R520D_H__
-
-/* Registers */
-#define R_0000F8_CONFIG_MEMSIZE                      0x0000F8
-#define   S_0000F8_CONFIG_MEMSIZE(x)                   (((x) & 0xFFFFFFFF) << 0)
-#define   G_0000F8_CONFIG_MEMSIZE(x)                   (((x) >> 0) & 0xFFFFFFFF)
-#define   C_0000F8_CONFIG_MEMSIZE                      0x00000000
-#define R_000134_HDP_FB_LOCATION                     0x000134
-#define   S_000134_HDP_FB_START(x)                     (((x) & 0xFFFF) << 0)
-#define   G_000134_HDP_FB_START(x)                     (((x) >> 0) & 0xFFFF)
-#define   C_000134_HDP_FB_START                        0xFFFF0000
-#define R_0007C0_CP_STAT                             0x0007C0
-#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
-#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
-#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
-#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
-#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
-#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
-#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
-#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
-#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
-#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
-#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
-#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
-#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
-#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
-#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
-#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
-#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
-#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
-#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
-#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
-#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
-#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
-#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
-#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
-#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
-#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
-#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
-#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
-#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
-#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
-#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
-#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
-#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
-#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
-#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
-#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
-#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
-#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
-#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
-#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
-#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
-#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
-#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
-#define R_000E40_RBBM_STATUS                         0x000E40
-#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
-#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
-#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
-#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
-#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
-#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
-#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
-#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
-#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
-#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
-#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
-#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
-#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
-#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
-#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
-#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
-#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
-#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
-#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
-#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
-#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
-#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
-#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
-#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
-#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
-#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
-#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
-#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
-#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
-#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
-#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
-#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
-#define   C_000E40_E2_BUSY                             0xFFFDFFFF
-#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
-#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
-#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
-#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
-#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
-#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
-#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
-#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
-#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
-#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
-#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
-#define   C_000E40_RE_BUSY                             0xFFDFFFFF
-#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
-#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
-#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
-#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
-#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
-#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
-#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
-#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
-#define   C_000E40_PB_BUSY                             0xFEFFFFFF
-#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
-#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
-#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
-#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
-#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
-#define   C_000E40_GA_BUSY                             0xFBFFFFFF
-#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
-#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
-#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
-#define   S_000E40_RBBM_HIBUSY(x)                      (((x) & 0x1) << 28)
-#define   G_000E40_RBBM_HIBUSY(x)                      (((x) >> 28) & 0x1)
-#define   C_000E40_RBBM_HIBUSY                         0xEFFFFFFF
-#define   S_000E40_SKID_CFBUSY(x)                      (((x) & 0x1) << 29)
-#define   G_000E40_SKID_CFBUSY(x)                      (((x) >> 29) & 0x1)
-#define   C_000E40_SKID_CFBUSY                         0xDFFFFFFF
-#define   S_000E40_VAP_VF_BUSY(x)                      (((x) & 0x1) << 30)
-#define   G_000E40_VAP_VF_BUSY(x)                      (((x) >> 30) & 0x1)
-#define   C_000E40_VAP_VF_BUSY                         0xBFFFFFFF
-#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
-#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
-#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
-
-
-#define R_000004_MC_FB_LOCATION                      0x000004
-#define   S_000004_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
-#define   G_000004_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
-#define   C_000004_MC_FB_START                         0xFFFF0000
-#define   S_000004_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
-#define   G_000004_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
-#define   C_000004_MC_FB_TOP                           0x0000FFFF
-#define R_000005_MC_AGP_LOCATION                     0x000005
-#define   S_000005_MC_AGP_START(x)                     (((x) & 0xFFFF) << 0)
-#define   G_000005_MC_AGP_START(x)                     (((x) >> 0) & 0xFFFF)
-#define   C_000005_MC_AGP_START                        0xFFFF0000
-#define   S_000005_MC_AGP_TOP(x)                       (((x) & 0xFFFF) << 16)
-#define   G_000005_MC_AGP_TOP(x)                       (((x) >> 16) & 0xFFFF)
-#define   C_000005_MC_AGP_TOP                          0x0000FFFF
-#define R_000006_AGP_BASE                            0x000006
-#define   S_000006_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
-#define   G_000006_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
-#define   C_000006_AGP_BASE_ADDR                       0x00000000
-#define R_000007_AGP_BASE_2                          0x000007
-#define   S_000007_AGP_BASE_ADDR_2(x)                  (((x) & 0xF) << 0)
-#define   G_000007_AGP_BASE_ADDR_2(x)                  (((x) >> 0) & 0xF)
-#define   C_000007_AGP_BASE_ADDR_2                     0xFFFFFFF0
-
-#endif
diff --git a/hw/display/r600_blit_shaders.h b/hw/display/r600_blit_shaders.h
deleted file mode 100644
index f437d36dd9..0000000000
--- a/hw/display/r600_blit_shaders.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2009 Advanced Micro Devices, Inc.
- * Copyright 2009 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef R600_BLIT_SHADERS_H
-#define R600_BLIT_SHADERS_H
-
-extern const u32 r6xx_ps[];
-extern const u32 r6xx_vs[];
-extern const u32 r7xx_default_state[];
-extern const u32 r6xx_default_state[];
-
-
-extern const u32 r6xx_ps_size, r6xx_vs_size;
-extern const u32 r6xx_default_size, r7xx_default_size;
-
-#endif
diff --git a/hw/display/r600_dpm.h b/hw/display/r600_dpm.h
deleted file mode 100644
index 6e4d22ed2a..0000000000
--- a/hw/display/r600_dpm.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __R600_DPM_H__
-#define __R600_DPM_H__
-
-#include "radeon.h"
-
-#define R600_ASI_DFLT                                10000
-#define R600_BSP_DFLT                                0x41EB
-#define R600_BSU_DFLT                                0x2
-#define R600_AH_DFLT                                 5
-#define R600_RLP_DFLT                                25
-#define R600_RMP_DFLT                                65
-#define R600_LHP_DFLT                                40
-#define R600_LMP_DFLT                                15
-#define R600_TD_DFLT                                 0
-#define R600_UTC_DFLT_00                             0x24
-#define R600_UTC_DFLT_01                             0x22
-#define R600_UTC_DFLT_02                             0x22
-#define R600_UTC_DFLT_03                             0x22
-#define R600_UTC_DFLT_04                             0x22
-#define R600_UTC_DFLT_05                             0x22
-#define R600_UTC_DFLT_06                             0x22
-#define R600_UTC_DFLT_07                             0x22
-#define R600_UTC_DFLT_08                             0x22
-#define R600_UTC_DFLT_09                             0x22
-#define R600_UTC_DFLT_10                             0x22
-#define R600_UTC_DFLT_11                             0x22
-#define R600_UTC_DFLT_12                             0x22
-#define R600_UTC_DFLT_13                             0x22
-#define R600_UTC_DFLT_14                             0x22
-#define R600_DTC_DFLT_00                             0x24
-#define R600_DTC_DFLT_01                             0x22
-#define R600_DTC_DFLT_02                             0x22
-#define R600_DTC_DFLT_03                             0x22
-#define R600_DTC_DFLT_04                             0x22
-#define R600_DTC_DFLT_05                             0x22
-#define R600_DTC_DFLT_06                             0x22
-#define R600_DTC_DFLT_07                             0x22
-#define R600_DTC_DFLT_08                             0x22
-#define R600_DTC_DFLT_09                             0x22
-#define R600_DTC_DFLT_10                             0x22
-#define R600_DTC_DFLT_11                             0x22
-#define R600_DTC_DFLT_12                             0x22
-#define R600_DTC_DFLT_13                             0x22
-#define R600_DTC_DFLT_14                             0x22
-#define R600_VRC_DFLT                                0x0000C003
-#define R600_VOLTAGERESPONSETIME_DFLT                1000
-#define R600_BACKBIASRESPONSETIME_DFLT               1000
-#define R600_VRU_DFLT                                0x3
-#define R600_SPLLSTEPTIME_DFLT                       0x1000
-#define R600_SPLLSTEPUNIT_DFLT                       0x3
-#define R600_TPU_DFLT                                0
-#define R600_TPC_DFLT                                0x200
-#define R600_SSTU_DFLT                               0
-#define R600_SST_DFLT                                0x00C8
-#define R600_GICST_DFLT                              0x200
-#define R600_FCT_DFLT                                0x0400
-#define R600_FCTU_DFLT                               0
-#define R600_CTXCGTT3DRPHC_DFLT                      0x20
-#define R600_CTXCGTT3DRSDC_DFLT                      0x40
-#define R600_VDDC3DOORPHC_DFLT                       0x100
-#define R600_VDDC3DOORSDC_DFLT                       0x7
-#define R600_VDDC3DOORSU_DFLT                        0
-#define R600_MPLLLOCKTIME_DFLT                       100
-#define R600_MPLLRESETTIME_DFLT                      150
-#define R600_VCOSTEPPCT_DFLT                          20
-#define R600_ENDINGVCOSTEPPCT_DFLT                    5
-#define R600_REFERENCEDIVIDER_DFLT                    4
-
-#define R600_PM_NUMBER_OF_TC 15
-#define R600_PM_NUMBER_OF_SCLKS 20
-#define R600_PM_NUMBER_OF_MCLKS 4
-#define R600_PM_NUMBER_OF_VOLTAGE_LEVELS 4
-#define R600_PM_NUMBER_OF_ACTIVITY_LEVELS 3
-
-/* XXX are these ok? */
-#define R600_TEMP_RANGE_MIN (90 * 1000)
-#define R600_TEMP_RANGE_MAX (120 * 1000)
-
-#define FDO_PWM_MODE_STATIC  1
-#define FDO_PWM_MODE_STATIC_RPM 5
-
-enum r600_power_level {
-	R600_POWER_LEVEL_LOW = 0,
-	R600_POWER_LEVEL_MEDIUM = 1,
-	R600_POWER_LEVEL_HIGH = 2,
-	R600_POWER_LEVEL_CTXSW = 3,
-};
-
-enum r600_td {
-	R600_TD_AUTO,
-	R600_TD_UP,
-	R600_TD_DOWN,
-};
-
-enum r600_display_watermark {
-	R600_DISPLAY_WATERMARK_LOW = 0,
-	R600_DISPLAY_WATERMARK_HIGH = 1,
-};
-
-enum r600_display_gap
-{
-    R600_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
-    R600_PM_DISPLAY_GAP_VBLANK       = 1,
-    R600_PM_DISPLAY_GAP_WATERMARK    = 2,
-    R600_PM_DISPLAY_GAP_IGNORE       = 3,
-};
-
-extern const u32 r600_utc[R600_PM_NUMBER_OF_TC];
-extern const u32 r600_dtc[R600_PM_NUMBER_OF_TC];
-
-void r600_dpm_print_class_info(u32 class, u32 class2);
-void r600_dpm_print_cap_info(u32 caps);
-void r600_dpm_print_ps_status(struct radeon_device *rdev,
-			      struct radeon_ps *rps);
-u32 r600_dpm_get_vblank_time(struct radeon_device *rdev);
-u32 r600_dpm_get_vrefresh(struct radeon_device *rdev);
-bool r600_is_uvd_state(u32 class, u32 class2);
-void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
-			    u32 *p, u32 *u);
-int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);
-void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable);
-void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable);
-void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable);
-void r600_enable_acpi_pm(struct radeon_device *rdev);
-void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable);
-bool r600_dynamicpm_enabled(struct radeon_device *rdev);
-void r600_enable_sclk_control(struct radeon_device *rdev, bool enable);
-void r600_enable_mclk_control(struct radeon_device *rdev, bool enable);
-void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable);
-void r600_wait_for_spll_change(struct radeon_device *rdev);
-void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p);
-void r600_set_at(struct radeon_device *rdev,
-		 u32 l_to_m, u32 m_to_h,
-		 u32 h_to_m, u32 m_to_l);
-void r600_set_tc(struct radeon_device *rdev, u32 index, u32 u_t, u32 d_t);
-void r600_select_td(struct radeon_device *rdev, enum r600_td td);
-void r600_set_vrc(struct radeon_device *rdev, u32 vrv);
-void r600_set_tpu(struct radeon_device *rdev, u32 u);
-void r600_set_tpc(struct radeon_device *rdev, u32 c);
-void r600_set_sstu(struct radeon_device *rdev, u32 u);
-void r600_set_sst(struct radeon_device *rdev, u32 t);
-void r600_set_git(struct radeon_device *rdev, u32 t);
-void r600_set_fctu(struct radeon_device *rdev, u32 u);
-void r600_set_fct(struct radeon_device *rdev, u32 t);
-void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p);
-void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s);
-void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u);
-void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p);
-void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s);
-void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time);
-void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time);
-void r600_engine_clock_entry_enable(struct radeon_device *rdev,
-				    u32 index, bool enable);
-void r600_engine_clock_entry_enable_pulse_skipping(struct radeon_device *rdev,
-						   u32 index, bool enable);
-void r600_engine_clock_entry_enable_post_divider(struct radeon_device *rdev,
-						 u32 index, bool enable);
-void r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev,
-					      u32 index, u32 divider);
-void r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev,
-						   u32 index, u32 divider);
-void r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev,
-						  u32 index, u32 divider);
-void r600_engine_clock_entry_set_step_time(struct radeon_device *rdev,
-					   u32 index, u32 step_time);
-void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u);
-void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u);
-void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt);
-void r600_voltage_control_enable_pins(struct radeon_device *rdev,
-				      u64 mask);
-void r600_voltage_control_program_voltages(struct radeon_device *rdev,
-					   enum r600_power_level index, u64 pins);
-void r600_voltage_control_deactivate_static_control(struct radeon_device *rdev,
-						    u64 mask);
-void r600_power_level_enable(struct radeon_device *rdev,
-			     enum r600_power_level index, bool enable);
-void r600_power_level_set_voltage_index(struct radeon_device *rdev,
-					enum r600_power_level index, u32 voltage_index);
-void r600_power_level_set_mem_clock_index(struct radeon_device *rdev,
-					  enum r600_power_level index, u32 mem_clock_index);
-void r600_power_level_set_eng_clock_index(struct radeon_device *rdev,
-					  enum r600_power_level index, u32 eng_clock_index);
-void r600_power_level_set_watermark_id(struct radeon_device *rdev,
-				       enum r600_power_level index,
-				       enum r600_display_watermark watermark_id);
-void r600_power_level_set_pcie_gen2(struct radeon_device *rdev,
-				    enum r600_power_level index, bool compatible);
-enum r600_power_level r600_power_level_get_current_index(struct radeon_device *rdev);
-enum r600_power_level r600_power_level_get_target_index(struct radeon_device *rdev);
-void r600_power_level_set_enter_index(struct radeon_device *rdev,
-				      enum r600_power_level index);
-void r600_wait_for_power_level_unequal(struct radeon_device *rdev,
-				       enum r600_power_level index);
-void r600_wait_for_power_level(struct radeon_device *rdev,
-			       enum r600_power_level index);
-void r600_start_dpm(struct radeon_device *rdev);
-void r600_stop_dpm(struct radeon_device *rdev);
-
-bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor);
-
-int r600_get_platform_caps(struct radeon_device *rdev);
-
-int r600_parse_extended_power_table(struct radeon_device *rdev);
-void r600_free_extended_power_table(struct radeon_device *rdev);
-
-enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,
-					       u32 sys_mask,
-					       enum radeon_pcie_gen asic_gen,
-					       enum radeon_pcie_gen default_gen);
-
-u16 r600_get_pcie_lane_support(struct radeon_device *rdev,
-			       u16 asic_lanes,
-			       u16 default_lanes);
-u8 r600_encode_pci_lane_width(u32 lanes);
-
-#endif
diff --git a/hw/display/r600d.h b/hw/display/r600d.h
deleted file mode 100644
index 2e00a5287b..0000000000
--- a/hw/display/r600d.h
+++ /dev/null
@@ -1,2370 +0,0 @@
-/*
- * Copyright 2009 Advanced Micro Devices, Inc.
- * Copyright 2009 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef R600D_H
-#define R600D_H
-
-#define CP_PACKET2			0x80000000
-#define		PACKET2_PAD_SHIFT		0
-#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
-
-#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
-
-#define R6XX_MAX_SH_GPRS			256
-#define R6XX_MAX_TEMP_GPRS			16
-#define R6XX_MAX_SH_THREADS			256
-#define R6XX_MAX_SH_STACK_ENTRIES		4096
-#define R6XX_MAX_BACKENDS			8
-#define R6XX_MAX_BACKENDS_MASK			0xff
-#define R6XX_MAX_SIMDS				8
-#define R6XX_MAX_SIMDS_MASK			0xff
-#define R6XX_MAX_PIPES				8
-#define R6XX_MAX_PIPES_MASK			0xff
-
-/* tiling bits */
-#define     ARRAY_LINEAR_GENERAL              0x00000000
-#define     ARRAY_LINEAR_ALIGNED              0x00000001
-#define     ARRAY_1D_TILED_THIN1              0x00000002
-#define     ARRAY_2D_TILED_THIN1              0x00000004
-
-/* Registers */
-#define	ARB_POP						0x2418
-#define 	ENABLE_TC128					(1 << 30)
-#define	ARB_GDEC_RD_CNTL				0x246C
-
-#define	CC_GC_SHADER_PIPE_CONFIG			0x8950
-#define	CC_RB_BACKEND_DISABLE				0x98F4
-#define		BACKEND_DISABLE(x)				((x) << 16)
-
-#define R_028808_CB_COLOR_CONTROL			0x28808
-#define   S_028808_SPECIAL_OP(x)                       (((x) & 0x7) << 4)
-#define   G_028808_SPECIAL_OP(x)                       (((x) >> 4) & 0x7)
-#define   C_028808_SPECIAL_OP                          0xFFFFFF8F
-#define     V_028808_SPECIAL_NORMAL                     0x00
-#define     V_028808_SPECIAL_DISABLE                    0x01
-#define     V_028808_SPECIAL_RESOLVE_BOX                0x07
-
-#define	CB_COLOR0_BASE					0x28040
-#define	CB_COLOR1_BASE					0x28044
-#define	CB_COLOR2_BASE					0x28048
-#define	CB_COLOR3_BASE					0x2804C
-#define	CB_COLOR4_BASE					0x28050
-#define	CB_COLOR5_BASE					0x28054
-#define	CB_COLOR6_BASE					0x28058
-#define	CB_COLOR7_BASE					0x2805C
-#define	CB_COLOR7_FRAG					0x280FC
-
-#define CB_COLOR0_SIZE                                  0x28060
-#define CB_COLOR0_VIEW                                  0x28080
-#define R_028080_CB_COLOR0_VIEW                      0x028080
-#define   S_028080_SLICE_START(x)                      (((x) & 0x7FF) << 0)
-#define   G_028080_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
-#define   C_028080_SLICE_START                         0xFFFFF800
-#define   S_028080_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
-#define   G_028080_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
-#define   C_028080_SLICE_MAX                           0xFF001FFF
-#define R_028084_CB_COLOR1_VIEW                      0x028084
-#define R_028088_CB_COLOR2_VIEW                      0x028088
-#define R_02808C_CB_COLOR3_VIEW                      0x02808C
-#define R_028090_CB_COLOR4_VIEW                      0x028090
-#define R_028094_CB_COLOR5_VIEW                      0x028094
-#define R_028098_CB_COLOR6_VIEW                      0x028098
-#define R_02809C_CB_COLOR7_VIEW                      0x02809C
-#define R_028100_CB_COLOR0_MASK                      0x028100
-#define   S_028100_CMASK_BLOCK_MAX(x)                  (((x) & 0xFFF) << 0)
-#define   G_028100_CMASK_BLOCK_MAX(x)                  (((x) >> 0) & 0xFFF)
-#define   C_028100_CMASK_BLOCK_MAX                     0xFFFFF000
-#define   S_028100_FMASK_TILE_MAX(x)                   (((x) & 0xFFFFF) << 12)
-#define   G_028100_FMASK_TILE_MAX(x)                   (((x) >> 12) & 0xFFFFF)
-#define   C_028100_FMASK_TILE_MAX                      0x00000FFF
-#define R_028104_CB_COLOR1_MASK                      0x028104
-#define R_028108_CB_COLOR2_MASK                      0x028108
-#define R_02810C_CB_COLOR3_MASK                      0x02810C
-#define R_028110_CB_COLOR4_MASK                      0x028110
-#define R_028114_CB_COLOR5_MASK                      0x028114
-#define R_028118_CB_COLOR6_MASK                      0x028118
-#define R_02811C_CB_COLOR7_MASK                      0x02811C
-#define CB_COLOR0_INFO                                  0x280a0
-#	define CB_FORMAT(x)				((x) << 2)
-#       define CB_ARRAY_MODE(x)                         ((x) << 8)
-#	define CB_SOURCE_FORMAT(x)			((x) << 27)
-#	define CB_SF_EXPORT_FULL			0
-#	define CB_SF_EXPORT_NORM			1
-#define CB_COLOR0_TILE                                  0x280c0
-#define CB_COLOR0_FRAG                                  0x280e0
-#define CB_COLOR0_MASK                                  0x28100
-
-#define SQ_ALU_CONST_CACHE_PS_0				0x28940
-#define SQ_ALU_CONST_CACHE_PS_1				0x28944
-#define SQ_ALU_CONST_CACHE_PS_2				0x28948
-#define SQ_ALU_CONST_CACHE_PS_3				0x2894c
-#define SQ_ALU_CONST_CACHE_PS_4				0x28950
-#define SQ_ALU_CONST_CACHE_PS_5				0x28954
-#define SQ_ALU_CONST_CACHE_PS_6				0x28958
-#define SQ_ALU_CONST_CACHE_PS_7				0x2895c
-#define SQ_ALU_CONST_CACHE_PS_8				0x28960
-#define SQ_ALU_CONST_CACHE_PS_9				0x28964
-#define SQ_ALU_CONST_CACHE_PS_10			0x28968
-#define SQ_ALU_CONST_CACHE_PS_11			0x2896c
-#define SQ_ALU_CONST_CACHE_PS_12			0x28970
-#define SQ_ALU_CONST_CACHE_PS_13			0x28974
-#define SQ_ALU_CONST_CACHE_PS_14			0x28978
-#define SQ_ALU_CONST_CACHE_PS_15			0x2897c
-#define SQ_ALU_CONST_CACHE_VS_0				0x28980
-#define SQ_ALU_CONST_CACHE_VS_1				0x28984
-#define SQ_ALU_CONST_CACHE_VS_2				0x28988
-#define SQ_ALU_CONST_CACHE_VS_3				0x2898c
-#define SQ_ALU_CONST_CACHE_VS_4				0x28990
-#define SQ_ALU_CONST_CACHE_VS_5				0x28994
-#define SQ_ALU_CONST_CACHE_VS_6				0x28998
-#define SQ_ALU_CONST_CACHE_VS_7				0x2899c
-#define SQ_ALU_CONST_CACHE_VS_8				0x289a0
-#define SQ_ALU_CONST_CACHE_VS_9				0x289a4
-#define SQ_ALU_CONST_CACHE_VS_10			0x289a8
-#define SQ_ALU_CONST_CACHE_VS_11			0x289ac
-#define SQ_ALU_CONST_CACHE_VS_12			0x289b0
-#define SQ_ALU_CONST_CACHE_VS_13			0x289b4
-#define SQ_ALU_CONST_CACHE_VS_14			0x289b8
-#define SQ_ALU_CONST_CACHE_VS_15			0x289bc
-#define SQ_ALU_CONST_CACHE_GS_0				0x289c0
-#define SQ_ALU_CONST_CACHE_GS_1				0x289c4
-#define SQ_ALU_CONST_CACHE_GS_2				0x289c8
-#define SQ_ALU_CONST_CACHE_GS_3				0x289cc
-#define SQ_ALU_CONST_CACHE_GS_4				0x289d0
-#define SQ_ALU_CONST_CACHE_GS_5				0x289d4
-#define SQ_ALU_CONST_CACHE_GS_6				0x289d8
-#define SQ_ALU_CONST_CACHE_GS_7				0x289dc
-#define SQ_ALU_CONST_CACHE_GS_8				0x289e0
-#define SQ_ALU_CONST_CACHE_GS_9				0x289e4
-#define SQ_ALU_CONST_CACHE_GS_10			0x289e8
-#define SQ_ALU_CONST_CACHE_GS_11			0x289ec
-#define SQ_ALU_CONST_CACHE_GS_12			0x289f0
-#define SQ_ALU_CONST_CACHE_GS_13			0x289f4
-#define SQ_ALU_CONST_CACHE_GS_14			0x289f8
-#define SQ_ALU_CONST_CACHE_GS_15			0x289fc
-
-#define	CONFIG_MEMSIZE					0x5428
-#define CONFIG_CNTL					0x5424
-#define	CP_STALLED_STAT1			0x8674
-#define	CP_STALLED_STAT2			0x8678
-#define	CP_BUSY_STAT				0x867C
-#define	CP_STAT						0x8680
-#define	CP_COHER_BASE					0x85F8
-#define	CP_DEBUG					0xC1FC
-#define	R_0086D8_CP_ME_CNTL			0x86D8
-#define		S_0086D8_CP_PFP_HALT(x)			(((x) & 1)<<26)
-#define		C_0086D8_CP_PFP_HALT(x)			((x) & 0xFBFFFFFF)
-#define		S_0086D8_CP_ME_HALT(x)			(((x) & 1)<<28)
-#define		C_0086D8_CP_ME_HALT(x)			((x) & 0xEFFFFFFF)
-#define	CP_ME_RAM_DATA					0xC160
-#define	CP_ME_RAM_RADDR					0xC158
-#define	CP_ME_RAM_WADDR					0xC15C
-#define CP_MEQ_THRESHOLDS				0x8764
-#define		MEQ_END(x)					((x) << 16)
-#define		ROQ_END(x)					((x) << 24)
-#define	CP_PERFMON_CNTL					0x87FC
-#define	CP_PFP_UCODE_ADDR				0xC150
-#define	CP_PFP_UCODE_DATA				0xC154
-#define	CP_QUEUE_THRESHOLDS				0x8760
-#define		ROQ_IB1_START(x)				((x) << 0)
-#define		ROQ_IB2_START(x)				((x) << 8)
-#define	CP_RB_BASE					0xC100
-#define	CP_RB_CNTL					0xC104
-#define		RB_BUFSZ(x)					((x) << 0)
-#define		RB_BLKSZ(x)					((x) << 8)
-#define		RB_NO_UPDATE					(1 << 27)
-#define		RB_RPTR_WR_ENA					(1 << 31)
-#define		BUF_SWAP_32BIT					(2 << 16)
-#define	CP_RB_RPTR					0x8700
-#define	CP_RB_RPTR_ADDR					0xC10C
-#define		RB_RPTR_SWAP(x)					((x) << 0)
-#define	CP_RB_RPTR_ADDR_HI				0xC110
-#define	CP_RB_RPTR_WR					0xC108
-#define	CP_RB_WPTR					0xC114
-#define	CP_RB_WPTR_ADDR					0xC118
-#define	CP_RB_WPTR_ADDR_HI				0xC11C
-#define	CP_RB_WPTR_DELAY				0x8704
-#define	CP_ROQ_IB1_STAT					0x8784
-#define	CP_ROQ_IB2_STAT					0x8788
-#define	CP_SEM_WAIT_TIMER				0x85BC
-
-#define	DB_DEBUG					0x9830
-#define		PREZ_MUST_WAIT_FOR_POSTZ_DONE			(1 << 31)
-#define	DB_DEPTH_BASE					0x2800C
-#define	DB_HTILE_DATA_BASE				0x28014
-#define	DB_HTILE_SURFACE				0x28D24
-#define   S_028D24_HTILE_WIDTH(x)                      (((x) & 0x1) << 0)
-#define   G_028D24_HTILE_WIDTH(x)                      (((x) >> 0) & 0x1)
-#define   C_028D24_HTILE_WIDTH                         0xFFFFFFFE
-#define   S_028D24_HTILE_HEIGHT(x)                      (((x) & 0x1) << 1)
-#define   G_028D24_HTILE_HEIGHT(x)                      (((x) >> 1) & 0x1)
-#define   C_028D24_HTILE_HEIGHT                         0xFFFFFFFD
-#define   G_028D24_LINEAR(x)                           (((x) >> 2) & 0x1)
-#define	DB_WATERMARKS					0x9838
-#define		DEPTH_FREE(x)					((x) << 0)
-#define		DEPTH_FLUSH(x)					((x) << 5)
-#define		DEPTH_PENDING_FREE(x)				((x) << 15)
-#define		DEPTH_CACHELINE_FREE(x)				((x) << 20)
-
-#define	DCP_TILING_CONFIG				0x6CA0
-#define		PIPE_TILING(x)					((x) << 1)
-#define 	BANK_TILING(x)					((x) << 4)
-#define		GROUP_SIZE(x)					((x) << 6)
-#define		ROW_TILING(x)					((x) << 8)
-#define		BANK_SWAPS(x)					((x) << 11)
-#define		SAMPLE_SPLIT(x)					((x) << 14)
-#define		BACKEND_MAP(x)					((x) << 16)
-
-#define GB_TILING_CONFIG				0x98F0
-#define     PIPE_TILING__SHIFT              1
-#define     PIPE_TILING__MASK               0x0000000e
-
-#define	GC_USER_SHADER_PIPE_CONFIG			0x8954
-#define		INACTIVE_QD_PIPES(x)				((x) << 8)
-#define		INACTIVE_QD_PIPES_MASK				0x0000FF00
-#define		INACTIVE_SIMDS(x)				((x) << 16)
-#define		INACTIVE_SIMDS_MASK				0x00FF0000
-
-#define SQ_CONFIG                                         0x8c00
-#       define VC_ENABLE                                  (1 << 0)
-#       define EXPORT_SRC_C                               (1 << 1)
-#       define DX9_CONSTS                                 (1 << 2)
-#       define ALU_INST_PREFER_VECTOR                     (1 << 3)
-#       define DX10_CLAMP                                 (1 << 4)
-#       define CLAUSE_SEQ_PRIO(x)                         ((x) << 8)
-#       define PS_PRIO(x)                                 ((x) << 24)
-#       define VS_PRIO(x)                                 ((x) << 26)
-#       define GS_PRIO(x)                                 ((x) << 28)
-#       define ES_PRIO(x)                                 ((x) << 30)
-#define SQ_GPR_RESOURCE_MGMT_1                            0x8c04
-#       define NUM_PS_GPRS(x)                             ((x) << 0)
-#       define NUM_VS_GPRS(x)                             ((x) << 16)
-#       define NUM_CLAUSE_TEMP_GPRS(x)                    ((x) << 28)
-#define SQ_GPR_RESOURCE_MGMT_2                            0x8c08
-#       define NUM_GS_GPRS(x)                             ((x) << 0)
-#       define NUM_ES_GPRS(x)                             ((x) << 16)
-#define SQ_THREAD_RESOURCE_MGMT                           0x8c0c
-#       define NUM_PS_THREADS(x)                          ((x) << 0)
-#       define NUM_VS_THREADS(x)                          ((x) << 8)
-#       define NUM_GS_THREADS(x)                          ((x) << 16)
-#       define NUM_ES_THREADS(x)                          ((x) << 24)
-#define SQ_STACK_RESOURCE_MGMT_1                          0x8c10
-#       define NUM_PS_STACK_ENTRIES(x)                    ((x) << 0)
-#       define NUM_VS_STACK_ENTRIES(x)                    ((x) << 16)
-#define SQ_STACK_RESOURCE_MGMT_2                          0x8c14
-#       define NUM_GS_STACK_ENTRIES(x)                    ((x) << 0)
-#       define NUM_ES_STACK_ENTRIES(x)                    ((x) << 16)
-#define SQ_ESGS_RING_BASE                               0x8c40
-#define SQ_GSVS_RING_BASE                               0x8c48
-#define SQ_ESTMP_RING_BASE                              0x8c50
-#define SQ_GSTMP_RING_BASE                              0x8c58
-#define SQ_VSTMP_RING_BASE                              0x8c60
-#define SQ_PSTMP_RING_BASE                              0x8c68
-#define SQ_FBUF_RING_BASE                               0x8c70
-#define SQ_REDUC_RING_BASE                              0x8c78
-
-#define GRBM_CNTL                                       0x8000
-#       define GRBM_READ_TIMEOUT(x)                     ((x) << 0)
-#define	GRBM_STATUS					0x8010
-#define		CMDFIFO_AVAIL_MASK				0x0000001F
-#define		GUI_ACTIVE					(1<<31)
-#define	GRBM_STATUS2					0x8014
-#define	GRBM_SOFT_RESET					0x8020
-#define		SOFT_RESET_CP					(1<<0)
-
-#define	CG_THERMAL_CTRL					0x7F0
-#define		DIG_THERM_DPM(x)			((x) << 12)
-#define		DIG_THERM_DPM_MASK			0x000FF000
-#define		DIG_THERM_DPM_SHIFT			12
-#define	CG_THERMAL_STATUS				0x7F4
-#define		ASIC_T(x)			        ((x) << 0)
-#define		ASIC_T_MASK			        0x1FF
-#define		ASIC_T_SHIFT			        0
-#define	CG_THERMAL_INT					0x7F8
-#define		DIG_THERM_INTH(x)			((x) << 8)
-#define		DIG_THERM_INTH_MASK			0x0000FF00
-#define		DIG_THERM_INTH_SHIFT			8
-#define		DIG_THERM_INTL(x)			((x) << 16)
-#define		DIG_THERM_INTL_MASK			0x00FF0000
-#define		DIG_THERM_INTL_SHIFT			16
-#define 	THERM_INT_MASK_HIGH			(1 << 24)
-#define 	THERM_INT_MASK_LOW			(1 << 25)
-
-#define	RV770_CG_THERMAL_INT				0x734
-
-#define	HDP_HOST_PATH_CNTL				0x2C00
-#define	HDP_NONSURFACE_BASE				0x2C04
-#define	HDP_NONSURFACE_INFO				0x2C08
-#define	HDP_NONSURFACE_SIZE				0x2C0C
-#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0
-#define	HDP_TILING_CONFIG				0x2F3C
-#define HDP_DEBUG1                                      0x2F34
-
-#define MC_CONFIG					0x2000
-#define MC_VM_AGP_TOP					0x2184
-#define MC_VM_AGP_BOT					0x2188
-#define	MC_VM_AGP_BASE					0x218C
-#define MC_VM_FB_LOCATION				0x2180
-#define MC_VM_L1_TLB_MCB_RD_UVD_CNTL			0x2124
-#define 	ENABLE_L1_TLB					(1 << 0)
-#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)
-#define		ENABLE_L1_STRICT_ORDERING			(1 << 2)
-#define		SYSTEM_ACCESS_MODE_MASK				0x000000C0
-#define		SYSTEM_ACCESS_MODE_SHIFT			6
-#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 6)
-#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 6)
-#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 6)
-#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 6)
-#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 8)
-#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE	(1 << 8)
-#define		ENABLE_SEMAPHORE_MODE				(1 << 10)
-#define		ENABLE_WAIT_L2_QUERY				(1 << 11)
-#define		EFFECTIVE_L1_TLB_SIZE(x)			(((x) & 7) << 12)
-#define		EFFECTIVE_L1_TLB_SIZE_MASK			0x00007000
-#define		EFFECTIVE_L1_TLB_SIZE_SHIFT			12
-#define		EFFECTIVE_L1_QUEUE_SIZE(x)			(((x) & 7) << 15)
-#define		EFFECTIVE_L1_QUEUE_SIZE_MASK			0x00038000
-#define		EFFECTIVE_L1_QUEUE_SIZE_SHIFT			15
-#define MC_VM_L1_TLB_MCD_RD_A_CNTL			0x219C
-#define MC_VM_L1_TLB_MCD_RD_B_CNTL			0x21A0
-#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL			0x21FC
-#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL			0x2204
-#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL			0x2208
-#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL			0x220C
-#define	MC_VM_L1_TLB_MCB_RD_SYS_CNTL			0x2200
-#define MC_VM_L1_TLB_MCB_WR_UVD_CNTL			0x212c
-#define MC_VM_L1_TLB_MCD_WR_A_CNTL			0x21A4
-#define MC_VM_L1_TLB_MCD_WR_B_CNTL			0x21A8
-#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL			0x2210
-#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL			0x2218
-#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL			0x221C
-#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL			0x2220
-#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL			0x2214
-#define MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2190
-#define		LOGICAL_PAGE_NUMBER_MASK			0x000FFFFF
-#define		LOGICAL_PAGE_NUMBER_SHIFT			0
-#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2194
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x2198
-
-#define RS_DQ_RD_RET_CONF				0x2348
-
-#define	PA_CL_ENHANCE					0x8A14
-#define		CLIP_VTX_REORDER_ENA				(1 << 0)
-#define		NUM_CLIP_SEQ(x)					((x) << 1)
-#define PA_SC_AA_CONFIG					0x28C04
-#define	PA_SC_AA_SAMPLE_LOCS_2S				0x8B40
-#define	PA_SC_AA_SAMPLE_LOCS_4S				0x8B44
-#define	PA_SC_AA_SAMPLE_LOCS_8S_WD0			0x8B48
-#define	PA_SC_AA_SAMPLE_LOCS_8S_WD1			0x8B4C
-#define		S0_X(x)						((x) << 0)
-#define		S0_Y(x)						((x) << 4)
-#define		S1_X(x)						((x) << 8)
-#define		S1_Y(x)						((x) << 12)
-#define		S2_X(x)						((x) << 16)
-#define		S2_Y(x)						((x) << 20)
-#define		S3_X(x)						((x) << 24)
-#define		S3_Y(x)						((x) << 28)
-#define		S4_X(x)						((x) << 0)
-#define		S4_Y(x)						((x) << 4)
-#define		S5_X(x)						((x) << 8)
-#define		S5_Y(x)						((x) << 12)
-#define		S6_X(x)						((x) << 16)
-#define		S6_Y(x)						((x) << 20)
-#define		S7_X(x)						((x) << 24)
-#define		S7_Y(x)						((x) << 28)
-#define PA_SC_CLIPRECT_RULE				0x2820c
-#define	PA_SC_ENHANCE					0x8BF0
-#define		FORCE_EOV_MAX_CLK_CNT(x)			((x) << 0)
-#define		FORCE_EOV_MAX_TILE_CNT(x)			((x) << 12)
-#define PA_SC_LINE_STIPPLE				0x28A0C
-#define	PA_SC_LINE_STIPPLE_STATE			0x8B10
-#define PA_SC_MODE_CNTL					0x28A4C
-#define	PA_SC_MULTI_CHIP_CNTL				0x8B20
-
-#define PA_SC_SCREEN_SCISSOR_TL                         0x28030
-#define PA_SC_GENERIC_SCISSOR_TL                        0x28240
-#define PA_SC_WINDOW_SCISSOR_TL                         0x28204
-
-#define	PCIE_PORT_INDEX					0x0038
-#define	PCIE_PORT_DATA					0x003C
-
-#define CHMAP						0x2004
-#define		NOOFCHAN_SHIFT					12
-#define		NOOFCHAN_MASK					0x00003000
-
-#define RAMCFG						0x2408
-#define		NOOFBANK_SHIFT					0
-#define		NOOFBANK_MASK					0x00000001
-#define		NOOFRANK_SHIFT					1
-#define		NOOFRANK_MASK					0x00000002
-#define		NOOFROWS_SHIFT					2
-#define		NOOFROWS_MASK					0x0000001C
-#define		NOOFCOLS_SHIFT					5
-#define		NOOFCOLS_MASK					0x00000060
-#define		CHANSIZE_SHIFT					7
-#define		CHANSIZE_MASK					0x00000080
-#define		BURSTLENGTH_SHIFT				8
-#define		BURSTLENGTH_MASK				0x00000100
-#define		CHANSIZE_OVERRIDE				(1 << 10)
-
-#define	SCRATCH_REG0					0x8500
-#define	SCRATCH_REG1					0x8504
-#define	SCRATCH_REG2					0x8508
-#define	SCRATCH_REG3					0x850C
-#define	SCRATCH_REG4					0x8510
-#define	SCRATCH_REG5					0x8514
-#define	SCRATCH_REG6					0x8518
-#define	SCRATCH_REG7					0x851C
-#define	SCRATCH_UMSK					0x8540
-#define	SCRATCH_ADDR					0x8544
-
-#define	SPI_CONFIG_CNTL					0x9100
-#define		GPR_WRITE_PRIORITY(x)				((x) << 0)
-#define		DISABLE_INTERP_1				(1 << 5)
-#define	SPI_CONFIG_CNTL_1				0x913C
-#define		VTX_DONE_DELAY(x)				((x) << 0)
-#define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)
-#define	SPI_INPUT_Z					0x286D8
-#define	SPI_PS_IN_CONTROL_0				0x286CC
-#define		NUM_INTERP(x)					((x)<<0)
-#define		POSITION_ENA					(1<<8)
-#define		POSITION_CENTROID				(1<<9)
-#define		POSITION_ADDR(x)				((x)<<10)
-#define		PARAM_GEN(x)					((x)<<15)
-#define		PARAM_GEN_ADDR(x)				((x)<<19)
-#define		BARYC_SAMPLE_CNTL(x)				((x)<<26)
-#define		PERSP_GRADIENT_ENA				(1<<28)
-#define		LINEAR_GRADIENT_ENA				(1<<29)
-#define		POSITION_SAMPLE					(1<<30)
-#define		BARYC_AT_SAMPLE_ENA				(1<<31)
-#define	SPI_PS_IN_CONTROL_1				0x286D0
-#define		GEN_INDEX_PIX					(1<<0)
-#define		GEN_INDEX_PIX_ADDR(x)				((x)<<1)
-#define		FRONT_FACE_ENA					(1<<8)
-#define		FRONT_FACE_CHAN(x)				((x)<<9)
-#define		FRONT_FACE_ALL_BITS				(1<<11)
-#define		FRONT_FACE_ADDR(x)				((x)<<12)
-#define		FOG_ADDR(x)					((x)<<17)
-#define		FIXED_PT_POSITION_ENA				(1<<24)
-#define		FIXED_PT_POSITION_ADDR(x)			((x)<<25)
-
-#define	SQ_MS_FIFO_SIZES				0x8CF0
-#define		CACHE_FIFO_SIZE(x)				((x) << 0)
-#define		FETCH_FIFO_HIWATER(x)				((x) << 8)
-#define		DONE_FIFO_HIWATER(x)				((x) << 16)
-#define		ALU_UPDATE_FIFO_HIWATER(x)			((x) << 24)
-#define	SQ_PGM_START_ES					0x28880
-#define	SQ_PGM_START_FS					0x28894
-#define	SQ_PGM_START_GS					0x2886C
-#define	SQ_PGM_START_PS					0x28840
-#define SQ_PGM_RESOURCES_PS                             0x28850
-#define SQ_PGM_EXPORTS_PS                               0x28854
-#define SQ_PGM_CF_OFFSET_PS                             0x288cc
-#define	SQ_PGM_START_VS					0x28858
-#define SQ_PGM_RESOURCES_VS                             0x28868
-#define SQ_PGM_CF_OFFSET_VS                             0x288d0
-
-#define SQ_VTX_CONSTANT_WORD0_0				0x30000
-#define SQ_VTX_CONSTANT_WORD1_0				0x30004
-#define SQ_VTX_CONSTANT_WORD2_0				0x30008
-#	define SQ_VTXC_BASE_ADDR_HI(x)			((x) << 0)
-#	define SQ_VTXC_STRIDE(x)			((x) << 8)
-#	define SQ_VTXC_ENDIAN_SWAP(x)			((x) << 30)
-#	define SQ_ENDIAN_NONE				0
-#	define SQ_ENDIAN_8IN16				1
-#	define SQ_ENDIAN_8IN32				2
-#define SQ_VTX_CONSTANT_WORD3_0				0x3000c
-#define	SQ_VTX_CONSTANT_WORD6_0				0x38018
-#define		S__SQ_VTX_CONSTANT_TYPE(x)			(((x) & 3) << 30)
-#define		G__SQ_VTX_CONSTANT_TYPE(x)			(((x) >> 30) & 3)
-#define			SQ_TEX_VTX_INVALID_TEXTURE			0x0
-#define			SQ_TEX_VTX_INVALID_BUFFER			0x1
-#define			SQ_TEX_VTX_VALID_TEXTURE			0x2
-#define			SQ_TEX_VTX_VALID_BUFFER				0x3
-
-
-#define	SX_MISC						0x28350
-#define	SX_MEMORY_EXPORT_BASE				0x9010
-#define	SX_DEBUG_1					0x9054
-#define		SMX_EVENT_RELEASE				(1 << 0)
-#define		ENABLE_NEW_SMX_ADDRESS				(1 << 16)
-
-#define	TA_CNTL_AUX					0x9508
-#define		DISABLE_CUBE_WRAP				(1 << 0)
-#define		DISABLE_CUBE_ANISO				(1 << 1)
-#define		SYNC_GRADIENT					(1 << 24)
-#define		SYNC_WALKER					(1 << 25)
-#define		SYNC_ALIGNER					(1 << 26)
-#define		BILINEAR_PRECISION_6_BIT			(0 << 31)
-#define		BILINEAR_PRECISION_8_BIT			(1 << 31)
-
-#define	TC_CNTL						0x9608
-#define		TC_L2_SIZE(x)					((x)<<5)
-#define		L2_DISABLE_LATE_HIT				(1<<9)
-
-#define	VC_ENHANCE					0x9714
-
-#define	VGT_CACHE_INVALIDATION				0x88C4
-#define		CACHE_INVALIDATION(x)				((x)<<0)
-#define			VC_ONLY						0
-#define			TC_ONLY						1
-#define			VC_AND_TC					2
-#define	VGT_DMA_BASE					0x287E8
-#define	VGT_DMA_BASE_HI					0x287E4
-#define	VGT_ES_PER_GS					0x88CC
-#define	VGT_GS_PER_ES					0x88C8
-#define	VGT_GS_PER_VS					0x88E8
-#define	VGT_GS_VERTEX_REUSE				0x88D4
-#define VGT_PRIMITIVE_TYPE                              0x8958
-#define	VGT_NUM_INSTANCES				0x8974
-#define	VGT_OUT_DEALLOC_CNTL				0x28C5C
-#define		DEALLOC_DIST_MASK				0x0000007F
-#define	VGT_STRMOUT_BASE_OFFSET_0			0x28B10
-#define	VGT_STRMOUT_BASE_OFFSET_1			0x28B14
-#define	VGT_STRMOUT_BASE_OFFSET_2			0x28B18
-#define	VGT_STRMOUT_BASE_OFFSET_3			0x28B1c
-#define	VGT_STRMOUT_BASE_OFFSET_HI_0			0x28B44
-#define	VGT_STRMOUT_BASE_OFFSET_HI_1			0x28B48
-#define	VGT_STRMOUT_BASE_OFFSET_HI_2			0x28B4c
-#define	VGT_STRMOUT_BASE_OFFSET_HI_3			0x28B50
-#define	VGT_STRMOUT_BUFFER_BASE_0			0x28AD8
-#define	VGT_STRMOUT_BUFFER_BASE_1			0x28AE8
-#define	VGT_STRMOUT_BUFFER_BASE_2			0x28AF8
-#define	VGT_STRMOUT_BUFFER_BASE_3			0x28B08
-#define	VGT_STRMOUT_BUFFER_OFFSET_0			0x28ADC
-#define	VGT_STRMOUT_BUFFER_OFFSET_1			0x28AEC
-#define	VGT_STRMOUT_BUFFER_OFFSET_2			0x28AFC
-#define	VGT_STRMOUT_BUFFER_OFFSET_3			0x28B0C
-#define VGT_STRMOUT_BUFFER_SIZE_0			0x28AD0
-#define VGT_STRMOUT_BUFFER_SIZE_1			0x28AE0
-#define VGT_STRMOUT_BUFFER_SIZE_2			0x28AF0
-#define VGT_STRMOUT_BUFFER_SIZE_3			0x28B00
-
-#define	VGT_STRMOUT_EN					0x28AB0
-#define	VGT_VERTEX_REUSE_BLOCK_CNTL			0x28C58
-#define		VTX_REUSE_DEPTH_MASK				0x000000FF
-#define VGT_EVENT_INITIATOR                             0x28a90
-#       define CACHE_FLUSH_AND_INV_EVENT_TS                     (0x14 << 0)
-#       define CACHE_FLUSH_AND_INV_EVENT                        (0x16 << 0)
-
-#define VM_CONTEXT0_CNTL				0x1410
-#define		ENABLE_CONTEXT					(1 << 0)
-#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
-#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
-#define VM_CONTEXT0_INVALIDATION_LOW_ADDR		0x1490
-#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR		0x14B0
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x1574
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x1594
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x15B4
-#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x1554
-#define VM_CONTEXT0_REQUEST_RESPONSE			0x1470
-#define		REQUEST_TYPE(x)					(((x) & 0xf) << 0)
-#define		RESPONSE_TYPE_MASK				0x000000F0
-#define		RESPONSE_TYPE_SHIFT				4
-#define VM_L2_CNTL					0x1400
-#define		ENABLE_L2_CACHE					(1 << 0)
-#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
-#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)
-#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 13)
-#define VM_L2_CNTL2					0x1404
-#define		INVALIDATE_ALL_L1_TLBS				(1 << 0)
-#define		INVALIDATE_L2_CACHE				(1 << 1)
-#define VM_L2_CNTL3					0x1408
-#define		BANK_SELECT_0(x)				(((x) & 0x1f) << 0)
-#define		BANK_SELECT_1(x)				(((x) & 0x1f) << 5)
-#define		L2_CACHE_UPDATE_MODE(x)				(((x) & 3) << 10)
-#define	VM_L2_STATUS					0x140C
-#define		L2_BUSY						(1 << 0)
-
-#define	WAIT_UNTIL					0x8040
-#define         WAIT_CP_DMA_IDLE_bit                            (1 << 8)
-#define         WAIT_2D_IDLE_bit                                (1 << 14)
-#define         WAIT_3D_IDLE_bit                                (1 << 15)
-#define         WAIT_2D_IDLECLEAN_bit                           (1 << 16)
-#define         WAIT_3D_IDLECLEAN_bit                           (1 << 17)
-
-/* async DMA */
-#define DMA_TILING_CONFIG                                 0x3ec4
-#define DMA_CONFIG                                        0x3e4c
-
-#define DMA_RB_CNTL                                       0xd000
-#       define DMA_RB_ENABLE                              (1 << 0)
-#       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */
-#       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */
-#       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)
-#       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */
-#       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */
-#define DMA_RB_BASE                                       0xd004
-#define DMA_RB_RPTR                                       0xd008
-#define DMA_RB_WPTR                                       0xd00c
-
-#define DMA_RB_RPTR_ADDR_HI                               0xd01c
-#define DMA_RB_RPTR_ADDR_LO                               0xd020
-
-#define DMA_IB_CNTL                                       0xd024
-#       define DMA_IB_ENABLE                              (1 << 0)
-#       define DMA_IB_SWAP_ENABLE                         (1 << 4)
-#define DMA_IB_RPTR                                       0xd028
-#define DMA_CNTL                                          0xd02c
-#       define TRAP_ENABLE                                (1 << 0)
-#       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)
-#       define SEM_WAIT_INT_ENABLE                        (1 << 2)
-#       define DATA_SWAP_ENABLE                           (1 << 3)
-#       define FENCE_SWAP_ENABLE                          (1 << 4)
-#       define CTXEMPTY_INT_ENABLE                        (1 << 28)
-#define DMA_STATUS_REG                                    0xd034
-#       define DMA_IDLE                                   (1 << 0)
-#define DMA_SEM_INCOMPLETE_TIMER_CNTL                     0xd044
-#define DMA_SEM_WAIT_FAIL_TIMER_CNTL                      0xd048
-#define DMA_MODE                                          0xd0bc
-
-/* async DMA packets */
-#define DMA_PACKET(cmd, t, s, n)	((((cmd) & 0xF) << 28) |	\
-					 (((t) & 0x1) << 23) |		\
-					 (((s) & 0x1) << 22) |		\
-					 (((n) & 0xFFFF) << 0))
-/* async DMA Packet types */
-#define	DMA_PACKET_WRITE				  0x2
-#define	DMA_PACKET_COPY					  0x3
-#define	DMA_PACKET_INDIRECT_BUFFER			  0x4
-#define	DMA_PACKET_SEMAPHORE				  0x5
-#define	DMA_PACKET_FENCE				  0x6
-#define	DMA_PACKET_TRAP					  0x7
-#define	DMA_PACKET_CONSTANT_FILL			  0xd /* 7xx only */
-#define	DMA_PACKET_NOP					  0xf
-
-#define IH_RB_CNTL                                        0x3e00
-#       define IH_RB_ENABLE                               (1 << 0)
-#       define IH_RB_SIZE(x)                              ((x) << 1) /* log2 */
-#       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
-#       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
-#       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
-#       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
-#       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)
-#define IH_RB_BASE                                        0x3e04
-#define IH_RB_RPTR                                        0x3e08
-#define IH_RB_WPTR                                        0x3e0c
-#       define RB_OVERFLOW                                (1 << 0)
-#       define WPTR_OFFSET_MASK                           0x3fffc
-#define IH_RB_WPTR_ADDR_HI                                0x3e10
-#define IH_RB_WPTR_ADDR_LO                                0x3e14
-#define IH_CNTL                                           0x3e18
-#       define ENABLE_INTR                                (1 << 0)
-#       define IH_MC_SWAP(x)                              ((x) << 1)
-#       define IH_MC_SWAP_NONE                            0
-#       define IH_MC_SWAP_16BIT                           1
-#       define IH_MC_SWAP_32BIT                           2
-#       define IH_MC_SWAP_64BIT                           3
-#       define RPTR_REARM                                 (1 << 4)
-#       define MC_WRREQ_CREDIT(x)                         ((x) << 15)
-#       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)
-
-#define RLC_CNTL                                          0x3f00
-#       define RLC_ENABLE                                 (1 << 0)
-#define RLC_HB_BASE                                       0x3f10
-#define RLC_HB_CNTL                                       0x3f0c
-#define RLC_HB_RPTR                                       0x3f20
-#define RLC_HB_WPTR                                       0x3f1c
-#define RLC_HB_WPTR_LSB_ADDR                              0x3f14
-#define RLC_HB_WPTR_MSB_ADDR                              0x3f18
-#define RLC_GPU_CLOCK_COUNT_LSB				  0x3f38
-#define RLC_GPU_CLOCK_COUNT_MSB				  0x3f3c
-#define RLC_CAPTURE_GPU_CLOCK_COUNT			  0x3f40
-#define RLC_MC_CNTL                                       0x3f44
-#define RLC_UCODE_CNTL                                    0x3f48
-#define RLC_UCODE_ADDR                                    0x3f2c
-#define RLC_UCODE_DATA                                    0x3f30
-
-#define SRBM_SOFT_RESET                                   0xe60
-#       define SOFT_RESET_BIF                             (1 << 1)
-#       define SOFT_RESET_DMA                             (1 << 12)
-#       define SOFT_RESET_RLC                             (1 << 13)
-#       define SOFT_RESET_UVD                             (1 << 18)
-#       define RV770_SOFT_RESET_DMA                       (1 << 20)
-
-#define BIF_SCRATCH0                                      0x5438
-
-#define BUS_CNTL                                          0x5420
-#       define BIOS_ROM_DIS                               (1 << 1)
-#       define VGA_COHE_SPEC_TIMER_DIS                    (1 << 9)
-
-#define CP_INT_CNTL                                       0xc124
-#       define CNTX_BUSY_INT_ENABLE                       (1 << 19)
-#       define CNTX_EMPTY_INT_ENABLE                      (1 << 20)
-#       define SCRATCH_INT_ENABLE                         (1 << 25)
-#       define TIME_STAMP_INT_ENABLE                      (1 << 26)
-#       define IB2_INT_ENABLE                             (1 << 29)
-#       define IB1_INT_ENABLE                             (1 << 30)
-#       define RB_INT_ENABLE                              (1 << 31)
-#define CP_INT_STATUS                                     0xc128
-#       define SCRATCH_INT_STAT                           (1 << 25)
-#       define TIME_STAMP_INT_STAT                        (1 << 26)
-#       define IB2_INT_STAT                               (1 << 29)
-#       define IB1_INT_STAT                               (1 << 30)
-#       define RB_INT_STAT                                (1 << 31)
-
-#define GRBM_INT_CNTL                                     0x8060
-#       define RDERR_INT_ENABLE                           (1 << 0)
-#       define WAIT_COUNT_TIMEOUT_INT_ENABLE              (1 << 1)
-#       define GUI_IDLE_INT_ENABLE                        (1 << 19)
-
-#define INTERRUPT_CNTL                                    0x5468
-#       define IH_DUMMY_RD_OVERRIDE                       (1 << 0)
-#       define IH_DUMMY_RD_EN                             (1 << 1)
-#       define IH_REQ_NONSNOOP_EN                         (1 << 3)
-#       define GEN_IH_INT_EN                              (1 << 8)
-#define INTERRUPT_CNTL2                                   0x546c
-
-#define D1MODE_VBLANK_STATUS                              0x6534
-#define D2MODE_VBLANK_STATUS                              0x6d34
-#       define DxMODE_VBLANK_OCCURRED                     (1 << 0)
-#       define DxMODE_VBLANK_ACK                          (1 << 4)
-#       define DxMODE_VBLANK_STAT                         (1 << 12)
-#       define DxMODE_VBLANK_INTERRUPT                    (1 << 16)
-#       define DxMODE_VBLANK_INTERRUPT_TYPE               (1 << 17)
-#define D1MODE_VLINE_STATUS                               0x653c
-#define D2MODE_VLINE_STATUS                               0x6d3c
-#       define DxMODE_VLINE_OCCURRED                      (1 << 0)
-#       define DxMODE_VLINE_ACK                           (1 << 4)
-#       define DxMODE_VLINE_STAT                          (1 << 12)
-#       define DxMODE_VLINE_INTERRUPT                     (1 << 16)
-#       define DxMODE_VLINE_INTERRUPT_TYPE                (1 << 17)
-#define DxMODE_INT_MASK                                   0x6540
-#       define D1MODE_VBLANK_INT_MASK                     (1 << 0)
-#       define D1MODE_VLINE_INT_MASK                      (1 << 4)
-#       define D2MODE_VBLANK_INT_MASK                     (1 << 8)
-#       define D2MODE_VLINE_INT_MASK                      (1 << 12)
-#define DCE3_DISP_INTERRUPT_STATUS                        0x7ddc
-#       define DC_HPD1_INTERRUPT                          (1 << 18)
-#       define DC_HPD2_INTERRUPT                          (1 << 19)
-#define DISP_INTERRUPT_STATUS                             0x7edc
-#       define LB_D1_VLINE_INTERRUPT                      (1 << 2)
-#       define LB_D2_VLINE_INTERRUPT                      (1 << 3)
-#       define LB_D1_VBLANK_INTERRUPT                     (1 << 4)
-#       define LB_D2_VBLANK_INTERRUPT                     (1 << 5)
-#       define DACA_AUTODETECT_INTERRUPT                  (1 << 16)
-#       define DACB_AUTODETECT_INTERRUPT                  (1 << 17)
-#       define DC_HOT_PLUG_DETECT1_INTERRUPT              (1 << 18)
-#       define DC_HOT_PLUG_DETECT2_INTERRUPT              (1 << 19)
-#       define DC_I2C_SW_DONE_INTERRUPT                   (1 << 20)
-#       define DC_I2C_HW_DONE_INTERRUPT                   (1 << 21)
-#define DISP_INTERRUPT_STATUS_CONTINUE                    0x7ee8
-#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE               0x7de8
-#       define DC_HPD4_INTERRUPT                          (1 << 14)
-#       define DC_HPD4_RX_INTERRUPT                       (1 << 15)
-#       define DC_HPD3_INTERRUPT                          (1 << 28)
-#       define DC_HPD1_RX_INTERRUPT                       (1 << 29)
-#       define DC_HPD2_RX_INTERRUPT                       (1 << 30)
-#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2              0x7dec
-#       define DC_HPD3_RX_INTERRUPT                       (1 << 0)
-#       define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT       (1 << 1)
-#       define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT      (1 << 2)
-#       define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT       (1 << 3)
-#       define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT      (1 << 4)
-#       define AUX1_SW_DONE_INTERRUPT                     (1 << 5)
-#       define AUX1_LS_DONE_INTERRUPT                     (1 << 6)
-#       define AUX2_SW_DONE_INTERRUPT                     (1 << 7)
-#       define AUX2_LS_DONE_INTERRUPT                     (1 << 8)
-#       define AUX3_SW_DONE_INTERRUPT                     (1 << 9)
-#       define AUX3_LS_DONE_INTERRUPT                     (1 << 10)
-#       define AUX4_SW_DONE_INTERRUPT                     (1 << 11)
-#       define AUX4_LS_DONE_INTERRUPT                     (1 << 12)
-#       define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT   (1 << 13)
-#       define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT   (1 << 14)
-/* DCE 3.2 */
-#       define AUX5_SW_DONE_INTERRUPT                     (1 << 15)
-#       define AUX5_LS_DONE_INTERRUPT                     (1 << 16)
-#       define AUX6_SW_DONE_INTERRUPT                     (1 << 17)
-#       define AUX6_LS_DONE_INTERRUPT                     (1 << 18)
-#       define DC_HPD5_INTERRUPT                          (1 << 19)
-#       define DC_HPD5_RX_INTERRUPT                       (1 << 20)
-#       define DC_HPD6_INTERRUPT                          (1 << 21)
-#       define DC_HPD6_RX_INTERRUPT                       (1 << 22)
-
-#define DACA_AUTO_DETECT_CONTROL                          0x7828
-#define DACB_AUTO_DETECT_CONTROL                          0x7a28
-#define DCE3_DACA_AUTO_DETECT_CONTROL                     0x7028
-#define DCE3_DACB_AUTO_DETECT_CONTROL                     0x7128
-#       define DACx_AUTODETECT_MODE(x)                    ((x) << 0)
-#       define DACx_AUTODETECT_MODE_NONE                  0
-#       define DACx_AUTODETECT_MODE_CONNECT               1
-#       define DACx_AUTODETECT_MODE_DISCONNECT            2
-#       define DACx_AUTODETECT_FRAME_TIME_COUNTER(x)      ((x) << 8)
-/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */
-#       define DACx_AUTODETECT_CHECK_MASK(x)              ((x) << 16)
-
-#define DCE3_DACA_AUTODETECT_INT_CONTROL                  0x7038
-#define DCE3_DACB_AUTODETECT_INT_CONTROL                  0x7138
-#define DACA_AUTODETECT_INT_CONTROL                       0x7838
-#define DACB_AUTODETECT_INT_CONTROL                       0x7a38
-#       define DACx_AUTODETECT_ACK                        (1 << 0)
-#       define DACx_AUTODETECT_INT_ENABLE                 (1 << 16)
-
-#define DC_HOT_PLUG_DETECT1_CONTROL                       0x7d00
-#define DC_HOT_PLUG_DETECT2_CONTROL                       0x7d10
-#define DC_HOT_PLUG_DETECT3_CONTROL                       0x7d24
-#       define DC_HOT_PLUG_DETECTx_EN                     (1 << 0)
-
-#define DC_HOT_PLUG_DETECT1_INT_STATUS                    0x7d04
-#define DC_HOT_PLUG_DETECT2_INT_STATUS                    0x7d14
-#define DC_HOT_PLUG_DETECT3_INT_STATUS                    0x7d28
-#       define DC_HOT_PLUG_DETECTx_INT_STATUS             (1 << 0)
-#       define DC_HOT_PLUG_DETECTx_SENSE                  (1 << 1)
-
-/* DCE 3.0 */
-#define DC_HPD1_INT_STATUS                                0x7d00
-#define DC_HPD2_INT_STATUS                                0x7d0c
-#define DC_HPD3_INT_STATUS                                0x7d18
-#define DC_HPD4_INT_STATUS                                0x7d24
-/* DCE 3.2 */
-#define DC_HPD5_INT_STATUS                                0x7dc0
-#define DC_HPD6_INT_STATUS                                0x7df4
-#       define DC_HPDx_INT_STATUS                         (1 << 0)
-#       define DC_HPDx_SENSE                              (1 << 1)
-#       define DC_HPDx_RX_INT_STATUS                      (1 << 8)
-
-#define DC_HOT_PLUG_DETECT1_INT_CONTROL                   0x7d08
-#define DC_HOT_PLUG_DETECT2_INT_CONTROL                   0x7d18
-#define DC_HOT_PLUG_DETECT3_INT_CONTROL                   0x7d2c
-#       define DC_HOT_PLUG_DETECTx_INT_ACK                (1 << 0)
-#       define DC_HOT_PLUG_DETECTx_INT_POLARITY           (1 << 8)
-#       define DC_HOT_PLUG_DETECTx_INT_EN                 (1 << 16)
-/* DCE 3.0 */
-#define DC_HPD1_INT_CONTROL                               0x7d04
-#define DC_HPD2_INT_CONTROL                               0x7d10
-#define DC_HPD3_INT_CONTROL                               0x7d1c
-#define DC_HPD4_INT_CONTROL                               0x7d28
-/* DCE 3.2 */
-#define DC_HPD5_INT_CONTROL                               0x7dc4
-#define DC_HPD6_INT_CONTROL                               0x7df8
-#       define DC_HPDx_INT_ACK                            (1 << 0)
-#       define DC_HPDx_INT_POLARITY                       (1 << 8)
-#       define DC_HPDx_INT_EN                             (1 << 16)
-#       define DC_HPDx_RX_INT_ACK                         (1 << 20)
-#       define DC_HPDx_RX_INT_EN                          (1 << 24)
-
-/* DCE 3.0 */
-#define DC_HPD1_CONTROL                                   0x7d08
-#define DC_HPD2_CONTROL                                   0x7d14
-#define DC_HPD3_CONTROL                                   0x7d20
-#define DC_HPD4_CONTROL                                   0x7d2c
-/* DCE 3.2 */
-#define DC_HPD5_CONTROL                                   0x7dc8
-#define DC_HPD6_CONTROL                                   0x7dfc
-#       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)
-#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
-/* DCE 3.2 */
-#       define DC_HPDx_EN                                 (1 << 28)
-
-#define D1GRPH_INTERRUPT_STATUS                           0x6158
-#define D2GRPH_INTERRUPT_STATUS                           0x6958
-#       define DxGRPH_PFLIP_INT_OCCURRED                  (1 << 0)
-#       define DxGRPH_PFLIP_INT_CLEAR                     (1 << 8)
-#define D1GRPH_INTERRUPT_CONTROL                          0x615c
-#define D2GRPH_INTERRUPT_CONTROL                          0x695c
-#       define DxGRPH_PFLIP_INT_MASK                      (1 << 0)
-#       define DxGRPH_PFLIP_INT_TYPE                      (1 << 8)
-
-/* PCIE link stuff */
-#define PCIE_LC_TRAINING_CNTL                             0xa1 /* PCIE_P */
-#       define LC_POINT_7_PLUS_EN                         (1 << 6)
-#define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */
-#       define LC_LINK_WIDTH_SHIFT                        0
-#       define LC_LINK_WIDTH_MASK                         0x7
-#       define LC_LINK_WIDTH_X0                           0
-#       define LC_LINK_WIDTH_X1                           1
-#       define LC_LINK_WIDTH_X2                           2
-#       define LC_LINK_WIDTH_X4                           3
-#       define LC_LINK_WIDTH_X8                           4
-#       define LC_LINK_WIDTH_X16                          6
-#       define LC_LINK_WIDTH_RD_SHIFT                     4
-#       define LC_LINK_WIDTH_RD_MASK                      0x70
-#       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)
-#       define LC_RECONFIG_NOW                            (1 << 8)
-#       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)
-#       define LC_RENEGOTIATE_EN                          (1 << 10)
-#       define LC_SHORT_RECONFIG_EN                       (1 << 11)
-#       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)
-#       define LC_UPCONFIGURE_DIS                         (1 << 13)
-#define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */
-#       define LC_GEN2_EN_STRAP                           (1 << 0)
-#       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 1)
-#       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 5)
-#       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 6)
-#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 8)
-#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     3
-#       define LC_CURRENT_DATA_RATE                       (1 << 11)
-#       define LC_VOLTAGE_TIMER_SEL_MASK                  (0xf << 14)
-#       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 21)
-#       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 23)
-#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 24)
-#define MM_CFGREGS_CNTL                                   0x544c
-#       define MM_WR_TO_CFG_EN                            (1 << 3)
-#define LINK_CNTL2                                        0x88 /* F0 */
-#       define TARGET_LINK_SPEED_MASK                     (0xf << 0)
-#       define SELECTABLE_DEEMPHASIS                      (1 << 6)
-
-/* Audio */
-#define AZ_HOT_PLUG_CONTROL               0x7300
-#       define AZ_FORCE_CODEC_WAKE        (1 << 0)
-#       define JACK_DETECTION_ENABLE      (1 << 4)
-#       define UNSOLICITED_RESPONSE_ENABLE (1 << 8)
-#       define CODEC_HOT_PLUG_ENABLE      (1 << 12)
-#       define AUDIO_ENABLED              (1 << 31)
-/* DCE3 adds */
-#       define PIN0_JACK_DETECTION_ENABLE (1 << 4)
-#       define PIN1_JACK_DETECTION_ENABLE (1 << 5)
-#       define PIN2_JACK_DETECTION_ENABLE (1 << 6)
-#       define PIN3_JACK_DETECTION_ENABLE (1 << 7)
-#       define PIN0_AUDIO_ENABLED         (1 << 24)
-#       define PIN1_AUDIO_ENABLED         (1 << 25)
-#       define PIN2_AUDIO_ENABLED         (1 << 26)
-#       define PIN3_AUDIO_ENABLED         (1 << 27)
-
-/* Audio clocks DCE 2.0/3.0 */
-#define AUDIO_DTO                         0x7340
-#       define AUDIO_DTO_PHASE(x)         (((x) & 0xffff) << 0)
-#       define AUDIO_DTO_MODULE(x)        (((x) & 0xffff) << 16)
-
-/* Audio clocks DCE 3.2 */
-#define DCCG_AUDIO_DTO0_PHASE             0x0514
-#define DCCG_AUDIO_DTO0_MODULE            0x0518
-#define DCCG_AUDIO_DTO0_LOAD              0x051c
-#       define DTO_LOAD                   (1 << 31)
-#define DCCG_AUDIO_DTO0_CNTL              0x0520
-#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0)
-#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7
-#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0
-
-#define DCCG_AUDIO_DTO1_PHASE             0x0524
-#define DCCG_AUDIO_DTO1_MODULE            0x0528
-#define DCCG_AUDIO_DTO1_LOAD              0x052c
-#define DCCG_AUDIO_DTO1_CNTL              0x0530
-
-#define DCCG_AUDIO_DTO_SELECT             0x0534
-
-/* digital blocks */
-#define TMDSA_CNTL                       0x7880
-#       define TMDSA_HDMI_EN             (1 << 2)
-#define LVTMA_CNTL                       0x7a80
-#       define LVTMA_HDMI_EN             (1 << 2)
-#define DDIA_CNTL                        0x7200
-#       define DDIA_HDMI_EN              (1 << 2)
-#define DIG0_CNTL                        0x75a0
-#       define DIG_MODE(x)               (((x) & 7) << 8)
-#       define DIG_MODE_DP               0
-#       define DIG_MODE_LVDS             1
-#       define DIG_MODE_TMDS_DVI         2
-#       define DIG_MODE_TMDS_HDMI        3
-#       define DIG_MODE_SDVO             4
-#define DIG1_CNTL                        0x79a0
-
-#define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER          0x71bc
-#define		SPEAKER_ALLOCATION(x)			(((x) & 0x7f) << 0)
-#define		SPEAKER_ALLOCATION_MASK			(0x7f << 0)
-#define		SPEAKER_ALLOCATION_SHIFT		0
-#define		HDMI_CONNECTION				(1 << 16)
-#define		DP_CONNECTION				(1 << 17)
-
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0        0x71c8 /* LPCM */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1        0x71cc /* AC3 */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2        0x71d0 /* MPEG1 */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3        0x71d4 /* MP3 */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4        0x71d8 /* MPEG2 */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5        0x71dc /* AAC */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6        0x71e0 /* DTS */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7        0x71e4 /* ATRAC */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8        0x71e8 /* one bit audio - leave at 0 (default) */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9        0x71ec /* Dolby Digital */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10       0x71f0 /* DTS-HD */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11       0x71f4 /* MAT-MLP */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12       0x71f8 /* DTS */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13       0x71fc /* WMA Pro */
-#       define MAX_CHANNELS(x)                            (((x) & 0x7) << 0)
-/* max channels minus one.  7 = 8 channels */
-#       define SUPPORTED_FREQUENCIES(x)                   (((x) & 0xff) << 8)
-#       define DESCRIPTOR_BYTE_2(x)                       (((x) & 0xff) << 16)
-#       define SUPPORTED_FREQUENCIES_STEREO(x)            (((x) & 0xff) << 24) /* LPCM only */
-/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
- * bit0 = 32 kHz
- * bit1 = 44.1 kHz
- * bit2 = 48 kHz
- * bit3 = 88.2 kHz
- * bit4 = 96 kHz
- * bit5 = 176.4 kHz
- * bit6 = 192 kHz
- */
-
-/* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one
- * instance of the blocks while r6xx has 2.  DCE 3.0 cards are slightly
- * different due to the new DIG blocks, but also have 2 instances.
- * DCE 3.0 HDMI blocks are part of each DIG encoder.
- */
-
-/* rs6xx/rs740/r6xx/dce3 */
-#define HDMI0_CONTROL                0x7400
-/* rs6xx/rs740/r6xx */
-#       define HDMI0_ENABLE          (1 << 0)
-#       define HDMI0_STREAM(x)       (((x) & 3) << 2)
-#       define HDMI0_STREAM_TMDSA    0
-#       define HDMI0_STREAM_LVTMA    1
-#       define HDMI0_STREAM_DVOA     2
-#       define HDMI0_STREAM_DDIA     3
-/* rs6xx/r6xx/dce3 */
-#       define HDMI0_ERROR_ACK       (1 << 8)
-#       define HDMI0_ERROR_MASK      (1 << 9)
-#define HDMI0_STATUS                 0x7404
-#       define HDMI0_ACTIVE_AVMUTE   (1 << 0)
-#       define HDMI0_AUDIO_ENABLE    (1 << 4)
-#       define HDMI0_AZ_FORMAT_WTRIG     (1 << 28)
-#       define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29)
-#define HDMI0_AUDIO_PACKET_CONTROL   0x7408
-#       define HDMI0_AUDIO_SAMPLE_SEND  (1 << 0)
-#       define HDMI0_AUDIO_DELAY_EN(x)  (((x) & 3) << 4)
-#       define HDMI0_AUDIO_DELAY_EN_MASK	(3 << 4)
-#       define HDMI0_AUDIO_SEND_MAX_PACKETS  (1 << 8)
-#       define HDMI0_AUDIO_TEST_EN         (1 << 12)
-#       define HDMI0_AUDIO_PACKETS_PER_LINE(x)  (((x) & 0x1f) << 16)
-#       define HDMI0_AUDIO_PACKETS_PER_LINE_MASK	(0x1f << 16)
-#       define HDMI0_AUDIO_CHANNEL_SWAP    (1 << 24)
-#       define HDMI0_60958_CS_UPDATE       (1 << 26)
-#       define HDMI0_AZ_FORMAT_WTRIG_MASK  (1 << 28)
-#       define HDMI0_AZ_FORMAT_WTRIG_ACK   (1 << 29)
-#define HDMI0_AUDIO_CRC_CONTROL      0x740c
-#       define HDMI0_AUDIO_CRC_EN    (1 << 0)
-#define DCE3_HDMI0_ACR_PACKET_CONTROL	0x740c
-#define HDMI0_VBI_PACKET_CONTROL     0x7410
-#       define HDMI0_NULL_SEND       (1 << 0)
-#       define HDMI0_GC_SEND         (1 << 4)
-#       define HDMI0_GC_CONT         (1 << 5) /* 0 - once; 1 - every frame */
-#define HDMI0_INFOFRAME_CONTROL0     0x7414
-#       define HDMI0_AVI_INFO_SEND   (1 << 0)
-#       define HDMI0_AVI_INFO_CONT   (1 << 1)
-#       define HDMI0_AUDIO_INFO_SEND (1 << 4)
-#       define HDMI0_AUDIO_INFO_CONT (1 << 5)
-#       define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */
-#       define HDMI0_AUDIO_INFO_UPDATE (1 << 7)
-#       define HDMI0_MPEG_INFO_SEND  (1 << 8)
-#       define HDMI0_MPEG_INFO_CONT  (1 << 9)
-#       define HDMI0_MPEG_INFO_UPDATE  (1 << 10)
-#define HDMI0_INFOFRAME_CONTROL1     0x7418
-#       define HDMI0_AVI_INFO_LINE(x)  (((x) & 0x3f) << 0)
-#       define HDMI0_AVI_INFO_LINE_MASK		(0x3f << 0)
-#       define HDMI0_AUDIO_INFO_LINE(x)  (((x) & 0x3f) << 8)
-#       define HDMI0_AUDIO_INFO_LINE_MASK	(0x3f << 8)
-#       define HDMI0_MPEG_INFO_LINE(x)  (((x) & 0x3f) << 16)
-#define HDMI0_GENERIC_PACKET_CONTROL 0x741c
-#       define HDMI0_GENERIC0_SEND   (1 << 0)
-#       define HDMI0_GENERIC0_CONT   (1 << 1)
-#       define HDMI0_GENERIC0_UPDATE (1 << 2)
-#       define HDMI0_GENERIC1_SEND   (1 << 4)
-#       define HDMI0_GENERIC1_CONT   (1 << 5)
-#       define HDMI0_GENERIC0_LINE(x)  (((x) & 0x3f) << 16)
-#       define HDMI0_GENERIC0_LINE_MASK		(0x3f << 16)
-#       define HDMI0_GENERIC1_LINE(x)  (((x) & 0x3f) << 24)
-#       define HDMI0_GENERIC1_LINE_MASK		(0x3f << 24)
-#define HDMI0_GC                     0x7428
-#       define HDMI0_GC_AVMUTE       (1 << 0)
-#define HDMI0_AVI_INFO0              0x7454
-#       define HDMI0_AVI_INFO_CHECKSUM(x)  (((x) & 0xff) << 0)
-#       define HDMI0_AVI_INFO_S(x)   (((x) & 3) << 8)
-#       define HDMI0_AVI_INFO_B(x)   (((x) & 3) << 10)
-#       define HDMI0_AVI_INFO_A(x)   (((x) & 1) << 12)
-#       define HDMI0_AVI_INFO_Y(x)   (((x) & 3) << 13)
-#       define HDMI0_AVI_INFO_Y_RGB       0
-#       define HDMI0_AVI_INFO_Y_YCBCR422  1
-#       define HDMI0_AVI_INFO_Y_YCBCR444  2
-#       define HDMI0_AVI_INFO_Y_A_B_S(x)   (((x) & 0xff) << 8)
-#       define HDMI0_AVI_INFO_R(x)   (((x) & 0xf) << 16)
-#       define HDMI0_AVI_INFO_M(x)   (((x) & 0x3) << 20)
-#       define HDMI0_AVI_INFO_C(x)   (((x) & 0x3) << 22)
-#       define HDMI0_AVI_INFO_C_M_R(x)   (((x) & 0xff) << 16)
-#       define HDMI0_AVI_INFO_SC(x)  (((x) & 0x3) << 24)
-#       define HDMI0_AVI_INFO_ITC_EC_Q_SC(x)  (((x) & 0xff) << 24)
-#define HDMI0_AVI_INFO1              0x7458
-#       define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
-#       define HDMI0_AVI_INFO_PR(x)  (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
-#       define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
-#define HDMI0_AVI_INFO2              0x745c
-#       define HDMI0_AVI_INFO_BOTTOM(x)  (((x) & 0xffff) << 0)
-#       define HDMI0_AVI_INFO_LEFT(x)    (((x) & 0xffff) << 16)
-#define HDMI0_AVI_INFO3              0x7460
-#       define HDMI0_AVI_INFO_RIGHT(x)    (((x) & 0xffff) << 0)
-#       define HDMI0_AVI_INFO_VERSION(x)  (((x) & 3) << 24)
-#define HDMI0_MPEG_INFO0             0x7464
-#       define HDMI0_MPEG_INFO_CHECKSUM(x)  (((x) & 0xff) << 0)
-#       define HDMI0_MPEG_INFO_MB0(x)  (((x) & 0xff) << 8)
-#       define HDMI0_MPEG_INFO_MB1(x)  (((x) & 0xff) << 16)
-#       define HDMI0_MPEG_INFO_MB2(x)  (((x) & 0xff) << 24)
-#define HDMI0_MPEG_INFO1             0x7468
-#       define HDMI0_MPEG_INFO_MB3(x)  (((x) & 0xff) << 0)
-#       define HDMI0_MPEG_INFO_MF(x)   (((x) & 3) << 8)
-#       define HDMI0_MPEG_INFO_FR(x)   (((x) & 1) << 12)
-#define HDMI0_GENERIC0_HDR           0x746c
-#define HDMI0_GENERIC0_0             0x7470
-#define HDMI0_GENERIC0_1             0x7474
-#define HDMI0_GENERIC0_2             0x7478
-#define HDMI0_GENERIC0_3             0x747c
-#define HDMI0_GENERIC0_4             0x7480
-#define HDMI0_GENERIC0_5             0x7484
-#define HDMI0_GENERIC0_6             0x7488
-#define HDMI0_GENERIC1_HDR           0x748c
-#define HDMI0_GENERIC1_0             0x7490
-#define HDMI0_GENERIC1_1             0x7494
-#define HDMI0_GENERIC1_2             0x7498
-#define HDMI0_GENERIC1_3             0x749c
-#define HDMI0_GENERIC1_4             0x74a0
-#define HDMI0_GENERIC1_5             0x74a4
-#define HDMI0_GENERIC1_6             0x74a8
-#define HDMI0_ACR_32_0               0x74ac
-#       define HDMI0_ACR_CTS_32(x)   (((x) & 0xfffff) << 12)
-#       define HDMI0_ACR_CTS_32_MASK		(0xfffff << 12)
-#define HDMI0_ACR_32_1               0x74b0
-#       define HDMI0_ACR_N_32(x)   (((x) & 0xfffff) << 0)
-#       define HDMI0_ACR_N_32_MASK		(0xfffff << 0)
-#define HDMI0_ACR_44_0               0x74b4
-#       define HDMI0_ACR_CTS_44(x)   (((x) & 0xfffff) << 12)
-#       define HDMI0_ACR_CTS_44_MASK		(0xfffff << 12)
-#define HDMI0_ACR_44_1               0x74b8
-#       define HDMI0_ACR_N_44(x)   (((x) & 0xfffff) << 0)
-#       define HDMI0_ACR_N_44_MASK		(0xfffff << 0)
-#define HDMI0_ACR_48_0               0x74bc
-#       define HDMI0_ACR_CTS_48(x)   (((x) & 0xfffff) << 12)
-#       define HDMI0_ACR_CTS_48_MASK		(0xfffff << 12)
-#define HDMI0_ACR_48_1               0x74c0
-#       define HDMI0_ACR_N_48(x)   (((x) & 0xfffff) << 0)
-#       define HDMI0_ACR_N_48_MASK		(0xfffff << 0)
-#define HDMI0_ACR_STATUS_0           0x74c4
-#define HDMI0_ACR_STATUS_1           0x74c8
-#define HDMI0_AUDIO_INFO0            0x74cc
-#       define HDMI0_AUDIO_INFO_CHECKSUM(x)  (((x) & 0xff) << 0)
-#       define HDMI0_AUDIO_INFO_CC(x)  (((x) & 7) << 8)
-#define HDMI0_AUDIO_INFO1            0x74d0
-#       define HDMI0_AUDIO_INFO_CA(x)  (((x) & 0xff) << 0)
-#       define HDMI0_AUDIO_INFO_LSV(x)  (((x) & 0xf) << 11)
-#       define HDMI0_AUDIO_INFO_DM_INH(x)  (((x) & 1) << 15)
-#       define HDMI0_AUDIO_INFO_DM_INH_LSV(x)  (((x) & 0xff) << 8)
-#define HDMI0_60958_0                0x74d4
-#       define HDMI0_60958_CS_A(x)   (((x) & 1) << 0)
-#       define HDMI0_60958_CS_B(x)   (((x) & 1) << 1)
-#       define HDMI0_60958_CS_C(x)   (((x) & 1) << 2)
-#       define HDMI0_60958_CS_D(x)   (((x) & 3) << 3)
-#       define HDMI0_60958_CS_MODE(x)   (((x) & 3) << 6)
-#       define HDMI0_60958_CS_CATEGORY_CODE(x)      (((x) & 0xff) << 8)
-#       define HDMI0_60958_CS_SOURCE_NUMBER(x)      (((x) & 0xf) << 16)
-#       define HDMI0_60958_CS_CHANNEL_NUMBER_L(x)   (((x) & 0xf) << 20)
-#       define HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK	(0xf << 20)
-#       define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
-#       define HDMI0_60958_CS_CLOCK_ACCURACY(x)     (((x) & 3) << 28)
-#       define HDMI0_60958_CS_CLOCK_ACCURACY_MASK	(3 << 28)
-#define HDMI0_60958_1                0x74d8
-#       define HDMI0_60958_CS_WORD_LENGTH(x)        (((x) & 0xf) << 0)
-#       define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x)   (((x) & 0xf) << 4)
-#       define HDMI0_60958_CS_VALID_L(x)   (((x) & 1) << 16)
-#       define HDMI0_60958_CS_VALID_R(x)   (((x) & 1) << 18)
-#       define HDMI0_60958_CS_CHANNEL_NUMBER_R(x)   (((x) & 0xf) << 20)
-#       define HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK	(0xf << 20)
-#define HDMI0_ACR_PACKET_CONTROL     0x74dc
-#       define HDMI0_ACR_SEND        (1 << 0)
-#       define HDMI0_ACR_CONT        (1 << 1)
-#       define HDMI0_ACR_SELECT(x)   (((x) & 3) << 4)
-#       define HDMI0_ACR_HW          0
-#       define HDMI0_ACR_32          1
-#       define HDMI0_ACR_44          2
-#       define HDMI0_ACR_48          3
-#       define HDMI0_ACR_SOURCE      (1 << 8) /* 0 - hw; 1 - cts value */
-#       define HDMI0_ACR_AUTO_SEND   (1 << 12)
-#define DCE3_HDMI0_AUDIO_CRC_CONTROL	0x74dc
-#define HDMI0_RAMP_CONTROL0          0x74e0
-#       define HDMI0_RAMP_MAX_COUNT(x)   (((x) & 0xffffff) << 0)
-#define HDMI0_RAMP_CONTROL1          0x74e4
-#       define HDMI0_RAMP_MIN_COUNT(x)   (((x) & 0xffffff) << 0)
-#define HDMI0_RAMP_CONTROL2          0x74e8
-#       define HDMI0_RAMP_INC_COUNT(x)   (((x) & 0xffffff) << 0)
-#define HDMI0_RAMP_CONTROL3          0x74ec
-#       define HDMI0_RAMP_DEC_COUNT(x)   (((x) & 0xffffff) << 0)
-/* HDMI0_60958_2 is r7xx only */
-#define HDMI0_60958_2                0x74f0
-#       define HDMI0_60958_CS_CHANNEL_NUMBER_2(x)   (((x) & 0xf) << 0)
-#       define HDMI0_60958_CS_CHANNEL_NUMBER_3(x)   (((x) & 0xf) << 4)
-#       define HDMI0_60958_CS_CHANNEL_NUMBER_4(x)   (((x) & 0xf) << 8)
-#       define HDMI0_60958_CS_CHANNEL_NUMBER_5(x)   (((x) & 0xf) << 12)
-#       define HDMI0_60958_CS_CHANNEL_NUMBER_6(x)   (((x) & 0xf) << 16)
-#       define HDMI0_60958_CS_CHANNEL_NUMBER_7(x)   (((x) & 0xf) << 20)
-/* r6xx only; second instance starts at 0x7700 */
-#define HDMI1_CONTROL                0x7700
-#define HDMI1_STATUS                 0x7704
-#define HDMI1_AUDIO_PACKET_CONTROL   0x7708
-/* DCE3; second instance starts at 0x7800 NOT 0x7700 */
-#define DCE3_HDMI1_CONTROL                0x7800
-#define DCE3_HDMI1_STATUS                 0x7804
-#define DCE3_HDMI1_AUDIO_PACKET_CONTROL   0x7808
-/* DCE3.2 (for interrupts) */
-#define AFMT_STATUS                          0x7600
-#       define AFMT_AUDIO_ENABLE             (1 << 4)
-#       define AFMT_AZ_FORMAT_WTRIG          (1 << 28)
-#       define AFMT_AZ_FORMAT_WTRIG_INT      (1 << 29)
-#       define AFMT_AZ_AUDIO_ENABLE_CHG      (1 << 30)
-#define AFMT_AUDIO_PACKET_CONTROL            0x7604
-#       define AFMT_AUDIO_SAMPLE_SEND        (1 << 0)
-#       define AFMT_AUDIO_TEST_EN            (1 << 12)
-#       define AFMT_AUDIO_CHANNEL_SWAP       (1 << 24)
-#       define AFMT_60958_CS_UPDATE          (1 << 26)
-#       define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
-#       define AFMT_AZ_FORMAT_WTRIG_MASK     (1 << 28)
-#       define AFMT_AZ_FORMAT_WTRIG_ACK      (1 << 29)
-#       define AFMT_AZ_AUDIO_ENABLE_CHG_ACK  (1 << 30)
-
-/* DCE3 FMT blocks */
-#define FMT_CONTROL                          0x6700
-#       define FMT_PIXEL_ENCODING            (1 << 16)
-        /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
-#define FMT_BIT_DEPTH_CONTROL                0x6710
-#       define FMT_TRUNCATE_EN               (1 << 0)
-#       define FMT_TRUNCATE_DEPTH            (1 << 4)
-#       define FMT_SPATIAL_DITHER_EN         (1 << 8)
-#       define FMT_SPATIAL_DITHER_MODE(x)    ((x) << 9)
-#       define FMT_SPATIAL_DITHER_DEPTH      (1 << 12)
-#       define FMT_FRAME_RANDOM_ENABLE       (1 << 13)
-#       define FMT_RGB_RANDOM_ENABLE         (1 << 14)
-#       define FMT_HIGHPASS_RANDOM_ENABLE    (1 << 15)
-#       define FMT_TEMPORAL_DITHER_EN        (1 << 16)
-#       define FMT_TEMPORAL_DITHER_DEPTH     (1 << 20)
-#       define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
-#       define FMT_TEMPORAL_LEVEL            (1 << 24)
-#       define FMT_TEMPORAL_DITHER_RESET     (1 << 25)
-#       define FMT_25FRC_SEL(x)              ((x) << 26)
-#       define FMT_50FRC_SEL(x)              ((x) << 28)
-#       define FMT_75FRC_SEL(x)              ((x) << 30)
-#define FMT_CLAMP_CONTROL                    0x672c
-#       define FMT_CLAMP_DATA_EN             (1 << 0)
-#       define FMT_CLAMP_COLOR_FORMAT(x)     ((x) << 16)
-#       define FMT_CLAMP_6BPC                0
-#       define FMT_CLAMP_8BPC                1
-#       define FMT_CLAMP_10BPC               2
-
-/* Power management */
-#define CG_SPLL_FUNC_CNTL                                 0x600
-#       define SPLL_RESET                                (1 << 0)
-#       define SPLL_SLEEP                                (1 << 1)
-#       define SPLL_REF_DIV(x)                           ((x) << 2)
-#       define SPLL_REF_DIV_MASK                         (7 << 2)
-#       define SPLL_FB_DIV(x)                            ((x) << 5)
-#       define SPLL_FB_DIV_MASK                          (0xff << 5)
-#       define SPLL_PULSEEN                              (1 << 13)
-#       define SPLL_PULSENUM(x)                          ((x) << 14)
-#       define SPLL_PULSENUM_MASK                        (3 << 14)
-#       define SPLL_SW_HILEN(x)                          ((x) << 16)
-#       define SPLL_SW_HILEN_MASK                        (0xf << 16)
-#       define SPLL_SW_LOLEN(x)                          ((x) << 20)
-#       define SPLL_SW_LOLEN_MASK                        (0xf << 20)
-#       define SPLL_DIVEN                                (1 << 24)
-#       define SPLL_BYPASS_EN                            (1 << 25)
-#       define SPLL_CHG_STATUS                           (1 << 29)
-#       define SPLL_CTLREQ                               (1 << 30)
-#       define SPLL_CTLACK                               (1 << 31)
-
-#define GENERAL_PWRMGT                                    0x618
-#       define GLOBAL_PWRMGT_EN                           (1 << 0)
-#       define STATIC_PM_EN                               (1 << 1)
-#       define MOBILE_SU                                  (1 << 2)
-#       define THERMAL_PROTECTION_DIS                     (1 << 3)
-#       define THERMAL_PROTECTION_TYPE                    (1 << 4)
-#       define ENABLE_GEN2PCIE                            (1 << 5)
-#       define SW_GPIO_INDEX(x)                           ((x) << 6)
-#       define SW_GPIO_INDEX_MASK                         (3 << 6)
-#       define LOW_VOLT_D2_ACPI                           (1 << 8)
-#       define LOW_VOLT_D3_ACPI                           (1 << 9)
-#       define VOLT_PWRMGT_EN                             (1 << 10)
-#define CG_TPC                                            0x61c
-#       define TPCC(x)                                    ((x) << 0)
-#       define TPCC_MASK                                  (0x7fffff << 0)
-#       define TPU(x)                                     ((x) << 23)
-#       define TPU_MASK                                   (0x1f << 23)
-#define SCLK_PWRMGT_CNTL                                  0x620
-#       define SCLK_PWRMGT_OFF                            (1 << 0)
-#       define SCLK_TURNOFF                               (1 << 1)
-#       define SPLL_TURNOFF                               (1 << 2)
-#       define SU_SCLK_USE_BCLK                           (1 << 3)
-#       define DYNAMIC_GFX_ISLAND_PWR_DOWN                (1 << 4)
-#       define DYNAMIC_GFX_ISLAND_PWR_LP                  (1 << 5)
-#       define CLK_TURN_ON_STAGGER                        (1 << 6)
-#       define CLK_TURN_OFF_STAGGER                       (1 << 7)
-#       define FIR_FORCE_TREND_SEL                        (1 << 8)
-#       define FIR_TREND_MODE                             (1 << 9)
-#       define DYN_GFX_CLK_OFF_EN                         (1 << 10)
-#       define VDDC3D_TURNOFF_D1                          (1 << 11)
-#       define VDDC3D_TURNOFF_D2                          (1 << 12)
-#       define VDDC3D_TURNOFF_D3                          (1 << 13)
-#       define SPLL_TURNOFF_D2                            (1 << 14)
-#       define SCLK_LOW_D1                                (1 << 15)
-#       define DYN_GFX_CLK_OFF_MC_EN                      (1 << 16)
-#define MCLK_PWRMGT_CNTL                                  0x624
-#       define MPLL_PWRMGT_OFF                            (1 << 0)
-#       define YCLK_TURNOFF                               (1 << 1)
-#       define MPLL_TURNOFF                               (1 << 2)
-#       define SU_MCLK_USE_BCLK                           (1 << 3)
-#       define DLL_READY                                  (1 << 4)
-#       define MC_BUSY                                    (1 << 5)
-#       define MC_INT_CNTL                                (1 << 7)
-#       define MRDCKA_SLEEP                               (1 << 8)
-#       define MRDCKB_SLEEP                               (1 << 9)
-#       define MRDCKC_SLEEP                               (1 << 10)
-#       define MRDCKD_SLEEP                               (1 << 11)
-#       define MRDCKE_SLEEP                               (1 << 12)
-#       define MRDCKF_SLEEP                               (1 << 13)
-#       define MRDCKG_SLEEP                               (1 << 14)
-#       define MRDCKH_SLEEP                               (1 << 15)
-#       define MRDCKA_RESET                               (1 << 16)
-#       define MRDCKB_RESET                               (1 << 17)
-#       define MRDCKC_RESET                               (1 << 18)
-#       define MRDCKD_RESET                               (1 << 19)
-#       define MRDCKE_RESET                               (1 << 20)
-#       define MRDCKF_RESET                               (1 << 21)
-#       define MRDCKG_RESET                               (1 << 22)
-#       define MRDCKH_RESET                               (1 << 23)
-#       define DLL_READY_READ                             (1 << 24)
-#       define USE_DISPLAY_GAP                            (1 << 25)
-#       define USE_DISPLAY_URGENT_NORMAL                  (1 << 26)
-#       define USE_DISPLAY_GAP_CTXSW                      (1 << 27)
-#       define MPLL_TURNOFF_D2                            (1 << 28)
-#       define USE_DISPLAY_URGENT_CTXSW                   (1 << 29)
-
-#define MPLL_TIME                                         0x634
-#       define MPLL_LOCK_TIME(x)                          ((x) << 0)
-#       define MPLL_LOCK_TIME_MASK                        (0xffff << 0)
-#       define MPLL_RESET_TIME(x)                         ((x) << 16)
-#       define MPLL_RESET_TIME_MASK                       (0xffff << 16)
-
-#define SCLK_FREQ_SETTING_STEP_0_PART1                    0x648
-#       define STEP_0_SPLL_POST_DIV(x)                    ((x) << 0)
-#       define STEP_0_SPLL_POST_DIV_MASK                  (0xff << 0)
-#       define STEP_0_SPLL_FB_DIV(x)                      ((x) << 8)
-#       define STEP_0_SPLL_FB_DIV_MASK                    (0xff << 8)
-#       define STEP_0_SPLL_REF_DIV(x)                     ((x) << 16)
-#       define STEP_0_SPLL_REF_DIV_MASK                   (7 << 16)
-#       define STEP_0_SPLL_STEP_TIME(x)                   ((x) << 19)
-#       define STEP_0_SPLL_STEP_TIME_MASK                 (0x1fff << 19)
-#define SCLK_FREQ_SETTING_STEP_0_PART2                    0x64c
-#       define STEP_0_PULSE_HIGH_CNT(x)                   ((x) << 0)
-#       define STEP_0_PULSE_HIGH_CNT_MASK                 (0x1ff << 0)
-#       define STEP_0_POST_DIV_EN                         (1 << 9)
-#       define STEP_0_SPLL_STEP_ENABLE                    (1 << 30)
-#       define STEP_0_SPLL_ENTRY_VALID                    (1 << 31)
-
-#define VID_RT                                            0x6f8
-#       define VID_CRT(x)                                 ((x) << 0)
-#       define VID_CRT_MASK                               (0x1fff << 0)
-#       define VID_CRTU(x)                                ((x) << 13)
-#       define VID_CRTU_MASK                              (7 << 13)
-#       define SSTU(x)                                    ((x) << 16)
-#       define SSTU_MASK                                  (7 << 16)
-#define CTXSW_PROFILE_INDEX                               0x6fc
-#       define CTXSW_FREQ_VIDS_CFG_INDEX(x)               ((x) << 0)
-#       define CTXSW_FREQ_VIDS_CFG_INDEX_MASK             (3 << 0)
-#       define CTXSW_FREQ_VIDS_CFG_INDEX_SHIFT            0
-#       define CTXSW_FREQ_MCLK_CFG_INDEX(x)               ((x) << 2)
-#       define CTXSW_FREQ_MCLK_CFG_INDEX_MASK             (3 << 2)
-#       define CTXSW_FREQ_MCLK_CFG_INDEX_SHIFT            2
-#       define CTXSW_FREQ_SCLK_CFG_INDEX(x)               ((x) << 4)
-#       define CTXSW_FREQ_SCLK_CFG_INDEX_MASK             (0x1f << 4)
-#       define CTXSW_FREQ_SCLK_CFG_INDEX_SHIFT            4
-#       define CTXSW_FREQ_STATE_SPLL_RESET_EN             (1 << 9)
-#       define CTXSW_FREQ_STATE_ENABLE                    (1 << 10)
-#       define CTXSW_FREQ_DISPLAY_WATERMARK               (1 << 11)
-#       define CTXSW_FREQ_GEN2PCIE_VOLT                   (1 << 12)
-
-#define TARGET_AND_CURRENT_PROFILE_INDEX                  0x70c
-#       define TARGET_PROFILE_INDEX_MASK                  (3 << 0)
-#       define TARGET_PROFILE_INDEX_SHIFT                 0
-#       define CURRENT_PROFILE_INDEX_MASK                 (3 << 2)
-#       define CURRENT_PROFILE_INDEX_SHIFT                2
-#       define DYN_PWR_ENTER_INDEX(x)                     ((x) << 4)
-#       define DYN_PWR_ENTER_INDEX_MASK                   (3 << 4)
-#       define DYN_PWR_ENTER_INDEX_SHIFT                  4
-#       define CURR_MCLK_INDEX_MASK                       (3 << 6)
-#       define CURR_MCLK_INDEX_SHIFT                      6
-#       define CURR_SCLK_INDEX_MASK                       (0x1f << 8)
-#       define CURR_SCLK_INDEX_SHIFT                      8
-#       define CURR_VID_INDEX_MASK                        (3 << 13)
-#       define CURR_VID_INDEX_SHIFT                       13
-
-#define LOWER_GPIO_ENABLE                                 0x710
-#define UPPER_GPIO_ENABLE                                 0x714
-#define CTXSW_VID_LOWER_GPIO_CNTL                         0x718
-
-#define VID_UPPER_GPIO_CNTL                               0x740
-#define CG_CTX_CGTT3D_R                                   0x744
-#       define PHC(x)                                     ((x) << 0)
-#       define PHC_MASK                                   (0x1ff << 0)
-#       define SDC(x)                                     ((x) << 9)
-#       define SDC_MASK                                   (0x3fff << 9)
-#define CG_VDDC3D_OOR                                     0x748
-#       define SU(x)                                      ((x) << 23)
-#       define SU_MASK                                    (0xf << 23)
-#define CG_FTV                                            0x74c
-#define CG_FFCT_0                                         0x750
-#       define UTC_0(x)                                   ((x) << 0)
-#       define UTC_0_MASK                                 (0x3ff << 0)
-#       define DTC_0(x)                                   ((x) << 10)
-#       define DTC_0_MASK                                 (0x3ff << 10)
-
-#define CG_BSP                                            0x78c
-#       define BSP(x)                                     ((x) << 0)
-#       define BSP_MASK                                   (0xffff << 0)
-#       define BSU(x)                                     ((x) << 16)
-#       define BSU_MASK                                   (0xf << 16)
-#define CG_RT                                             0x790
-#       define FLS(x)                                     ((x) << 0)
-#       define FLS_MASK                                   (0xffff << 0)
-#       define FMS(x)                                     ((x) << 16)
-#       define FMS_MASK                                   (0xffff << 16)
-#define CG_LT                                             0x794
-#       define FHS(x)                                     ((x) << 0)
-#       define FHS_MASK                                   (0xffff << 0)
-#define CG_GIT                                            0x798
-#       define CG_GICST(x)                                ((x) << 0)
-#       define CG_GICST_MASK                              (0xffff << 0)
-#       define CG_GIPOT(x)                                ((x) << 16)
-#       define CG_GIPOT_MASK                              (0xffff << 16)
-
-#define CG_SSP                                            0x7a8
-#       define CG_SST(x)                                  ((x) << 0)
-#       define CG_SST_MASK                                (0xffff << 0)
-#       define CG_SSTU(x)                                 ((x) << 16)
-#       define CG_SSTU_MASK                               (0xf << 16)
-
-#define CG_RLC_REQ_AND_RSP                                0x7c4
-#       define RLC_CG_REQ_TYPE_MASK                       0xf
-#       define RLC_CG_REQ_TYPE_SHIFT                      0
-#       define CG_RLC_RSP_TYPE_MASK                       0xf0
-#       define CG_RLC_RSP_TYPE_SHIFT                      4
-
-#define CG_FC_T                                           0x7cc
-#       define FC_T(x)                                    ((x) << 0)
-#       define FC_T_MASK                                  (0xffff << 0)
-#       define FC_TU(x)                                   ((x) << 16)
-#       define FC_TU_MASK                                 (0x1f << 16)
-
-#define GPIOPAD_MASK                                      0x1798
-#define GPIOPAD_A                                         0x179c
-#define GPIOPAD_EN                                        0x17a0
-
-#define GRBM_PWR_CNTL                                     0x800c
-#       define REQ_TYPE_MASK                              0xf
-#       define REQ_TYPE_SHIFT                             0
-#       define RSP_TYPE_MASK                              0xf0
-#       define RSP_TYPE_SHIFT                             4
-
-/*
- * UVD
- */
-#define UVD_SEMA_ADDR_LOW				0xef00
-#define UVD_SEMA_ADDR_HIGH				0xef04
-#define UVD_SEMA_CMD					0xef08
-
-#define UVD_GPCOM_VCPU_CMD				0xef0c
-#define UVD_GPCOM_VCPU_DATA0				0xef10
-#define UVD_GPCOM_VCPU_DATA1				0xef14
-#define UVD_ENGINE_CNTL					0xef18
-#define UVD_NO_OP					0xeffc
-
-#define UVD_SEMA_CNTL					0xf400
-#define UVD_RB_ARB_CTRL					0xf480
-
-#define UVD_LMI_EXT40_ADDR				0xf498
-#define UVD_CGC_GATE					0xf4a8
-#define UVD_LMI_CTRL2					0xf4f4
-#define UVD_MASTINT_EN					0xf500
-#define UVD_FW_START					0xf51C
-#define UVD_LMI_ADDR_EXT				0xf594
-#define UVD_LMI_CTRL					0xf598
-#define UVD_LMI_SWAP_CNTL				0xf5b4
-#define UVD_MP_SWAP_CNTL				0xf5bC
-#define UVD_MPC_CNTL					0xf5dC
-#define UVD_MPC_SET_MUXA0				0xf5e4
-#define UVD_MPC_SET_MUXA1				0xf5e8
-#define UVD_MPC_SET_MUXB0				0xf5eC
-#define UVD_MPC_SET_MUXB1				0xf5f0
-#define UVD_MPC_SET_MUX					0xf5f4
-#define UVD_MPC_SET_ALU					0xf5f8
-
-#define UVD_VCPU_CACHE_OFFSET0				0xf608
-#define UVD_VCPU_CACHE_SIZE0				0xf60c
-#define UVD_VCPU_CACHE_OFFSET1				0xf610
-#define UVD_VCPU_CACHE_SIZE1				0xf614
-#define UVD_VCPU_CACHE_OFFSET2				0xf618
-#define UVD_VCPU_CACHE_SIZE2				0xf61c
-
-#define UVD_VCPU_CNTL					0xf660
-#define UVD_SOFT_RESET					0xf680
-#define		RBC_SOFT_RESET					(1<<0)
-#define		LBSI_SOFT_RESET					(1<<1)
-#define		LMI_SOFT_RESET					(1<<2)
-#define		VCPU_SOFT_RESET					(1<<3)
-#define		CSM_SOFT_RESET					(1<<5)
-#define		CXW_SOFT_RESET					(1<<6)
-#define		TAP_SOFT_RESET					(1<<7)
-#define		LMI_UMC_SOFT_RESET				(1<<13)
-#define UVD_RBC_IB_BASE					0xf684
-#define UVD_RBC_IB_SIZE					0xf688
-#define UVD_RBC_RB_BASE					0xf68c
-#define UVD_RBC_RB_RPTR					0xf690
-#define UVD_RBC_RB_WPTR					0xf694
-#define UVD_RBC_RB_WPTR_CNTL				0xf698
-
-#define UVD_STATUS					0xf6bc
-
-#define UVD_SEMA_TIMEOUT_STATUS				0xf6c0
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL		0xf6c4
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL		0xf6c8
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL		0xf6cc
-
-#define UVD_RBC_RB_CNTL					0xf6a4
-#define UVD_RBC_RB_RPTR_ADDR				0xf6a8
-
-#define UVD_CONTEXT_ID					0xf6f4
-
-/* rs780 only */
-#define	GFX_MACRO_BYPASS_CNTL				0x30c0
-#define		SPLL_BYPASS_CNTL			(1 << 0)
-#define		UPLL_BYPASS_CNTL			(1 << 1)
-
-#define CG_UPLL_FUNC_CNTL				0x7e0
-#	define UPLL_RESET_MASK				0x00000001
-#	define UPLL_SLEEP_MASK				0x00000002
-#	define UPLL_BYPASS_EN_MASK			0x00000004
-#	define UPLL_CTLREQ_MASK				0x00000008
-#	define UPLL_FB_DIV(x)				((x) << 4)
-#	define UPLL_FB_DIV_MASK				0x0000FFF0
-#	define UPLL_REF_DIV(x)				((x) << 16)
-#	define UPLL_REF_DIV_MASK			0x003F0000
-#	define UPLL_REFCLK_SRC_SEL_MASK			0x20000000
-#	define UPLL_CTLACK_MASK				0x40000000
-#	define UPLL_CTLACK2_MASK			0x80000000
-#define CG_UPLL_FUNC_CNTL_2				0x7e4
-#	define UPLL_SW_HILEN(x)				((x) << 0)
-#	define UPLL_SW_LOLEN(x)				((x) << 4)
-#	define UPLL_SW_HILEN2(x)			((x) << 8)
-#	define UPLL_SW_LOLEN2(x)			((x) << 12)
-#	define UPLL_DIVEN_MASK				0x00010000
-#	define UPLL_DIVEN2_MASK				0x00020000
-#	define UPLL_SW_MASK				0x0003FFFF
-#	define VCLK_SRC_SEL(x)				((x) << 20)
-#	define VCLK_SRC_SEL_MASK			0x01F00000
-#	define DCLK_SRC_SEL(x)				((x) << 25)
-#	define DCLK_SRC_SEL_MASK			0x3E000000
-
-/*
- * PM4
- */
-#define PACKET0(reg, n)	((RADEON_PACKET_TYPE0 << 30) |			\
-			 (((reg) >> 2) & 0xFFFF) |			\
-			 ((n) & 0x3FFF) << 16)
-#define PACKET3(op, n)	((RADEON_PACKET_TYPE3 << 30) |			\
-			 (((op) & 0xFF) << 8) |				\
-			 ((n) & 0x3FFF) << 16)
-
-/* Packet 3 types */
-#define	PACKET3_NOP					0x10
-#define	PACKET3_INDIRECT_BUFFER_END			0x17
-#define	PACKET3_SET_PREDICATION				0x20
-#define	PACKET3_REG_RMW					0x21
-#define	PACKET3_COND_EXEC				0x22
-#define	PACKET3_PRED_EXEC				0x23
-#define	PACKET3_START_3D_CMDBUF				0x24
-#define	PACKET3_DRAW_INDEX_2				0x27
-#define	PACKET3_CONTEXT_CONTROL				0x28
-#define	PACKET3_DRAW_INDEX_IMMD_BE			0x29
-#define	PACKET3_INDEX_TYPE				0x2A
-#define	PACKET3_DRAW_INDEX				0x2B
-#define	PACKET3_DRAW_INDEX_AUTO				0x2D
-#define	PACKET3_DRAW_INDEX_IMMD				0x2E
-#define	PACKET3_NUM_INSTANCES				0x2F
-#define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
-#define	PACKET3_INDIRECT_BUFFER_MP			0x38
-#define	PACKET3_MEM_SEMAPHORE				0x39
-#              define PACKET3_SEM_WAIT_ON_SIGNAL    (0x1 << 12)
-#              define PACKET3_SEM_SEL_SIGNAL	    (0x6 << 29)
-#              define PACKET3_SEM_SEL_WAIT	    (0x7 << 29)
-#define	PACKET3_MPEG_INDEX				0x3A
-#define	PACKET3_COPY_DW					0x3B
-#define	PACKET3_WAIT_REG_MEM				0x3C
-#define	PACKET3_MEM_WRITE				0x3D
-#define	PACKET3_INDIRECT_BUFFER				0x32
-#define	PACKET3_CP_DMA					0x41
-/* 1. header
- * 2. SRC_ADDR_LO [31:0]
- * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0]
- * 4. DST_ADDR_LO [31:0]
- * 5. DST_ADDR_HI [7:0]
- * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
- */
-#              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)
-/* COMMAND */
-#              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
-                /* 0 - none
-		 * 1 - 8 in 16
-		 * 2 - 8 in 32
-		 * 3 - 8 in 64
-		 */
-#              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
-                /* 0 - none
-		 * 1 - 8 in 16
-		 * 2 - 8 in 32
-		 * 3 - 8 in 64
-		 */
-#              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)
-                /* 0 - memory
-		 * 1 - register
-		 */
-#              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)
-                /* 0 - memory
-		 * 1 - register
-		 */
-#              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)
-#              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)
-#define	PACKET3_PFP_SYNC_ME				0x42 /* r7xx+ only */
-#define	PACKET3_SURFACE_SYNC				0x43
-#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
-#              define PACKET3_FULL_CACHE_ENA       (1 << 20) /* r7xx+ only */
-#              define PACKET3_TC_ACTION_ENA        (1 << 23)
-#              define PACKET3_VC_ACTION_ENA        (1 << 24)
-#              define PACKET3_CB_ACTION_ENA        (1 << 25)
-#              define PACKET3_DB_ACTION_ENA        (1 << 26)
-#              define PACKET3_SH_ACTION_ENA        (1 << 27)
-#              define PACKET3_SMX_ACTION_ENA       (1 << 28)
-#define	PACKET3_ME_INITIALIZE				0x44
-#define		PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
-#define	PACKET3_COND_WRITE				0x45
-#define	PACKET3_EVENT_WRITE				0x46
-#define		EVENT_TYPE(x)                           ((x) << 0)
-#define		EVENT_INDEX(x)                          ((x) << 8)
-                /* 0 - any non-TS event
-		 * 1 - ZPASS_DONE
-		 * 2 - SAMPLE_PIPELINESTAT
-		 * 3 - SAMPLE_STREAMOUTSTAT*
-		 * 4 - *S_PARTIAL_FLUSH
-		 * 5 - TS events
-		 */
-#define	PACKET3_EVENT_WRITE_EOP				0x47
-#define		DATA_SEL(x)                             ((x) << 29)
-                /* 0 - discard
-		 * 1 - send low 32bit data
-		 * 2 - send 64bit data
-		 * 3 - send 64bit counter value
-		 */
-#define		INT_SEL(x)                              ((x) << 24)
-                /* 0 - none
-		 * 1 - interrupt only (DATA_SEL = 0)
-		 * 2 - interrupt when data write is confirmed
-		 */
-#define	PACKET3_ONE_REG_WRITE				0x57
-#define	PACKET3_SET_CONFIG_REG				0x68
-#define		PACKET3_SET_CONFIG_REG_OFFSET			0x00008000
-#define		PACKET3_SET_CONFIG_REG_END			0x0000ac00
-#define	PACKET3_SET_CONTEXT_REG				0x69
-#define		PACKET3_SET_CONTEXT_REG_OFFSET			0x00028000
-#define		PACKET3_SET_CONTEXT_REG_END			0x00029000
-#define	PACKET3_SET_ALU_CONST				0x6A
-#define		PACKET3_SET_ALU_CONST_OFFSET			0x00030000
-#define		PACKET3_SET_ALU_CONST_END			0x00032000
-#define	PACKET3_SET_BOOL_CONST				0x6B
-#define		PACKET3_SET_BOOL_CONST_OFFSET			0x0003e380
-#define		PACKET3_SET_BOOL_CONST_END			0x00040000
-#define	PACKET3_SET_LOOP_CONST				0x6C
-#define		PACKET3_SET_LOOP_CONST_OFFSET			0x0003e200
-#define		PACKET3_SET_LOOP_CONST_END			0x0003e380
-#define	PACKET3_SET_RESOURCE				0x6D
-#define		PACKET3_SET_RESOURCE_OFFSET			0x00038000
-#define		PACKET3_SET_RESOURCE_END			0x0003c000
-#define	PACKET3_SET_SAMPLER				0x6E
-#define		PACKET3_SET_SAMPLER_OFFSET			0x0003c000
-#define		PACKET3_SET_SAMPLER_END				0x0003cff0
-#define	PACKET3_SET_CTL_CONST				0x6F
-#define		PACKET3_SET_CTL_CONST_OFFSET			0x0003cff0
-#define		PACKET3_SET_CTL_CONST_END			0x0003e200
-#define	PACKET3_STRMOUT_BASE_UPDATE			0x72 /* r7xx */
-#define	PACKET3_SURFACE_BASE_UPDATE			0x73
-
-#define R_000011_K8_FB_LOCATION                 0x11
-#define R_000012_MC_MISC_UMA_CNTL               0x12
-#define   G_000012_K8_ADDR_EXT(x)               (((x) >> 0) & 0xFF)
-#define R_0028F8_MC_INDEX			0x28F8
-#define   	S_0028F8_MC_IND_ADDR(x)                 (((x) & 0x1FF) << 0)
-#define   	C_0028F8_MC_IND_ADDR                    0xFFFFFE00
-#define   	S_0028F8_MC_IND_WR_EN(x)                (((x) & 0x1) << 9)
-#define R_0028FC_MC_DATA                        0x28FC
-
-#define	R_008020_GRBM_SOFT_RESET		0x8020
-#define		S_008020_SOFT_RESET_CP(x)		(((x) & 1) << 0)
-#define		S_008020_SOFT_RESET_CB(x)		(((x) & 1) << 1)
-#define		S_008020_SOFT_RESET_CR(x)		(((x) & 1) << 2)
-#define		S_008020_SOFT_RESET_DB(x)		(((x) & 1) << 3)
-#define		S_008020_SOFT_RESET_PA(x)		(((x) & 1) << 5)
-#define		S_008020_SOFT_RESET_SC(x)		(((x) & 1) << 6)
-#define		S_008020_SOFT_RESET_SMX(x)		(((x) & 1) << 7)
-#define		S_008020_SOFT_RESET_SPI(x)		(((x) & 1) << 8)
-#define		S_008020_SOFT_RESET_SH(x)		(((x) & 1) << 9)
-#define		S_008020_SOFT_RESET_SX(x)		(((x) & 1) << 10)
-#define		S_008020_SOFT_RESET_TC(x)		(((x) & 1) << 11)
-#define		S_008020_SOFT_RESET_TA(x)		(((x) & 1) << 12)
-#define		S_008020_SOFT_RESET_VC(x)		(((x) & 1) << 13)
-#define		S_008020_SOFT_RESET_VGT(x)		(((x) & 1) << 14)
-#define	R_008010_GRBM_STATUS			0x8010
-#define		S_008010_CMDFIFO_AVAIL(x)		(((x) & 0x1F) << 0)
-#define		S_008010_CP_RQ_PENDING(x)		(((x) & 1) << 6)
-#define		S_008010_CF_RQ_PENDING(x)		(((x) & 1) << 7)
-#define		S_008010_PF_RQ_PENDING(x)		(((x) & 1) << 8)
-#define		S_008010_GRBM_EE_BUSY(x)		(((x) & 1) << 10)
-#define		S_008010_VC_BUSY(x)			(((x) & 1) << 11)
-#define		S_008010_DB03_CLEAN(x)			(((x) & 1) << 12)
-#define		S_008010_CB03_CLEAN(x)			(((x) & 1) << 13)
-#define		S_008010_VGT_BUSY_NO_DMA(x)		(((x) & 1) << 16)
-#define		S_008010_VGT_BUSY(x)			(((x) & 1) << 17)
-#define		S_008010_TA03_BUSY(x)			(((x) & 1) << 18)
-#define		S_008010_TC_BUSY(x)			(((x) & 1) << 19)
-#define		S_008010_SX_BUSY(x)			(((x) & 1) << 20)
-#define		S_008010_SH_BUSY(x)			(((x) & 1) << 21)
-#define		S_008010_SPI03_BUSY(x)			(((x) & 1) << 22)
-#define		S_008010_SMX_BUSY(x)			(((x) & 1) << 23)
-#define		S_008010_SC_BUSY(x)			(((x) & 1) << 24)
-#define		S_008010_PA_BUSY(x)			(((x) & 1) << 25)
-#define		S_008010_DB03_BUSY(x)			(((x) & 1) << 26)
-#define		S_008010_CR_BUSY(x)			(((x) & 1) << 27)
-#define		S_008010_CP_COHERENCY_BUSY(x)		(((x) & 1) << 28)
-#define		S_008010_CP_BUSY(x)			(((x) & 1) << 29)
-#define		S_008010_CB03_BUSY(x)			(((x) & 1) << 30)
-#define		S_008010_GUI_ACTIVE(x)			(((x) & 1) << 31)
-#define		G_008010_CMDFIFO_AVAIL(x)		(((x) >> 0) & 0x1F)
-#define		G_008010_CP_RQ_PENDING(x)		(((x) >> 6) & 1)
-#define		G_008010_CF_RQ_PENDING(x)		(((x) >> 7) & 1)
-#define		G_008010_PF_RQ_PENDING(x)		(((x) >> 8) & 1)
-#define		G_008010_GRBM_EE_BUSY(x)		(((x) >> 10) & 1)
-#define		G_008010_VC_BUSY(x)			(((x) >> 11) & 1)
-#define		G_008010_DB03_CLEAN(x)			(((x) >> 12) & 1)
-#define		G_008010_CB03_CLEAN(x)			(((x) >> 13) & 1)
-#define		G_008010_TA_BUSY(x)			(((x) >> 14) & 1)
-#define		G_008010_VGT_BUSY_NO_DMA(x)		(((x) >> 16) & 1)
-#define		G_008010_VGT_BUSY(x)			(((x) >> 17) & 1)
-#define		G_008010_TA03_BUSY(x)			(((x) >> 18) & 1)
-#define		G_008010_TC_BUSY(x)			(((x) >> 19) & 1)
-#define		G_008010_SX_BUSY(x)			(((x) >> 20) & 1)
-#define		G_008010_SH_BUSY(x)			(((x) >> 21) & 1)
-#define		G_008010_SPI03_BUSY(x)			(((x) >> 22) & 1)
-#define		G_008010_SMX_BUSY(x)			(((x) >> 23) & 1)
-#define		G_008010_SC_BUSY(x)			(((x) >> 24) & 1)
-#define		G_008010_PA_BUSY(x)			(((x) >> 25) & 1)
-#define		G_008010_DB03_BUSY(x)			(((x) >> 26) & 1)
-#define		G_008010_CR_BUSY(x)			(((x) >> 27) & 1)
-#define		G_008010_CP_COHERENCY_BUSY(x)		(((x) >> 28) & 1)
-#define		G_008010_CP_BUSY(x)			(((x) >> 29) & 1)
-#define		G_008010_CB03_BUSY(x)			(((x) >> 30) & 1)
-#define		G_008010_GUI_ACTIVE(x)			(((x) >> 31) & 1)
-#define	R_008014_GRBM_STATUS2			0x8014
-#define		S_008014_CR_CLEAN(x)			(((x) & 1) << 0)
-#define		S_008014_SMX_CLEAN(x)			(((x) & 1) << 1)
-#define		S_008014_SPI0_BUSY(x)			(((x) & 1) << 8)
-#define		S_008014_SPI1_BUSY(x)			(((x) & 1) << 9)
-#define		S_008014_SPI2_BUSY(x)			(((x) & 1) << 10)
-#define		S_008014_SPI3_BUSY(x)			(((x) & 1) << 11)
-#define		S_008014_TA0_BUSY(x)			(((x) & 1) << 12)
-#define		S_008014_TA1_BUSY(x)			(((x) & 1) << 13)
-#define		S_008014_TA2_BUSY(x)			(((x) & 1) << 14)
-#define		S_008014_TA3_BUSY(x)			(((x) & 1) << 15)
-#define		S_008014_DB0_BUSY(x)			(((x) & 1) << 16)
-#define		S_008014_DB1_BUSY(x)			(((x) & 1) << 17)
-#define		S_008014_DB2_BUSY(x)			(((x) & 1) << 18)
-#define		S_008014_DB3_BUSY(x)			(((x) & 1) << 19)
-#define		S_008014_CB0_BUSY(x)			(((x) & 1) << 20)
-#define		S_008014_CB1_BUSY(x)			(((x) & 1) << 21)
-#define		S_008014_CB2_BUSY(x)			(((x) & 1) << 22)
-#define		S_008014_CB3_BUSY(x)			(((x) & 1) << 23)
-#define		G_008014_CR_CLEAN(x)			(((x) >> 0) & 1)
-#define		G_008014_SMX_CLEAN(x)			(((x) >> 1) & 1)
-#define		G_008014_SPI0_BUSY(x)			(((x) >> 8) & 1)
-#define		G_008014_SPI1_BUSY(x)			(((x) >> 9) & 1)
-#define		G_008014_SPI2_BUSY(x)			(((x) >> 10) & 1)
-#define		G_008014_SPI3_BUSY(x)			(((x) >> 11) & 1)
-#define		G_008014_TA0_BUSY(x)			(((x) >> 12) & 1)
-#define		G_008014_TA1_BUSY(x)			(((x) >> 13) & 1)
-#define		G_008014_TA2_BUSY(x)			(((x) >> 14) & 1)
-#define		G_008014_TA3_BUSY(x)			(((x) >> 15) & 1)
-#define		G_008014_DB0_BUSY(x)			(((x) >> 16) & 1)
-#define		G_008014_DB1_BUSY(x)			(((x) >> 17) & 1)
-#define		G_008014_DB2_BUSY(x)			(((x) >> 18) & 1)
-#define		G_008014_DB3_BUSY(x)			(((x) >> 19) & 1)
-#define		G_008014_CB0_BUSY(x)			(((x) >> 20) & 1)
-#define		G_008014_CB1_BUSY(x)			(((x) >> 21) & 1)
-#define		G_008014_CB2_BUSY(x)			(((x) >> 22) & 1)
-#define		G_008014_CB3_BUSY(x)			(((x) >> 23) & 1)
-#define	R_000E50_SRBM_STATUS				0x0E50
-#define		G_000E50_RLC_RQ_PENDING(x)		(((x) >> 3) & 1)
-#define		G_000E50_RCU_RQ_PENDING(x)		(((x) >> 4) & 1)
-#define		G_000E50_GRBM_RQ_PENDING(x)		(((x) >> 5) & 1)
-#define		G_000E50_HI_RQ_PENDING(x)		(((x) >> 6) & 1)
-#define		G_000E50_IO_EXTERN_SIGNAL(x)		(((x) >> 7) & 1)
-#define		G_000E50_VMC_BUSY(x)			(((x) >> 8) & 1)
-#define		G_000E50_MCB_BUSY(x)			(((x) >> 9) & 1)
-#define		G_000E50_MCDZ_BUSY(x)			(((x) >> 10) & 1)
-#define		G_000E50_MCDY_BUSY(x)			(((x) >> 11) & 1)
-#define		G_000E50_MCDX_BUSY(x)			(((x) >> 12) & 1)
-#define		G_000E50_MCDW_BUSY(x)			(((x) >> 13) & 1)
-#define		G_000E50_SEM_BUSY(x)			(((x) >> 14) & 1)
-#define		G_000E50_RLC_BUSY(x)			(((x) >> 15) & 1)
-#define		G_000E50_IH_BUSY(x)			(((x) >> 17) & 1)
-#define		G_000E50_BIF_BUSY(x)			(((x) >> 29) & 1)
-#define	R_000E60_SRBM_SOFT_RESET			0x0E60
-#define		S_000E60_SOFT_RESET_BIF(x)		(((x) & 1) << 1)
-#define		S_000E60_SOFT_RESET_CG(x)		(((x) & 1) << 2)
-#define		S_000E60_SOFT_RESET_CMC(x)		(((x) & 1) << 3)
-#define		S_000E60_SOFT_RESET_CSC(x)		(((x) & 1) << 4)
-#define		S_000E60_SOFT_RESET_DC(x)		(((x) & 1) << 5)
-#define		S_000E60_SOFT_RESET_GRBM(x)		(((x) & 1) << 8)
-#define		S_000E60_SOFT_RESET_HDP(x)		(((x) & 1) << 9)
-#define		S_000E60_SOFT_RESET_IH(x)		(((x) & 1) << 10)
-#define		S_000E60_SOFT_RESET_MC(x)		(((x) & 1) << 11)
-#define		S_000E60_SOFT_RESET_RLC(x)		(((x) & 1) << 13)
-#define		S_000E60_SOFT_RESET_ROM(x)		(((x) & 1) << 14)
-#define		S_000E60_SOFT_RESET_SEM(x)		(((x) & 1) << 15)
-#define		S_000E60_SOFT_RESET_TSC(x)		(((x) & 1) << 16)
-#define		S_000E60_SOFT_RESET_VMC(x)		(((x) & 1) << 17)
-
-#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL		0x5480
-
-#define R_028C04_PA_SC_AA_CONFIG                     0x028C04
-#define   S_028C04_MSAA_NUM_SAMPLES(x)                 (((x) & 0x3) << 0)
-#define   G_028C04_MSAA_NUM_SAMPLES(x)                 (((x) >> 0) & 0x3)
-#define   C_028C04_MSAA_NUM_SAMPLES                    0xFFFFFFFC
-#define   S_028C04_AA_MASK_CENTROID_DTMN(x)            (((x) & 0x1) << 4)
-#define   G_028C04_AA_MASK_CENTROID_DTMN(x)            (((x) >> 4) & 0x1)
-#define   C_028C04_AA_MASK_CENTROID_DTMN               0xFFFFFFEF
-#define   S_028C04_MAX_SAMPLE_DIST(x)                  (((x) & 0xF) << 13)
-#define   G_028C04_MAX_SAMPLE_DIST(x)                  (((x) >> 13) & 0xF)
-#define   C_028C04_MAX_SAMPLE_DIST                     0xFFFE1FFF
-#define R_0280E0_CB_COLOR0_FRAG                      0x0280E0
-#define   S_0280E0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
-#define   G_0280E0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
-#define   C_0280E0_BASE_256B                           0x00000000
-#define R_0280E4_CB_COLOR1_FRAG                      0x0280E4
-#define R_0280E8_CB_COLOR2_FRAG                      0x0280E8
-#define R_0280EC_CB_COLOR3_FRAG                      0x0280EC
-#define R_0280F0_CB_COLOR4_FRAG                      0x0280F0
-#define R_0280F4_CB_COLOR5_FRAG                      0x0280F4
-#define R_0280F8_CB_COLOR6_FRAG                      0x0280F8
-#define R_0280FC_CB_COLOR7_FRAG                      0x0280FC
-#define R_0280C0_CB_COLOR0_TILE                      0x0280C0
-#define   S_0280C0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
-#define   G_0280C0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
-#define   C_0280C0_BASE_256B                           0x00000000
-#define R_0280C4_CB_COLOR1_TILE                      0x0280C4
-#define R_0280C8_CB_COLOR2_TILE                      0x0280C8
-#define R_0280CC_CB_COLOR3_TILE                      0x0280CC
-#define R_0280D0_CB_COLOR4_TILE                      0x0280D0
-#define R_0280D4_CB_COLOR5_TILE                      0x0280D4
-#define R_0280D8_CB_COLOR6_TILE                      0x0280D8
-#define R_0280DC_CB_COLOR7_TILE                      0x0280DC
-#define R_0280A0_CB_COLOR0_INFO                      0x0280A0
-#define   S_0280A0_ENDIAN(x)                           (((x) & 0x3) << 0)
-#define   G_0280A0_ENDIAN(x)                           (((x) >> 0) & 0x3)
-#define   C_0280A0_ENDIAN                              0xFFFFFFFC
-#define   S_0280A0_FORMAT(x)                           (((x) & 0x3F) << 2)
-#define   G_0280A0_FORMAT(x)                           (((x) >> 2) & 0x3F)
-#define   C_0280A0_FORMAT                              0xFFFFFF03
-#define     V_0280A0_COLOR_INVALID                     0x00000000
-#define     V_0280A0_COLOR_8                           0x00000001
-#define     V_0280A0_COLOR_4_4                         0x00000002
-#define     V_0280A0_COLOR_3_3_2                       0x00000003
-#define     V_0280A0_COLOR_16                          0x00000005
-#define     V_0280A0_COLOR_16_FLOAT                    0x00000006
-#define     V_0280A0_COLOR_8_8                         0x00000007
-#define     V_0280A0_COLOR_5_6_5                       0x00000008
-#define     V_0280A0_COLOR_6_5_5                       0x00000009
-#define     V_0280A0_COLOR_1_5_5_5                     0x0000000A
-#define     V_0280A0_COLOR_4_4_4_4                     0x0000000B
-#define     V_0280A0_COLOR_5_5_5_1                     0x0000000C
-#define     V_0280A0_COLOR_32                          0x0000000D
-#define     V_0280A0_COLOR_32_FLOAT                    0x0000000E
-#define     V_0280A0_COLOR_16_16                       0x0000000F
-#define     V_0280A0_COLOR_16_16_FLOAT                 0x00000010
-#define     V_0280A0_COLOR_8_24                        0x00000011
-#define     V_0280A0_COLOR_8_24_FLOAT                  0x00000012
-#define     V_0280A0_COLOR_24_8                        0x00000013
-#define     V_0280A0_COLOR_24_8_FLOAT                  0x00000014
-#define     V_0280A0_COLOR_10_11_11                    0x00000015
-#define     V_0280A0_COLOR_10_11_11_FLOAT              0x00000016
-#define     V_0280A0_COLOR_11_11_10                    0x00000017
-#define     V_0280A0_COLOR_11_11_10_FLOAT              0x00000018
-#define     V_0280A0_COLOR_2_10_10_10                  0x00000019
-#define     V_0280A0_COLOR_8_8_8_8                     0x0000001A
-#define     V_0280A0_COLOR_10_10_10_2                  0x0000001B
-#define     V_0280A0_COLOR_X24_8_32_FLOAT              0x0000001C
-#define     V_0280A0_COLOR_32_32                       0x0000001D
-#define     V_0280A0_COLOR_32_32_FLOAT                 0x0000001E
-#define     V_0280A0_COLOR_16_16_16_16                 0x0000001F
-#define     V_0280A0_COLOR_16_16_16_16_FLOAT           0x00000020
-#define     V_0280A0_COLOR_32_32_32_32                 0x00000022
-#define     V_0280A0_COLOR_32_32_32_32_FLOAT           0x00000023
-#define   S_0280A0_ARRAY_MODE(x)                       (((x) & 0xF) << 8)
-#define   G_0280A0_ARRAY_MODE(x)                       (((x) >> 8) & 0xF)
-#define   C_0280A0_ARRAY_MODE                          0xFFFFF0FF
-#define     V_0280A0_ARRAY_LINEAR_GENERAL              0x00000000
-#define     V_0280A0_ARRAY_LINEAR_ALIGNED              0x00000001
-#define     V_0280A0_ARRAY_1D_TILED_THIN1              0x00000002
-#define     V_0280A0_ARRAY_2D_TILED_THIN1              0x00000004
-#define   S_0280A0_NUMBER_TYPE(x)                      (((x) & 0x7) << 12)
-#define   G_0280A0_NUMBER_TYPE(x)                      (((x) >> 12) & 0x7)
-#define   C_0280A0_NUMBER_TYPE                         0xFFFF8FFF
-#define   S_0280A0_READ_SIZE(x)                        (((x) & 0x1) << 15)
-#define   G_0280A0_READ_SIZE(x)                        (((x) >> 15) & 0x1)
-#define   C_0280A0_READ_SIZE                           0xFFFF7FFF
-#define   S_0280A0_COMP_SWAP(x)                        (((x) & 0x3) << 16)
-#define   G_0280A0_COMP_SWAP(x)                        (((x) >> 16) & 0x3)
-#define   C_0280A0_COMP_SWAP                           0xFFFCFFFF
-#define   S_0280A0_TILE_MODE(x)                        (((x) & 0x3) << 18)
-#define   G_0280A0_TILE_MODE(x)                        (((x) >> 18) & 0x3)
-#define   C_0280A0_TILE_MODE                           0xFFF3FFFF
-#define     V_0280A0_TILE_DISABLE			0
-#define     V_0280A0_CLEAR_ENABLE			1
-#define     V_0280A0_FRAG_ENABLE			2
-#define   S_0280A0_BLEND_CLAMP(x)                      (((x) & 0x1) << 20)
-#define   G_0280A0_BLEND_CLAMP(x)                      (((x) >> 20) & 0x1)
-#define   C_0280A0_BLEND_CLAMP                         0xFFEFFFFF
-#define   S_0280A0_CLEAR_COLOR(x)                      (((x) & 0x1) << 21)
-#define   G_0280A0_CLEAR_COLOR(x)                      (((x) >> 21) & 0x1)
-#define   C_0280A0_CLEAR_COLOR                         0xFFDFFFFF
-#define   S_0280A0_BLEND_BYPASS(x)                     (((x) & 0x1) << 22)
-#define   G_0280A0_BLEND_BYPASS(x)                     (((x) >> 22) & 0x1)
-#define   C_0280A0_BLEND_BYPASS                        0xFFBFFFFF
-#define   S_0280A0_BLEND_FLOAT32(x)                    (((x) & 0x1) << 23)
-#define   G_0280A0_BLEND_FLOAT32(x)                    (((x) >> 23) & 0x1)
-#define   C_0280A0_BLEND_FLOAT32                       0xFF7FFFFF
-#define   S_0280A0_SIMPLE_FLOAT(x)                     (((x) & 0x1) << 24)
-#define   G_0280A0_SIMPLE_FLOAT(x)                     (((x) >> 24) & 0x1)
-#define   C_0280A0_SIMPLE_FLOAT                        0xFEFFFFFF
-#define   S_0280A0_ROUND_MODE(x)                       (((x) & 0x1) << 25)
-#define   G_0280A0_ROUND_MODE(x)                       (((x) >> 25) & 0x1)
-#define   C_0280A0_ROUND_MODE                          0xFDFFFFFF
-#define   S_0280A0_TILE_COMPACT(x)                     (((x) & 0x1) << 26)
-#define   G_0280A0_TILE_COMPACT(x)                     (((x) >> 26) & 0x1)
-#define   C_0280A0_TILE_COMPACT                        0xFBFFFFFF
-#define   S_0280A0_SOURCE_FORMAT(x)                    (((x) & 0x1) << 27)
-#define   G_0280A0_SOURCE_FORMAT(x)                    (((x) >> 27) & 0x1)
-#define   C_0280A0_SOURCE_FORMAT                       0xF7FFFFFF
-#define R_0280A4_CB_COLOR1_INFO                      0x0280A4
-#define R_0280A8_CB_COLOR2_INFO                      0x0280A8
-#define R_0280AC_CB_COLOR3_INFO                      0x0280AC
-#define R_0280B0_CB_COLOR4_INFO                      0x0280B0
-#define R_0280B4_CB_COLOR5_INFO                      0x0280B4
-#define R_0280B8_CB_COLOR6_INFO                      0x0280B8
-#define R_0280BC_CB_COLOR7_INFO                      0x0280BC
-#define R_028060_CB_COLOR0_SIZE                      0x028060
-#define   S_028060_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
-#define   G_028060_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
-#define   C_028060_PITCH_TILE_MAX                      0xFFFFFC00
-#define   S_028060_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
-#define   G_028060_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
-#define   C_028060_SLICE_TILE_MAX                      0xC00003FF
-#define R_028064_CB_COLOR1_SIZE                      0x028064
-#define R_028068_CB_COLOR2_SIZE                      0x028068
-#define R_02806C_CB_COLOR3_SIZE                      0x02806C
-#define R_028070_CB_COLOR4_SIZE                      0x028070
-#define R_028074_CB_COLOR5_SIZE                      0x028074
-#define R_028078_CB_COLOR6_SIZE                      0x028078
-#define R_02807C_CB_COLOR7_SIZE                      0x02807C
-#define R_028238_CB_TARGET_MASK                      0x028238
-#define   S_028238_TARGET0_ENABLE(x)                   (((x) & 0xF) << 0)
-#define   G_028238_TARGET0_ENABLE(x)                   (((x) >> 0) & 0xF)
-#define   C_028238_TARGET0_ENABLE                      0xFFFFFFF0
-#define   S_028238_TARGET1_ENABLE(x)                   (((x) & 0xF) << 4)
-#define   G_028238_TARGET1_ENABLE(x)                   (((x) >> 4) & 0xF)
-#define   C_028238_TARGET1_ENABLE                      0xFFFFFF0F
-#define   S_028238_TARGET2_ENABLE(x)                   (((x) & 0xF) << 8)
-#define   G_028238_TARGET2_ENABLE(x)                   (((x) >> 8) & 0xF)
-#define   C_028238_TARGET2_ENABLE                      0xFFFFF0FF
-#define   S_028238_TARGET3_ENABLE(x)                   (((x) & 0xF) << 12)
-#define   G_028238_TARGET3_ENABLE(x)                   (((x) >> 12) & 0xF)
-#define   C_028238_TARGET3_ENABLE                      0xFFFF0FFF
-#define   S_028238_TARGET4_ENABLE(x)                   (((x) & 0xF) << 16)
-#define   G_028238_TARGET4_ENABLE(x)                   (((x) >> 16) & 0xF)
-#define   C_028238_TARGET4_ENABLE                      0xFFF0FFFF
-#define   S_028238_TARGET5_ENABLE(x)                   (((x) & 0xF) << 20)
-#define   G_028238_TARGET5_ENABLE(x)                   (((x) >> 20) & 0xF)
-#define   C_028238_TARGET5_ENABLE                      0xFF0FFFFF
-#define   S_028238_TARGET6_ENABLE(x)                   (((x) & 0xF) << 24)
-#define   G_028238_TARGET6_ENABLE(x)                   (((x) >> 24) & 0xF)
-#define   C_028238_TARGET6_ENABLE                      0xF0FFFFFF
-#define   S_028238_TARGET7_ENABLE(x)                   (((x) & 0xF) << 28)
-#define   G_028238_TARGET7_ENABLE(x)                   (((x) >> 28) & 0xF)
-#define   C_028238_TARGET7_ENABLE                      0x0FFFFFFF
-#define R_02823C_CB_SHADER_MASK                      0x02823C
-#define   S_02823C_OUTPUT0_ENABLE(x)                   (((x) & 0xF) << 0)
-#define   G_02823C_OUTPUT0_ENABLE(x)                   (((x) >> 0) & 0xF)
-#define   C_02823C_OUTPUT0_ENABLE                      0xFFFFFFF0
-#define   S_02823C_OUTPUT1_ENABLE(x)                   (((x) & 0xF) << 4)
-#define   G_02823C_OUTPUT1_ENABLE(x)                   (((x) >> 4) & 0xF)
-#define   C_02823C_OUTPUT1_ENABLE                      0xFFFFFF0F
-#define   S_02823C_OUTPUT2_ENABLE(x)                   (((x) & 0xF) << 8)
-#define   G_02823C_OUTPUT2_ENABLE(x)                   (((x) >> 8) & 0xF)
-#define   C_02823C_OUTPUT2_ENABLE                      0xFFFFF0FF
-#define   S_02823C_OUTPUT3_ENABLE(x)                   (((x) & 0xF) << 12)
-#define   G_02823C_OUTPUT3_ENABLE(x)                   (((x) >> 12) & 0xF)
-#define   C_02823C_OUTPUT3_ENABLE                      0xFFFF0FFF
-#define   S_02823C_OUTPUT4_ENABLE(x)                   (((x) & 0xF) << 16)
-#define   G_02823C_OUTPUT4_ENABLE(x)                   (((x) >> 16) & 0xF)
-#define   C_02823C_OUTPUT4_ENABLE                      0xFFF0FFFF
-#define   S_02823C_OUTPUT5_ENABLE(x)                   (((x) & 0xF) << 20)
-#define   G_02823C_OUTPUT5_ENABLE(x)                   (((x) >> 20) & 0xF)
-#define   C_02823C_OUTPUT5_ENABLE                      0xFF0FFFFF
-#define   S_02823C_OUTPUT6_ENABLE(x)                   (((x) & 0xF) << 24)
-#define   G_02823C_OUTPUT6_ENABLE(x)                   (((x) >> 24) & 0xF)
-#define   C_02823C_OUTPUT6_ENABLE                      0xF0FFFFFF
-#define   S_02823C_OUTPUT7_ENABLE(x)                   (((x) & 0xF) << 28)
-#define   G_02823C_OUTPUT7_ENABLE(x)                   (((x) >> 28) & 0xF)
-#define   C_02823C_OUTPUT7_ENABLE                      0x0FFFFFFF
-#define R_028AB0_VGT_STRMOUT_EN                      0x028AB0
-#define   S_028AB0_STREAMOUT(x)                        (((x) & 0x1) << 0)
-#define   G_028AB0_STREAMOUT(x)                        (((x) >> 0) & 0x1)
-#define   C_028AB0_STREAMOUT                           0xFFFFFFFE
-#define R_028B20_VGT_STRMOUT_BUFFER_EN               0x028B20
-#define   S_028B20_BUFFER_0_EN(x)                      (((x) & 0x1) << 0)
-#define   G_028B20_BUFFER_0_EN(x)                      (((x) >> 0) & 0x1)
-#define   C_028B20_BUFFER_0_EN                         0xFFFFFFFE
-#define   S_028B20_BUFFER_1_EN(x)                      (((x) & 0x1) << 1)
-#define   G_028B20_BUFFER_1_EN(x)                      (((x) >> 1) & 0x1)
-#define   C_028B20_BUFFER_1_EN                         0xFFFFFFFD
-#define   S_028B20_BUFFER_2_EN(x)                      (((x) & 0x1) << 2)
-#define   G_028B20_BUFFER_2_EN(x)                      (((x) >> 2) & 0x1)
-#define   C_028B20_BUFFER_2_EN                         0xFFFFFFFB
-#define   S_028B20_BUFFER_3_EN(x)                      (((x) & 0x1) << 3)
-#define   G_028B20_BUFFER_3_EN(x)                      (((x) >> 3) & 0x1)
-#define   C_028B20_BUFFER_3_EN                         0xFFFFFFF7
-#define   S_028B20_SIZE(x)                             (((x) & 0xFFFFFFFF) << 0)
-#define   G_028B20_SIZE(x)                             (((x) >> 0) & 0xFFFFFFFF)
-#define   C_028B20_SIZE                                0x00000000
-#define R_038000_SQ_TEX_RESOURCE_WORD0_0             0x038000
-#define   S_038000_DIM(x)                              (((x) & 0x7) << 0)
-#define   G_038000_DIM(x)                              (((x) >> 0) & 0x7)
-#define   C_038000_DIM                                 0xFFFFFFF8
-#define     V_038000_SQ_TEX_DIM_1D                     0x00000000
-#define     V_038000_SQ_TEX_DIM_2D                     0x00000001
-#define     V_038000_SQ_TEX_DIM_3D                     0x00000002
-#define     V_038000_SQ_TEX_DIM_CUBEMAP                0x00000003
-#define     V_038000_SQ_TEX_DIM_1D_ARRAY               0x00000004
-#define     V_038000_SQ_TEX_DIM_2D_ARRAY               0x00000005
-#define     V_038000_SQ_TEX_DIM_2D_MSAA                0x00000006
-#define     V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA          0x00000007
-#define   S_038000_TILE_MODE(x)                        (((x) & 0xF) << 3)
-#define   G_038000_TILE_MODE(x)                        (((x) >> 3) & 0xF)
-#define   C_038000_TILE_MODE                           0xFFFFFF87
-#define     V_038000_ARRAY_LINEAR_GENERAL              0x00000000
-#define     V_038000_ARRAY_LINEAR_ALIGNED              0x00000001
-#define     V_038000_ARRAY_1D_TILED_THIN1              0x00000002
-#define     V_038000_ARRAY_2D_TILED_THIN1              0x00000004
-#define   S_038000_TILE_TYPE(x)                        (((x) & 0x1) << 7)
-#define   G_038000_TILE_TYPE(x)                        (((x) >> 7) & 0x1)
-#define   C_038000_TILE_TYPE                           0xFFFFFF7F
-#define   S_038000_PITCH(x)                            (((x) & 0x7FF) << 8)
-#define   G_038000_PITCH(x)                            (((x) >> 8) & 0x7FF)
-#define   C_038000_PITCH                               0xFFF800FF
-#define   S_038000_TEX_WIDTH(x)                        (((x) & 0x1FFF) << 19)
-#define   G_038000_TEX_WIDTH(x)                        (((x) >> 19) & 0x1FFF)
-#define   C_038000_TEX_WIDTH                           0x0007FFFF
-#define R_038004_SQ_TEX_RESOURCE_WORD1_0             0x038004
-#define   S_038004_TEX_HEIGHT(x)                       (((x) & 0x1FFF) << 0)
-#define   G_038004_TEX_HEIGHT(x)                       (((x) >> 0) & 0x1FFF)
-#define   C_038004_TEX_HEIGHT                          0xFFFFE000
-#define   S_038004_TEX_DEPTH(x)                        (((x) & 0x1FFF) << 13)
-#define   G_038004_TEX_DEPTH(x)                        (((x) >> 13) & 0x1FFF)
-#define   C_038004_TEX_DEPTH                           0xFC001FFF
-#define   S_038004_DATA_FORMAT(x)                      (((x) & 0x3F) << 26)
-#define   G_038004_DATA_FORMAT(x)                      (((x) >> 26) & 0x3F)
-#define   C_038004_DATA_FORMAT                         0x03FFFFFF
-#define     V_038004_COLOR_INVALID                     0x00000000
-#define     V_038004_COLOR_8                           0x00000001
-#define     V_038004_COLOR_4_4                         0x00000002
-#define     V_038004_COLOR_3_3_2                       0x00000003
-#define     V_038004_COLOR_16                          0x00000005
-#define     V_038004_COLOR_16_FLOAT                    0x00000006
-#define     V_038004_COLOR_8_8                         0x00000007
-#define     V_038004_COLOR_5_6_5                       0x00000008
-#define     V_038004_COLOR_6_5_5                       0x00000009
-#define     V_038004_COLOR_1_5_5_5                     0x0000000A
-#define     V_038004_COLOR_4_4_4_4                     0x0000000B
-#define     V_038004_COLOR_5_5_5_1                     0x0000000C
-#define     V_038004_COLOR_32                          0x0000000D
-#define     V_038004_COLOR_32_FLOAT                    0x0000000E
-#define     V_038004_COLOR_16_16                       0x0000000F
-#define     V_038004_COLOR_16_16_FLOAT                 0x00000010
-#define     V_038004_COLOR_8_24                        0x00000011
-#define     V_038004_COLOR_8_24_FLOAT                  0x00000012
-#define     V_038004_COLOR_24_8                        0x00000013
-#define     V_038004_COLOR_24_8_FLOAT                  0x00000014
-#define     V_038004_COLOR_10_11_11                    0x00000015
-#define     V_038004_COLOR_10_11_11_FLOAT              0x00000016
-#define     V_038004_COLOR_11_11_10                    0x00000017
-#define     V_038004_COLOR_11_11_10_FLOAT              0x00000018
-#define     V_038004_COLOR_2_10_10_10                  0x00000019
-#define     V_038004_COLOR_8_8_8_8                     0x0000001A
-#define     V_038004_COLOR_10_10_10_2                  0x0000001B
-#define     V_038004_COLOR_X24_8_32_FLOAT              0x0000001C
-#define     V_038004_COLOR_32_32                       0x0000001D
-#define     V_038004_COLOR_32_32_FLOAT                 0x0000001E
-#define     V_038004_COLOR_16_16_16_16                 0x0000001F
-#define     V_038004_COLOR_16_16_16_16_FLOAT           0x00000020
-#define     V_038004_COLOR_32_32_32_32                 0x00000022
-#define     V_038004_COLOR_32_32_32_32_FLOAT           0x00000023
-#define     V_038004_FMT_1                             0x00000025
-#define     V_038004_FMT_GB_GR                         0x00000027
-#define     V_038004_FMT_BG_RG                         0x00000028
-#define     V_038004_FMT_32_AS_8                       0x00000029
-#define     V_038004_FMT_32_AS_8_8                     0x0000002A
-#define     V_038004_FMT_5_9_9_9_SHAREDEXP             0x0000002B
-#define     V_038004_FMT_8_8_8                         0x0000002C
-#define     V_038004_FMT_16_16_16                      0x0000002D
-#define     V_038004_FMT_16_16_16_FLOAT                0x0000002E
-#define     V_038004_FMT_32_32_32                      0x0000002F
-#define     V_038004_FMT_32_32_32_FLOAT                0x00000030
-#define     V_038004_FMT_BC1                           0x00000031
-#define     V_038004_FMT_BC2                           0x00000032
-#define     V_038004_FMT_BC3                           0x00000033
-#define     V_038004_FMT_BC4                           0x00000034
-#define     V_038004_FMT_BC5                           0x00000035
-#define     V_038004_FMT_BC6                           0x00000036
-#define     V_038004_FMT_BC7                           0x00000037
-#define     V_038004_FMT_32_AS_32_32_32_32             0x00000038
-#define R_038010_SQ_TEX_RESOURCE_WORD4_0             0x038010
-#define   S_038010_FORMAT_COMP_X(x)                    (((x) & 0x3) << 0)
-#define   G_038010_FORMAT_COMP_X(x)                    (((x) >> 0) & 0x3)
-#define   C_038010_FORMAT_COMP_X                       0xFFFFFFFC
-#define   S_038010_FORMAT_COMP_Y(x)                    (((x) & 0x3) << 2)
-#define   G_038010_FORMAT_COMP_Y(x)                    (((x) >> 2) & 0x3)
-#define   C_038010_FORMAT_COMP_Y                       0xFFFFFFF3
-#define   S_038010_FORMAT_COMP_Z(x)                    (((x) & 0x3) << 4)
-#define   G_038010_FORMAT_COMP_Z(x)                    (((x) >> 4) & 0x3)
-#define   C_038010_FORMAT_COMP_Z                       0xFFFFFFCF
-#define   S_038010_FORMAT_COMP_W(x)                    (((x) & 0x3) << 6)
-#define   G_038010_FORMAT_COMP_W(x)                    (((x) >> 6) & 0x3)
-#define   C_038010_FORMAT_COMP_W                       0xFFFFFF3F
-#define   S_038010_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 8)
-#define   G_038010_NUM_FORMAT_ALL(x)                   (((x) >> 8) & 0x3)
-#define   C_038010_NUM_FORMAT_ALL                      0xFFFFFCFF
-#define   S_038010_SRF_MODE_ALL(x)                     (((x) & 0x1) << 10)
-#define   G_038010_SRF_MODE_ALL(x)                     (((x) >> 10) & 0x1)
-#define   C_038010_SRF_MODE_ALL                        0xFFFFFBFF
-#define   S_038010_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 11)
-#define   G_038010_FORCE_DEGAMMA(x)                    (((x) >> 11) & 0x1)
-#define   C_038010_FORCE_DEGAMMA                       0xFFFFF7FF
-#define   S_038010_ENDIAN_SWAP(x)                      (((x) & 0x3) << 12)
-#define   G_038010_ENDIAN_SWAP(x)                      (((x) >> 12) & 0x3)
-#define   C_038010_ENDIAN_SWAP                         0xFFFFCFFF
-#define   S_038010_REQUEST_SIZE(x)                     (((x) & 0x3) << 14)
-#define   G_038010_REQUEST_SIZE(x)                     (((x) >> 14) & 0x3)
-#define   C_038010_REQUEST_SIZE                        0xFFFF3FFF
-#define   S_038010_DST_SEL_X(x)                        (((x) & 0x7) << 16)
-#define   G_038010_DST_SEL_X(x)                        (((x) >> 16) & 0x7)
-#define   C_038010_DST_SEL_X                           0xFFF8FFFF
-#define   S_038010_DST_SEL_Y(x)                        (((x) & 0x7) << 19)
-#define   G_038010_DST_SEL_Y(x)                        (((x) >> 19) & 0x7)
-#define   C_038010_DST_SEL_Y                           0xFFC7FFFF
-#define   S_038010_DST_SEL_Z(x)                        (((x) & 0x7) << 22)
-#define   G_038010_DST_SEL_Z(x)                        (((x) >> 22) & 0x7)
-#define   C_038010_DST_SEL_Z                           0xFE3FFFFF
-#define   S_038010_DST_SEL_W(x)                        (((x) & 0x7) << 25)
-#define   G_038010_DST_SEL_W(x)                        (((x) >> 25) & 0x7)
-#define   C_038010_DST_SEL_W                           0xF1FFFFFF
-#	define SQ_SEL_X					0
-#	define SQ_SEL_Y					1
-#	define SQ_SEL_Z					2
-#	define SQ_SEL_W					3
-#	define SQ_SEL_0					4
-#	define SQ_SEL_1					5
-#define   S_038010_BASE_LEVEL(x)                       (((x) & 0xF) << 28)
-#define   G_038010_BASE_LEVEL(x)                       (((x) >> 28) & 0xF)
-#define   C_038010_BASE_LEVEL                          0x0FFFFFFF
-#define R_038014_SQ_TEX_RESOURCE_WORD5_0             0x038014
-#define   S_038014_LAST_LEVEL(x)                       (((x) & 0xF) << 0)
-#define   G_038014_LAST_LEVEL(x)                       (((x) >> 0) & 0xF)
-#define   C_038014_LAST_LEVEL                          0xFFFFFFF0
-#define   S_038014_BASE_ARRAY(x)                       (((x) & 0x1FFF) << 4)
-#define   G_038014_BASE_ARRAY(x)                       (((x) >> 4) & 0x1FFF)
-#define   C_038014_BASE_ARRAY                          0xFFFE000F
-#define   S_038014_LAST_ARRAY(x)                       (((x) & 0x1FFF) << 17)
-#define   G_038014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
-#define   C_038014_LAST_ARRAY                          0xC001FFFF
-#define R_0288A8_SQ_ESGS_RING_ITEMSIZE               0x0288A8
-#define   S_0288A8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
-#define   G_0288A8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
-#define   C_0288A8_ITEMSIZE                            0xFFFF8000
-#define R_008C44_SQ_ESGS_RING_SIZE                   0x008C44
-#define   S_008C44_MEM_SIZE(x)                         (((x) & 0xFFFFFFFF) << 0)
-#define   G_008C44_MEM_SIZE(x)                         (((x) >> 0) & 0xFFFFFFFF)
-#define   C_008C44_MEM_SIZE                            0x00000000
-#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE              0x0288B0
-#define   S_0288B0_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
-#define   G_0288B0_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
-#define   C_0288B0_ITEMSIZE                            0xFFFF8000
-#define R_008C54_SQ_ESTMP_RING_SIZE                  0x008C54
-#define   S_008C54_MEM_SIZE(x)                         (((x) & 0xFFFFFFFF) << 0)
-#define   G_008C54_MEM_SIZE(x)                         (((x) >> 0) & 0xFFFFFFFF)
-#define   C_008C54_MEM_SIZE                            0x00000000
-#define R_0288C0_SQ_FBUF_RING_ITEMSIZE               0x0288C0
-#define   S_0288C0_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
-#define   G_0288C0_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
-#define   C_0288C0_ITEMSIZE                            0xFFFF8000
-#define R_008C74_SQ_FBUF_RING_SIZE                   0x008C74
-#define   S_008C74_MEM_SIZE(x)                         (((x) & 0xFFFFFFFF) << 0)
-#define   G_008C74_MEM_SIZE(x)                         (((x) >> 0) & 0xFFFFFFFF)
-#define   C_008C74_MEM_SIZE                            0x00000000
-#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE              0x0288B4
-#define   S_0288B4_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
-#define   G_0288B4_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
-#define   C_0288B4_ITEMSIZE                            0xFFFF8000
-#define R_008C5C_SQ_GSTMP_RING_SIZE                  0x008C5C
-#define   S_008C5C_MEM_SIZE(x)                         (((x) & 0xFFFFFFFF) << 0)
-#define   G_008C5C_MEM_SIZE(x)                         (((x) >> 0) & 0xFFFFFFFF)
-#define   C_008C5C_MEM_SIZE                            0x00000000
-#define R_0288AC_SQ_GSVS_RING_ITEMSIZE               0x0288AC
-#define   S_0288AC_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
-#define   G_0288AC_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
-#define   C_0288AC_ITEMSIZE                            0xFFFF8000
-#define R_008C4C_SQ_GSVS_RING_SIZE                   0x008C4C
-#define   S_008C4C_MEM_SIZE(x)                         (((x) & 0xFFFFFFFF) << 0)
-#define   G_008C4C_MEM_SIZE(x)                         (((x) >> 0) & 0xFFFFFFFF)
-#define   C_008C4C_MEM_SIZE                            0x00000000
-#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE              0x0288BC
-#define   S_0288BC_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
-#define   G_0288BC_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
-#define   C_0288BC_ITEMSIZE                            0xFFFF8000
-#define R_008C6C_SQ_PSTMP_RING_SIZE                  0x008C6C
-#define   S_008C6C_MEM_SIZE(x)                         (((x) & 0xFFFFFFFF) << 0)
-#define   G_008C6C_MEM_SIZE(x)                         (((x) >> 0) & 0xFFFFFFFF)
-#define   C_008C6C_MEM_SIZE                            0x00000000
-#define R_0288C4_SQ_REDUC_RING_ITEMSIZE              0x0288C4
-#define   S_0288C4_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
-#define   G_0288C4_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
-#define   C_0288C4_ITEMSIZE                            0xFFFF8000
-#define R_008C7C_SQ_REDUC_RING_SIZE                  0x008C7C
-#define   S_008C7C_MEM_SIZE(x)                         (((x) & 0xFFFFFFFF) << 0)
-#define   G_008C7C_MEM_SIZE(x)                         (((x) >> 0) & 0xFFFFFFFF)
-#define   C_008C7C_MEM_SIZE                            0x00000000
-#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE              0x0288B8
-#define   S_0288B8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
-#define   G_0288B8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
-#define   C_0288B8_ITEMSIZE                            0xFFFF8000
-#define R_008C64_SQ_VSTMP_RING_SIZE                  0x008C64
-#define   S_008C64_MEM_SIZE(x)                         (((x) & 0xFFFFFFFF) << 0)
-#define   G_008C64_MEM_SIZE(x)                         (((x) >> 0) & 0xFFFFFFFF)
-#define   C_008C64_MEM_SIZE                            0x00000000
-#define R_0288C8_SQ_GS_VERT_ITEMSIZE                 0x0288C8
-#define   S_0288C8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
-#define   G_0288C8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
-#define   C_0288C8_ITEMSIZE                            0xFFFF8000
-#define R_028010_DB_DEPTH_INFO                       0x028010
-#define   S_028010_FORMAT(x)                           (((x) & 0x7) << 0)
-#define   G_028010_FORMAT(x)                           (((x) >> 0) & 0x7)
-#define   C_028010_FORMAT                              0xFFFFFFF8
-#define     V_028010_DEPTH_INVALID                     0x00000000
-#define     V_028010_DEPTH_16                          0x00000001
-#define     V_028010_DEPTH_X8_24                       0x00000002
-#define     V_028010_DEPTH_8_24                        0x00000003
-#define     V_028010_DEPTH_X8_24_FLOAT                 0x00000004
-#define     V_028010_DEPTH_8_24_FLOAT                  0x00000005
-#define     V_028010_DEPTH_32_FLOAT                    0x00000006
-#define     V_028010_DEPTH_X24_8_32_FLOAT              0x00000007
-#define   S_028010_READ_SIZE(x)                        (((x) & 0x1) << 3)
-#define   G_028010_READ_SIZE(x)                        (((x) >> 3) & 0x1)
-#define   C_028010_READ_SIZE                           0xFFFFFFF7
-#define   S_028010_ARRAY_MODE(x)                       (((x) & 0xF) << 15)
-#define   G_028010_ARRAY_MODE(x)                       (((x) >> 15) & 0xF)
-#define   C_028010_ARRAY_MODE                          0xFFF87FFF
-#define     V_028010_ARRAY_1D_TILED_THIN1              0x00000002
-#define     V_028010_ARRAY_2D_TILED_THIN1              0x00000004
-#define   S_028010_TILE_SURFACE_ENABLE(x)              (((x) & 0x1) << 25)
-#define   G_028010_TILE_SURFACE_ENABLE(x)              (((x) >> 25) & 0x1)
-#define   C_028010_TILE_SURFACE_ENABLE                 0xFDFFFFFF
-#define   S_028010_TILE_COMPACT(x)                     (((x) & 0x1) << 26)
-#define   G_028010_TILE_COMPACT(x)                     (((x) >> 26) & 0x1)
-#define   C_028010_TILE_COMPACT                        0xFBFFFFFF
-#define   S_028010_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
-#define   G_028010_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
-#define   C_028010_ZRANGE_PRECISION                    0x7FFFFFFF
-#define R_028000_DB_DEPTH_SIZE                       0x028000
-#define   S_028000_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
-#define   G_028000_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
-#define   C_028000_PITCH_TILE_MAX                      0xFFFFFC00
-#define   S_028000_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
-#define   G_028000_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
-#define   C_028000_SLICE_TILE_MAX                      0xC00003FF
-#define R_028004_DB_DEPTH_VIEW                       0x028004
-#define   S_028004_SLICE_START(x)                      (((x) & 0x7FF) << 0)
-#define   G_028004_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
-#define   C_028004_SLICE_START                         0xFFFFF800
-#define   S_028004_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
-#define   G_028004_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
-#define   C_028004_SLICE_MAX                           0xFF001FFF
-#define R_028800_DB_DEPTH_CONTROL                    0x028800
-#define   S_028800_STENCIL_ENABLE(x)                   (((x) & 0x1) << 0)
-#define   G_028800_STENCIL_ENABLE(x)                   (((x) >> 0) & 0x1)
-#define   C_028800_STENCIL_ENABLE                      0xFFFFFFFE
-#define   S_028800_Z_ENABLE(x)                         (((x) & 0x1) << 1)
-#define   G_028800_Z_ENABLE(x)                         (((x) >> 1) & 0x1)
-#define   C_028800_Z_ENABLE                            0xFFFFFFFD
-#define   S_028800_Z_WRITE_ENABLE(x)                   (((x) & 0x1) << 2)
-#define   G_028800_Z_WRITE_ENABLE(x)                   (((x) >> 2) & 0x1)
-#define   C_028800_Z_WRITE_ENABLE                      0xFFFFFFFB
-#define   S_028800_ZFUNC(x)                            (((x) & 0x7) << 4)
-#define   G_028800_ZFUNC(x)                            (((x) >> 4) & 0x7)
-#define   C_028800_ZFUNC                               0xFFFFFF8F
-#define   S_028800_BACKFACE_ENABLE(x)                  (((x) & 0x1) << 7)
-#define   G_028800_BACKFACE_ENABLE(x)                  (((x) >> 7) & 0x1)
-#define   C_028800_BACKFACE_ENABLE                     0xFFFFFF7F
-#define   S_028800_STENCILFUNC(x)                      (((x) & 0x7) << 8)
-#define   G_028800_STENCILFUNC(x)                      (((x) >> 8) & 0x7)
-#define   C_028800_STENCILFUNC                         0xFFFFF8FF
-#define   S_028800_STENCILFAIL(x)                      (((x) & 0x7) << 11)
-#define   G_028800_STENCILFAIL(x)                      (((x) >> 11) & 0x7)
-#define   C_028800_STENCILFAIL                         0xFFFFC7FF
-#define   S_028800_STENCILZPASS(x)                     (((x) & 0x7) << 14)
-#define   G_028800_STENCILZPASS(x)                     (((x) >> 14) & 0x7)
-#define   C_028800_STENCILZPASS                        0xFFFE3FFF
-#define   S_028800_STENCILZFAIL(x)                     (((x) & 0x7) << 17)
-#define   G_028800_STENCILZFAIL(x)                     (((x) >> 17) & 0x7)
-#define   C_028800_STENCILZFAIL                        0xFFF1FFFF
-#define   S_028800_STENCILFUNC_BF(x)                   (((x) & 0x7) << 20)
-#define   G_028800_STENCILFUNC_BF(x)                   (((x) >> 20) & 0x7)
-#define   C_028800_STENCILFUNC_BF                      0xFF8FFFFF
-#define   S_028800_STENCILFAIL_BF(x)                   (((x) & 0x7) << 23)
-#define   G_028800_STENCILFAIL_BF(x)                   (((x) >> 23) & 0x7)
-#define   C_028800_STENCILFAIL_BF                      0xFC7FFFFF
-#define   S_028800_STENCILZPASS_BF(x)                  (((x) & 0x7) << 26)
-#define   G_028800_STENCILZPASS_BF(x)                  (((x) >> 26) & 0x7)
-#define   C_028800_STENCILZPASS_BF                     0xE3FFFFFF
-#define   S_028800_STENCILZFAIL_BF(x)                  (((x) & 0x7) << 29)
-#define   G_028800_STENCILZFAIL_BF(x)                  (((x) >> 29) & 0x7)
-#define   C_028800_STENCILZFAIL_BF                     0x1FFFFFFF
-
-#endif
diff --git a/hw/display/radeon.h b/hw/display/radeon.h
deleted file mode 100644
index 32808e50be..0000000000
--- a/hw/display/radeon.h
+++ /dev/null
@@ -1,2967 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RADEON_H__
-#define __RADEON_H__
-
-/* TODO: Here are things that needs to be done :
- *	- surface allocator & initializer : (bit like scratch reg) should
- *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
- *	  related to surface
- *	- WB : write back stuff (do it bit like scratch reg things)
- *	- Vblank : look at Jesse's rework and what we should do
- *	- r600/r700: gart & cp
- *	- cs : clean cs ioctl use bitmap & things like that.
- *	- power management stuff
- *	- Barrier in gart code
- *	- Unmappabled vram ?
- *	- TESTING, TESTING, TESTING
- */
-
-/* Initialization path:
- *  We expect that acceleration initialization might fail for various
- *  reasons even thought we work hard to make it works on most
- *  configurations. In order to still have a working userspace in such
- *  situation the init path must succeed up to the memory controller
- *  initialization point. Failure before this point are considered as
- *  fatal error. Here is the init callchain :
- *      radeon_device_init  perform common structure, mutex initialization
- *      asic_init           setup the GPU memory layout and perform all
- *                          one time initialization (failure in this
- *                          function are considered fatal)
- *      asic_startup        setup the GPU acceleration, in order to
- *                          follow guideline the first thing this
- *                          function should do is setting the GPU
- *                          memory controller (only MC setup failure
- *                          are considered as fatal)
- */
-
-#include <linux/atomic.h>
-#include <linux/wait.h>
-#include <linux/list.h>
-#include <linux/kref.h>
-#include <linux/interval_tree.h>
-#include <linux/hashtable.h>
-#include <linux/dma-fence.h>
-
-#include <drm/ttm/ttm_bo_api.h>
-#include <drm/ttm/ttm_bo_driver.h>
-#include <drm/ttm/ttm_placement.h>
-#include <drm/ttm/ttm_module.h>
-#include <drm/ttm/ttm_execbuf_util.h>
-
-#include <drm/drm_gem.h>
-
-#include "radeon_family.h"
-#include "radeon_mode.h"
-#include "radeon_reg.h"
-
-/*
- * Modules parameters.
- */
-extern int radeon_no_wb;
-extern int radeon_modeset;
-extern int radeon_dynclks;
-extern int radeon_r4xx_atom;
-extern int radeon_agpmode;
-extern int radeon_vram_limit;
-extern int radeon_gart_size;
-extern int radeon_benchmarking;
-extern int radeon_testing;
-extern int radeon_connector_table;
-extern int radeon_tv;
-extern int radeon_audio;
-extern int radeon_disp_priority;
-extern int radeon_hw_i2c;
-extern int radeon_pcie_gen2;
-extern int radeon_msi;
-extern int radeon_lockup_timeout;
-extern int radeon_fastfb;
-extern int radeon_dpm;
-extern int radeon_aspm;
-extern int radeon_runtime_pm;
-extern int radeon_hard_reset;
-extern int radeon_vm_size;
-extern int radeon_vm_block_size;
-extern int radeon_deep_color;
-extern int radeon_use_pflipirq;
-extern int radeon_bapm;
-extern int radeon_backlight;
-extern int radeon_auxch;
-extern int radeon_mst;
-extern int radeon_uvd;
-extern int radeon_vce;
-extern int radeon_si_support;
-extern int radeon_cik_support;
-
-/*
- * Copy from radeon_drv.h so we don't have to include both and have conflicting
- * symbol;
- */
-#define RADEON_MAX_USEC_TIMEOUT			100000	/* 100 ms */
-#define RADEON_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
-#define RADEON_USEC_IB_TEST_TIMEOUT		1000000 /* 1s */
-/* RADEON_IB_POOL_SIZE must be a power of 2 */
-#define RADEON_IB_POOL_SIZE			16
-#define RADEON_DEBUGFS_MAX_COMPONENTS		32
-#define RADEONFB_CONN_LIMIT			4
-#define RADEON_BIOS_NUM_SCRATCH			8
-
-/* internal ring indices */
-/* r1xx+ has gfx CP ring */
-#define RADEON_RING_TYPE_GFX_INDEX		0
-
-/* cayman has 2 compute CP rings */
-#define CAYMAN_RING_TYPE_CP1_INDEX		1
-#define CAYMAN_RING_TYPE_CP2_INDEX		2
-
-/* R600+ has an async dma ring */
-#define R600_RING_TYPE_DMA_INDEX		3
-/* cayman add a second async dma ring */
-#define CAYMAN_RING_TYPE_DMA1_INDEX		4
-
-/* R600+ */
-#define R600_RING_TYPE_UVD_INDEX		5
-
-/* TN+ */
-#define TN_RING_TYPE_VCE1_INDEX			6
-#define TN_RING_TYPE_VCE2_INDEX			7
-
-/* max number of rings */
-#define RADEON_NUM_RINGS			8
-
-/* number of hw syncs before falling back on blocking */
-#define RADEON_NUM_SYNCS			4
-
-/* hardcode those limit for now */
-#define RADEON_VA_IB_OFFSET			(1 << 20)
-#define RADEON_VA_RESERVED_SIZE			(8 << 20)
-#define RADEON_IB_VM_MAX_SIZE			(64 << 10)
-
-/* hard reset data */
-#define RADEON_ASIC_RESET_DATA                  0x39d5e86b
-
-/* reset flags */
-#define RADEON_RESET_GFX			(1 << 0)
-#define RADEON_RESET_COMPUTE			(1 << 1)
-#define RADEON_RESET_DMA			(1 << 2)
-#define RADEON_RESET_CP				(1 << 3)
-#define RADEON_RESET_GRBM			(1 << 4)
-#define RADEON_RESET_DMA1			(1 << 5)
-#define RADEON_RESET_RLC			(1 << 6)
-#define RADEON_RESET_SEM			(1 << 7)
-#define RADEON_RESET_IH				(1 << 8)
-#define RADEON_RESET_VMC			(1 << 9)
-#define RADEON_RESET_MC				(1 << 10)
-#define RADEON_RESET_DISPLAY			(1 << 11)
-
-/* CG block flags */
-#define RADEON_CG_BLOCK_GFX			(1 << 0)
-#define RADEON_CG_BLOCK_MC			(1 << 1)
-#define RADEON_CG_BLOCK_SDMA			(1 << 2)
-#define RADEON_CG_BLOCK_UVD			(1 << 3)
-#define RADEON_CG_BLOCK_VCE			(1 << 4)
-#define RADEON_CG_BLOCK_HDP			(1 << 5)
-#define RADEON_CG_BLOCK_BIF			(1 << 6)
-
-/* CG flags */
-#define RADEON_CG_SUPPORT_GFX_MGCG		(1 << 0)
-#define RADEON_CG_SUPPORT_GFX_MGLS		(1 << 1)
-#define RADEON_CG_SUPPORT_GFX_CGCG		(1 << 2)
-#define RADEON_CG_SUPPORT_GFX_CGLS		(1 << 3)
-#define RADEON_CG_SUPPORT_GFX_CGTS		(1 << 4)
-#define RADEON_CG_SUPPORT_GFX_CGTS_LS		(1 << 5)
-#define RADEON_CG_SUPPORT_GFX_CP_LS		(1 << 6)
-#define RADEON_CG_SUPPORT_GFX_RLC_LS		(1 << 7)
-#define RADEON_CG_SUPPORT_MC_LS			(1 << 8)
-#define RADEON_CG_SUPPORT_MC_MGCG		(1 << 9)
-#define RADEON_CG_SUPPORT_SDMA_LS		(1 << 10)
-#define RADEON_CG_SUPPORT_SDMA_MGCG		(1 << 11)
-#define RADEON_CG_SUPPORT_BIF_LS		(1 << 12)
-#define RADEON_CG_SUPPORT_UVD_MGCG		(1 << 13)
-#define RADEON_CG_SUPPORT_VCE_MGCG		(1 << 14)
-#define RADEON_CG_SUPPORT_HDP_LS		(1 << 15)
-#define RADEON_CG_SUPPORT_HDP_MGCG		(1 << 16)
-
-/* PG flags */
-#define RADEON_PG_SUPPORT_GFX_PG		(1 << 0)
-#define RADEON_PG_SUPPORT_GFX_SMG		(1 << 1)
-#define RADEON_PG_SUPPORT_GFX_DMG		(1 << 2)
-#define RADEON_PG_SUPPORT_UVD			(1 << 3)
-#define RADEON_PG_SUPPORT_VCE			(1 << 4)
-#define RADEON_PG_SUPPORT_CP			(1 << 5)
-#define RADEON_PG_SUPPORT_GDS			(1 << 6)
-#define RADEON_PG_SUPPORT_RLC_SMU_HS		(1 << 7)
-#define RADEON_PG_SUPPORT_SDMA			(1 << 8)
-#define RADEON_PG_SUPPORT_ACP			(1 << 9)
-#define RADEON_PG_SUPPORT_SAMU			(1 << 10)
-
-/* max cursor sizes (in pixels) */
-#define CURSOR_WIDTH 64
-#define CURSOR_HEIGHT 64
-
-#define CIK_CURSOR_WIDTH 128
-#define CIK_CURSOR_HEIGHT 128
-
-/*
- * Errata workarounds.
- */
-enum radeon_pll_errata {
-	CHIP_ERRATA_R300_CG             = 0x00000001,
-	CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
-	CHIP_ERRATA_PLL_DELAY           = 0x00000004
-};
-
-
-struct radeon_device;
-
-
-/*
- * BIOS.
- */
-bool radeon_get_bios(struct radeon_device *rdev);
-
-/*
- * Dummy page
- */
-struct radeon_dummy_page {
-	uint64_t	entry;
-	struct page	*page;
-	dma_addr_t	addr;
-};
-int radeon_dummy_page_init(struct radeon_device *rdev);
-void radeon_dummy_page_fini(struct radeon_device *rdev);
-
-
-/*
- * Clocks
- */
-struct radeon_clock {
-	struct radeon_pll p1pll;
-	struct radeon_pll p2pll;
-	struct radeon_pll dcpll;
-	struct radeon_pll spll;
-	struct radeon_pll mpll;
-	/* 10 Khz units */
-	uint32_t default_mclk;
-	uint32_t default_sclk;
-	uint32_t default_dispclk;
-	uint32_t current_dispclk;
-	uint32_t dp_extclk;
-	uint32_t max_pixel_clock;
-	uint32_t vco_freq;
-};
-
-/*
- * Power management
- */
-int radeon_pm_init(struct radeon_device *rdev);
-int radeon_pm_late_init(struct radeon_device *rdev);
-void radeon_pm_fini(struct radeon_device *rdev);
-void radeon_pm_compute_clocks(struct radeon_device *rdev);
-void radeon_pm_suspend(struct radeon_device *rdev);
-void radeon_pm_resume(struct radeon_device *rdev);
-void radeon_combios_get_power_modes(struct radeon_device *rdev);
-void radeon_atombios_get_power_modes(struct radeon_device *rdev);
-int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
-				   u8 clock_type,
-				   u32 clock,
-				   bool strobe_mode,
-				   struct atom_clock_dividers *dividers);
-int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
-					u32 clock,
-					bool strobe_mode,
-					struct atom_mpll_param *mpll_param);
-void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
-int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
-					  u16 voltage_level, u8 voltage_type,
-					  u32 *gpio_value, u32 *gpio_mask);
-void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
-					 u32 eng_clock, u32 mem_clock);
-int radeon_atom_get_voltage_step(struct radeon_device *rdev,
-				 u8 voltage_type, u16 *voltage_step);
-int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
-			     u16 voltage_id, u16 *voltage);
-int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
-						      u16 *voltage,
-						      u16 leakage_idx);
-int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
-					  u16 *leakage_id);
-int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
-							 u16 *vddc, u16 *vddci,
-							 u16 virtual_voltage_id,
-							 u16 vbios_voltage_id);
-int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
-				u16 virtual_voltage_id,
-				u16 *voltage);
-int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
-				      u8 voltage_type,
-				      u16 nominal_voltage,
-				      u16 *true_voltage);
-int radeon_atom_get_min_voltage(struct radeon_device *rdev,
-				u8 voltage_type, u16 *min_voltage);
-int radeon_atom_get_max_voltage(struct radeon_device *rdev,
-				u8 voltage_type, u16 *max_voltage);
-int radeon_atom_get_voltage_table(struct radeon_device *rdev,
-				  u8 voltage_type, u8 voltage_mode,
-				  struct atom_voltage_table *voltage_table);
-bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
-				 u8 voltage_type, u8 voltage_mode);
-int radeon_atom_get_svi2_info(struct radeon_device *rdev,
-			      u8 voltage_type,
-			      u8 *svd_gpio_id, u8 *svc_gpio_id);
-void radeon_atom_update_memory_dll(struct radeon_device *rdev,
-				   u32 mem_clock);
-void radeon_atom_set_ac_timing(struct radeon_device *rdev,
-			       u32 mem_clock);
-int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
-				  u8 module_index,
-				  struct atom_mc_reg_table *reg_table);
-int radeon_atom_get_memory_info(struct radeon_device *rdev,
-				u8 module_index, struct atom_memory_info *mem_info);
-int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
-				     bool gddr5, u8 module_index,
-				     struct atom_memory_clock_range_table *mclk_range_table);
-int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
-			     u16 voltage_id, u16 *voltage);
-void rs690_pm_info(struct radeon_device *rdev);
-extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
-				    unsigned *bankh, unsigned *mtaspect,
-				    unsigned *tile_split);
-
-/*
- * Fences.
- */
-struct radeon_fence_driver {
-	struct radeon_device		*rdev;
-	uint32_t			scratch_reg;
-	uint64_t			gpu_addr;
-	volatile uint32_t		*cpu_addr;
-	/* sync_seq is protected by ring emission lock */
-	uint64_t			sync_seq[RADEON_NUM_RINGS];
-	atomic64_t			last_seq;
-	bool				initialized, delayed_irq;
-	struct delayed_work		lockup_work;
-};
-
-struct radeon_fence {
-	struct dma_fence		base;
-
-	struct radeon_device	*rdev;
-	uint64_t		seq;
-	/* RB, DMA, etc. */
-	unsigned		ring;
-	bool			is_vm_update;
-
-	wait_queue_entry_t		fence_wake;
-};
-
-int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
-int radeon_fence_driver_init(struct radeon_device *rdev);
-void radeon_fence_driver_fini(struct radeon_device *rdev);
-void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
-int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
-void radeon_fence_process(struct radeon_device *rdev, int ring);
-bool radeon_fence_signaled(struct radeon_fence *fence);
-long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
-int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
-int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
-int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
-int radeon_fence_wait_any(struct radeon_device *rdev,
-			  struct radeon_fence **fences,
-			  bool intr);
-struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
-void radeon_fence_unref(struct radeon_fence **fence);
-unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
-bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
-void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
-static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
-						      struct radeon_fence *b)
-{
-	if (!a) {
-		return b;
-	}
-
-	if (!b) {
-		return a;
-	}
-
-	BUG_ON(a->ring != b->ring);
-
-	if (a->seq > b->seq) {
-		return a;
-	} else {
-		return b;
-	}
-}
-
-static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
-					   struct radeon_fence *b)
-{
-	if (!a) {
-		return false;
-	}
-
-	if (!b) {
-		return true;
-	}
-
-	BUG_ON(a->ring != b->ring);
-
-	return a->seq < b->seq;
-}
-
-/*
- * Tiling registers
- */
-struct radeon_surface_reg {
-	struct radeon_bo *bo;
-};
-
-#define RADEON_GEM_MAX_SURFACES 8
-
-/*
- * TTM.
- */
-struct radeon_mman {
-	struct ttm_bo_device		bdev;
-	bool				initialized;
-
-#if defined(CONFIG_DEBUG_FS)
-	struct dentry			*vram;
-	struct dentry			*gtt;
-#endif
-};
-
-struct radeon_bo_list {
-	struct radeon_bo		*robj;
-	struct ttm_validate_buffer	tv;
-	uint64_t			gpu_offset;
-	unsigned			preferred_domains;
-	unsigned			allowed_domains;
-	uint32_t			tiling_flags;
-};
-
-/* bo virtual address in a specific vm */
-struct radeon_bo_va {
-	/* protected by bo being reserved */
-	struct list_head		bo_list;
-	uint32_t			flags;
-	struct radeon_fence		*last_pt_update;
-	unsigned			ref_count;
-
-	/* protected by vm mutex */
-	struct interval_tree_node	it;
-	struct list_head		vm_status;
-
-	/* constant after initialization */
-	struct radeon_vm		*vm;
-	struct radeon_bo		*bo;
-};
-
-struct radeon_bo {
-	/* Protected by gem.mutex */
-	struct list_head		list;
-	/* Protected by tbo.reserved */
-	u32				initial_domain;
-	struct ttm_place		placements[4];
-	struct ttm_placement		placement;
-	struct ttm_buffer_object	tbo;
-	struct ttm_bo_kmap_obj		kmap;
-	u32				flags;
-	unsigned			pin_count;
-	void				*kptr;
-	u32				tiling_flags;
-	u32				pitch;
-	int				surface_reg;
-	unsigned			prime_shared_count;
-	/* list of all virtual address to which this bo
-	 * is associated to
-	 */
-	struct list_head		va;
-	/* Constant after initialization */
-	struct radeon_device		*rdev;
-	struct drm_gem_object		gem_base;
-
-	struct ttm_bo_kmap_obj		dma_buf_vmap;
-	pid_t				pid;
-
-	struct radeon_mn		*mn;
-	struct list_head		mn_list;
-};
-#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
-
-int radeon_gem_debugfs_init(struct radeon_device *rdev);
-
-/* sub-allocation manager, it has to be protected by another lock.
- * By conception this is an helper for other part of the driver
- * like the indirect buffer or semaphore, which both have their
- * locking.
- *
- * Principe is simple, we keep a list of sub allocation in offset
- * order (first entry has offset == 0, last entry has the highest
- * offset).
- *
- * When allocating new object we first check if there is room at
- * the end total_size - (last_object_offset + last_object_size) >=
- * alloc_size. If so we allocate new object there.
- *
- * When there is not enough room at the end, we start waiting for
- * each sub object until we reach object_offset+object_size >=
- * alloc_size, this object then become the sub object we return.
- *
- * Alignment can't be bigger than page size.
- *
- * Hole are not considered for allocation to keep things simple.
- * Assumption is that there won't be hole (all object on same
- * alignment).
- */
-struct radeon_sa_manager {
-	wait_queue_head_t	wq;
-	struct radeon_bo	*bo;
-	struct list_head	*hole;
-	struct list_head	flist[RADEON_NUM_RINGS];
-	struct list_head	olist;
-	unsigned		size;
-	uint64_t		gpu_addr;
-	void			*cpu_ptr;
-	uint32_t		domain;
-	uint32_t		align;
-};
-
-struct radeon_sa_bo;
-
-/* sub-allocation buffer */
-struct radeon_sa_bo {
-	struct list_head		olist;
-	struct list_head		flist;
-	struct radeon_sa_manager	*manager;
-	unsigned			soffset;
-	unsigned			eoffset;
-	struct radeon_fence		*fence;
-};
-
-/*
- * GEM objects.
- */
-struct radeon_gem {
-	struct mutex		mutex;
-	struct list_head	objects;
-};
-
-int radeon_gem_init(struct radeon_device *rdev);
-void radeon_gem_fini(struct radeon_device *rdev);
-int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
-				int alignment, int initial_domain,
-				u32 flags, bool kernel,
-				struct drm_gem_object **obj);
-
-int radeon_mode_dumb_create(struct drm_file *file_priv,
-			    struct drm_device *dev,
-			    struct drm_mode_create_dumb *args);
-int radeon_mode_dumb_mmap(struct drm_file *filp,
-			  struct drm_device *dev,
-			  uint32_t handle, uint64_t *offset_p);
-
-/*
- * Semaphores.
- */
-struct radeon_semaphore {
-	struct radeon_sa_bo	*sa_bo;
-	signed			waiters;
-	uint64_t		gpu_addr;
-};
-
-int radeon_semaphore_create(struct radeon_device *rdev,
-			    struct radeon_semaphore **semaphore);
-bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
-				  struct radeon_semaphore *semaphore);
-bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
-				struct radeon_semaphore *semaphore);
-void radeon_semaphore_free(struct radeon_device *rdev,
-			   struct radeon_semaphore **semaphore,
-			   struct radeon_fence *fence);
-
-/*
- * Synchronization
- */
-struct radeon_sync {
-	struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
-	struct radeon_fence	*sync_to[RADEON_NUM_RINGS];
-	struct radeon_fence	*last_vm_update;
-};
-
-void radeon_sync_create(struct radeon_sync *sync);
-void radeon_sync_fence(struct radeon_sync *sync,
-		       struct radeon_fence *fence);
-int radeon_sync_resv(struct radeon_device *rdev,
-		     struct radeon_sync *sync,
-		     struct reservation_object *resv,
-		     bool shared);
-int radeon_sync_rings(struct radeon_device *rdev,
-		      struct radeon_sync *sync,
-		      int waiting_ring);
-void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
-		      struct radeon_fence *fence);
-
-/*
- * GART structures, functions & helpers
- */
-struct radeon_mc;
-
-#define RADEON_GPU_PAGE_SIZE 4096
-#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
-#define RADEON_GPU_PAGE_SHIFT 12
-#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
-
-#define RADEON_GART_PAGE_DUMMY  0
-#define RADEON_GART_PAGE_VALID	(1 << 0)
-#define RADEON_GART_PAGE_READ	(1 << 1)
-#define RADEON_GART_PAGE_WRITE	(1 << 2)
-#define RADEON_GART_PAGE_SNOOP	(1 << 3)
-
-struct radeon_gart {
-	dma_addr_t			table_addr;
-	struct radeon_bo		*robj;
-	void				*ptr;
-	unsigned			num_gpu_pages;
-	unsigned			num_cpu_pages;
-	unsigned			table_size;
-	struct page			**pages;
-	uint64_t			*pages_entry;
-	bool				ready;
-};
-
-int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
-void radeon_gart_table_ram_free(struct radeon_device *rdev);
-int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
-void radeon_gart_table_vram_free(struct radeon_device *rdev);
-int radeon_gart_table_vram_pin(struct radeon_device *rdev);
-void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
-int radeon_gart_init(struct radeon_device *rdev);
-void radeon_gart_fini(struct radeon_device *rdev);
-void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
-			int pages);
-int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
-		     int pages, struct page **pagelist,
-		     dma_addr_t *dma_addr, uint32_t flags);
-
-
-/*
- * GPU MC structures, functions & helpers
- */
-struct radeon_mc {
-	resource_size_t		aper_size;
-	resource_size_t		aper_base;
-	resource_size_t		agp_base;
-	/* for some chips with <= 32MB we need to lie
-	 * about vram size near mc fb location */
-	u64			mc_vram_size;
-	u64			visible_vram_size;
-	u64			gtt_size;
-	u64			gtt_start;
-	u64			gtt_end;
-	u64			vram_start;
-	u64			vram_end;
-	unsigned		vram_width;
-	u64			real_vram_size;
-	int			vram_mtrr;
-	bool			vram_is_ddr;
-	bool			igp_sideport_enabled;
-	u64                     gtt_base_align;
-	u64                     mc_mask;
-};
-
-bool radeon_combios_sideport_present(struct radeon_device *rdev);
-bool radeon_atombios_sideport_present(struct radeon_device *rdev);
-
-/*
- * GPU scratch registers structures, functions & helpers
- */
-struct radeon_scratch {
-	unsigned		num_reg;
-	uint32_t                reg_base;
-	bool			free[32];
-	uint32_t		reg[32];
-};
-
-int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
-void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
-
-/*
- * GPU doorbell structures, functions & helpers
- */
-#define RADEON_MAX_DOORBELLS 1024	/* Reserve at most 1024 doorbell slots for radeon-owned rings. */
-
-struct radeon_doorbell {
-	/* doorbell mmio */
-	resource_size_t		base;
-	resource_size_t		size;
-	u32 __iomem		*ptr;
-	u32			num_doorbells;	/* Number of doorbells actually reserved for radeon. */
-	DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
-};
-
-int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
-void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
-
-/*
- * IRQS.
- */
-
-struct radeon_flip_work {
-	struct work_struct		flip_work;
-	struct work_struct		unpin_work;
-	struct radeon_device		*rdev;
-	int				crtc_id;
-	u32				target_vblank;
-	uint64_t			base;
-	struct drm_pending_vblank_event *event;
-	struct radeon_bo		*old_rbo;
-	struct dma_fence		*fence;
-	bool				async;
-};
-
-struct r500_irq_stat_regs {
-	u32 disp_int;
-	u32 hdmi0_status;
-};
-
-struct r600_irq_stat_regs {
-	u32 disp_int;
-	u32 disp_int_cont;
-	u32 disp_int_cont2;
-	u32 d1grph_int;
-	u32 d2grph_int;
-	u32 hdmi0_status;
-	u32 hdmi1_status;
-};
-
-struct evergreen_irq_stat_regs {
-	u32 disp_int[6];
-	u32 grph_int[6];
-	u32 afmt_status[6];
-};
-
-struct cik_irq_stat_regs {
-	u32 disp_int;
-	u32 disp_int_cont;
-	u32 disp_int_cont2;
-	u32 disp_int_cont3;
-	u32 disp_int_cont4;
-	u32 disp_int_cont5;
-	u32 disp_int_cont6;
-	u32 d1grph_int;
-	u32 d2grph_int;
-	u32 d3grph_int;
-	u32 d4grph_int;
-	u32 d5grph_int;
-	u32 d6grph_int;
-};
-
-union radeon_irq_stat_regs {
-	struct r500_irq_stat_regs r500;
-	struct r600_irq_stat_regs r600;
-	struct evergreen_irq_stat_regs evergreen;
-	struct cik_irq_stat_regs cik;
-};
-
-struct radeon_irq {
-	bool				installed;
-	spinlock_t			lock;
-	atomic_t			ring_int[RADEON_NUM_RINGS];
-	bool				crtc_vblank_int[RADEON_MAX_CRTCS];
-	atomic_t			pflip[RADEON_MAX_CRTCS];
-	wait_queue_head_t		vblank_queue;
-	bool				hpd[RADEON_MAX_HPD_PINS];
-	bool				afmt[RADEON_MAX_AFMT_BLOCKS];
-	union radeon_irq_stat_regs	stat_regs;
-	bool				dpm_thermal;
-};
-
-int radeon_irq_kms_init(struct radeon_device *rdev);
-void radeon_irq_kms_fini(struct radeon_device *rdev);
-void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
-bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
-void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
-void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
-void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
-void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
-void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
-void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
-void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
-
-/*
- * CP & rings.
- */
-
-struct radeon_ib {
-	struct radeon_sa_bo		*sa_bo;
-	uint32_t			length_dw;
-	uint64_t			gpu_addr;
-	uint32_t			*ptr;
-	int				ring;
-	struct radeon_fence		*fence;
-	struct radeon_vm		*vm;
-	bool				is_const_ib;
-	struct radeon_sync		sync;
-};
-
-struct radeon_ring {
-	struct radeon_bo	*ring_obj;
-	volatile uint32_t	*ring;
-	unsigned		rptr_offs;
-	unsigned		rptr_save_reg;
-	u64			next_rptr_gpu_addr;
-	volatile u32		*next_rptr_cpu_addr;
-	unsigned		wptr;
-	unsigned		wptr_old;
-	unsigned		ring_size;
-	unsigned		ring_free_dw;
-	int			count_dw;
-	atomic_t		last_rptr;
-	atomic64_t		last_activity;
-	uint64_t		gpu_addr;
-	uint32_t		align_mask;
-	uint32_t		ptr_mask;
-	bool			ready;
-	u32			nop;
-	u32			idx;
-	u64			last_semaphore_signal_addr;
-	u64			last_semaphore_wait_addr;
-	/* for CIK queues */
-	u32 me;
-	u32 pipe;
-	u32 queue;
-	struct radeon_bo	*mqd_obj;
-	u32 doorbell_index;
-	unsigned		wptr_offs;
-};
-
-struct radeon_mec {
-	struct radeon_bo	*hpd_eop_obj;
-	u64			hpd_eop_gpu_addr;
-	u32 num_pipe;
-	u32 num_mec;
-	u32 num_queue;
-};
-
-/*
- * VM
- */
-
-/* maximum number of VMIDs */
-#define RADEON_NUM_VM	16
-
-/* number of entries in page table */
-#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
-
-/* PTBs (Page Table Blocks) need to be aligned to 32K */
-#define RADEON_VM_PTB_ALIGN_SIZE   32768
-#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
-#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
-
-#define R600_PTE_VALID		(1 << 0)
-#define R600_PTE_SYSTEM		(1 << 1)
-#define R600_PTE_SNOOPED	(1 << 2)
-#define R600_PTE_READABLE	(1 << 5)
-#define R600_PTE_WRITEABLE	(1 << 6)
-
-/* PTE (Page Table Entry) fragment field for different page sizes */
-#define R600_PTE_FRAG_4KB	(0 << 7)
-#define R600_PTE_FRAG_64KB	(4 << 7)
-#define R600_PTE_FRAG_256KB	(6 << 7)
-
-/* flags needed to be set so we can copy directly from the GART table */
-#define R600_PTE_GART_MASK	( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
-				  R600_PTE_SYSTEM | R600_PTE_VALID )
-
-struct radeon_vm_pt {
-	struct radeon_bo		*bo;
-	uint64_t			addr;
-};
-
-struct radeon_vm_id {
-	unsigned		id;
-	uint64_t		pd_gpu_addr;
-	/* last flushed PD/PT update */
-	struct radeon_fence	*flushed_updates;
-	/* last use of vmid */
-	struct radeon_fence	*last_id_use;
-};
-
-struct radeon_vm {
-	struct mutex		mutex;
-
-	struct rb_root_cached	va;
-
-	/* protecting invalidated and freed */
-	spinlock_t		status_lock;
-
-	/* BOs moved, but not yet updated in the PT */
-	struct list_head	invalidated;
-
-	/* BOs freed, but not yet updated in the PT */
-	struct list_head	freed;
-
-	/* BOs cleared in the PT */
-	struct list_head	cleared;
-
-	/* contains the page directory */
-	struct radeon_bo	*page_directory;
-	unsigned		max_pde_used;
-
-	/* array of page tables, one for each page directory entry */
-	struct radeon_vm_pt	*page_tables;
-
-	struct radeon_bo_va	*ib_bo_va;
-
-	/* for id and flush management per ring */
-	struct radeon_vm_id	ids[RADEON_NUM_RINGS];
-};
-
-struct radeon_vm_manager {
-	struct radeon_fence		*active[RADEON_NUM_VM];
-	uint32_t			max_pfn;
-	/* number of VMIDs */
-	unsigned			nvm;
-	/* vram base address for page table entry  */
-	u64				vram_base_offset;
-	/* is vm enabled? */
-	bool				enabled;
-	/* for hw to save the PD addr on suspend/resume */
-	uint32_t			saved_table_addr[RADEON_NUM_VM];
-};
-
-/*
- * file private structure
- */
-struct radeon_fpriv {
-	struct radeon_vm		vm;
-};
-
-/*
- * R6xx+ IH ring
- */
-struct r600_ih {
-	struct radeon_bo	*ring_obj;
-	volatile uint32_t	*ring;
-	unsigned		rptr;
-	unsigned		ring_size;
-	uint64_t		gpu_addr;
-	uint32_t		ptr_mask;
-	atomic_t		lock;
-	bool                    enabled;
-};
-
-/*
- * RLC stuff
- */
-#include "clearstate_defs.h"
-
-struct radeon_rlc {
-	/* for power gating */
-	struct radeon_bo	*save_restore_obj;
-	uint64_t		save_restore_gpu_addr;
-	volatile uint32_t	*sr_ptr;
-	const u32               *reg_list;
-	u32                     reg_list_size;
-	/* for clear state */
-	struct radeon_bo	*clear_state_obj;
-	uint64_t		clear_state_gpu_addr;
-	volatile uint32_t	*cs_ptr;
-	const struct cs_section_def   *cs_data;
-	u32                     clear_state_size;
-	/* for cp tables */
-	struct radeon_bo	*cp_table_obj;
-	uint64_t		cp_table_gpu_addr;
-	volatile uint32_t	*cp_table_ptr;
-	u32                     cp_table_size;
-};
-
-int radeon_ib_get(struct radeon_device *rdev, int ring,
-		  struct radeon_ib *ib, struct radeon_vm *vm,
-		  unsigned size);
-void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
-int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
-		       struct radeon_ib *const_ib, bool hdp_flush);
-int radeon_ib_pool_init(struct radeon_device *rdev);
-void radeon_ib_pool_fini(struct radeon_device *rdev);
-int radeon_ib_ring_tests(struct radeon_device *rdev);
-/* Ring access between begin & end cannot sleep */
-bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
-				      struct radeon_ring *ring);
-void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
-int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
-int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
-void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
-			bool hdp_flush);
-void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
-			       bool hdp_flush);
-void radeon_ring_undo(struct radeon_ring *ring);
-void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
-int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
-void radeon_ring_lockup_update(struct radeon_device *rdev,
-			       struct radeon_ring *ring);
-bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
-unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
-			    uint32_t **data);
-int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
-			unsigned size, uint32_t *data);
-int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
-		     unsigned rptr_offs, u32 nop);
-void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
-
-
-/* r600 async dma */
-void r600_dma_stop(struct radeon_device *rdev);
-int r600_dma_resume(struct radeon_device *rdev);
-void r600_dma_fini(struct radeon_device *rdev);
-
-void cayman_dma_stop(struct radeon_device *rdev);
-int cayman_dma_resume(struct radeon_device *rdev);
-void cayman_dma_fini(struct radeon_device *rdev);
-
-/*
- * CS.
- */
-struct radeon_cs_chunk {
-	uint32_t		length_dw;
-	uint32_t		*kdata;
-	void __user		*user_ptr;
-};
-
-struct radeon_cs_parser {
-	struct device		*dev;
-	struct radeon_device	*rdev;
-	struct drm_file		*filp;
-	/* chunks */
-	unsigned		nchunks;
-	struct radeon_cs_chunk	*chunks;
-	uint64_t		*chunks_array;
-	/* IB */
-	unsigned		idx;
-	/* relocations */
-	unsigned		nrelocs;
-	struct radeon_bo_list	*relocs;
-	struct radeon_bo_list	*vm_bos;
-	struct list_head	validated;
-	unsigned		dma_reloc_idx;
-	/* indices of various chunks */
-	struct radeon_cs_chunk  *chunk_ib;
-	struct radeon_cs_chunk  *chunk_relocs;
-	struct radeon_cs_chunk  *chunk_flags;
-	struct radeon_cs_chunk  *chunk_const_ib;
-	struct radeon_ib	ib;
-	struct radeon_ib	const_ib;
-	void			*track;
-	unsigned		family;
-	int			parser_error;
-	u32			cs_flags;
-	u32			ring;
-	s32			priority;
-	struct ww_acquire_ctx	ticket;
-};
-
-static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
-{
-	struct radeon_cs_chunk *ibc = p->chunk_ib;
-
-	if (ibc->kdata)
-		return ibc->kdata[idx];
-	return p->ib.ptr[idx];
-}
-
-
-struct radeon_cs_packet {
-	unsigned	idx;
-	unsigned	type;
-	unsigned	reg;
-	unsigned	opcode;
-	int		count;
-	unsigned	one_reg_wr;
-};
-
-typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
-				      struct radeon_cs_packet *pkt,
-				      unsigned idx, unsigned reg);
-typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
-				      struct radeon_cs_packet *pkt);
-
-
-/*
- * AGP
- */
-int radeon_agp_init(struct radeon_device *rdev);
-void radeon_agp_resume(struct radeon_device *rdev);
-void radeon_agp_suspend(struct radeon_device *rdev);
-void radeon_agp_fini(struct radeon_device *rdev);
-
-
-/*
- * Writeback
- */
-struct radeon_wb {
-	struct radeon_bo	*wb_obj;
-	volatile uint32_t	*wb;
-	uint64_t		gpu_addr;
-	bool                    enabled;
-	bool                    use_event;
-};
-
-#define RADEON_WB_SCRATCH_OFFSET 0
-#define RADEON_WB_RING0_NEXT_RPTR 256
-#define RADEON_WB_CP_RPTR_OFFSET 1024
-#define RADEON_WB_CP1_RPTR_OFFSET 1280
-#define RADEON_WB_CP2_RPTR_OFFSET 1536
-#define R600_WB_DMA_RPTR_OFFSET   1792
-#define R600_WB_IH_WPTR_OFFSET   2048
-#define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
-#define R600_WB_EVENT_OFFSET     3072
-#define CIK_WB_CP1_WPTR_OFFSET     3328
-#define CIK_WB_CP2_WPTR_OFFSET     3584
-#define R600_WB_DMA_RING_TEST_OFFSET 3588
-#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
-
-/**
- * struct radeon_pm - power management datas
- * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
- * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
- * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
- * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
- * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
- * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
- * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
- * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
- * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
- * @sclk:          	GPU clock Mhz (core bandwidth depends of this clock)
- * @needed_bandwidth:   current bandwidth needs
- *
- * It keeps track of various data needed to take powermanagement decision.
- * Bandwidth need is used to determine minimun clock of the GPU and memory.
- * Equation between gpu/memory clock and available bandwidth is hw dependent
- * (type of memory, bus size, efficiency, ...)
- */
-
-enum radeon_pm_method {
-	PM_METHOD_PROFILE,
-	PM_METHOD_DYNPM,
-	PM_METHOD_DPM,
-};
-
-enum radeon_dynpm_state {
-	DYNPM_STATE_DISABLED,
-	DYNPM_STATE_MINIMUM,
-	DYNPM_STATE_PAUSED,
-	DYNPM_STATE_ACTIVE,
-	DYNPM_STATE_SUSPENDED,
-};
-enum radeon_dynpm_action {
-	DYNPM_ACTION_NONE,
-	DYNPM_ACTION_MINIMUM,
-	DYNPM_ACTION_DOWNCLOCK,
-	DYNPM_ACTION_UPCLOCK,
-	DYNPM_ACTION_DEFAULT
-};
-
-enum radeon_voltage_type {
-	VOLTAGE_NONE = 0,
-	VOLTAGE_GPIO,
-	VOLTAGE_VDDC,
-	VOLTAGE_SW
-};
-
-enum radeon_pm_state_type {
-	/* not used for dpm */
-	POWER_STATE_TYPE_DEFAULT,
-	POWER_STATE_TYPE_POWERSAVE,
-	/* user selectable states */
-	POWER_STATE_TYPE_BATTERY,
-	POWER_STATE_TYPE_BALANCED,
-	POWER_STATE_TYPE_PERFORMANCE,
-	/* internal states */
-	POWER_STATE_TYPE_INTERNAL_UVD,
-	POWER_STATE_TYPE_INTERNAL_UVD_SD,
-	POWER_STATE_TYPE_INTERNAL_UVD_HD,
-	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
-	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
-	POWER_STATE_TYPE_INTERNAL_BOOT,
-	POWER_STATE_TYPE_INTERNAL_THERMAL,
-	POWER_STATE_TYPE_INTERNAL_ACPI,
-	POWER_STATE_TYPE_INTERNAL_ULV,
-	POWER_STATE_TYPE_INTERNAL_3DPERF,
-};
-
-enum radeon_pm_profile_type {
-	PM_PROFILE_DEFAULT,
-	PM_PROFILE_AUTO,
-	PM_PROFILE_LOW,
-	PM_PROFILE_MID,
-	PM_PROFILE_HIGH,
-};
-
-#define PM_PROFILE_DEFAULT_IDX 0
-#define PM_PROFILE_LOW_SH_IDX  1
-#define PM_PROFILE_MID_SH_IDX  2
-#define PM_PROFILE_HIGH_SH_IDX 3
-#define PM_PROFILE_LOW_MH_IDX  4
-#define PM_PROFILE_MID_MH_IDX  5
-#define PM_PROFILE_HIGH_MH_IDX 6
-#define PM_PROFILE_MAX         7
-
-struct radeon_pm_profile {
-	int dpms_off_ps_idx;
-	int dpms_on_ps_idx;
-	int dpms_off_cm_idx;
-	int dpms_on_cm_idx;
-};
-
-enum radeon_int_thermal_type {
-	THERMAL_TYPE_NONE,
-	THERMAL_TYPE_EXTERNAL,
-	THERMAL_TYPE_EXTERNAL_GPIO,
-	THERMAL_TYPE_RV6XX,
-	THERMAL_TYPE_RV770,
-	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
-	THERMAL_TYPE_EVERGREEN,
-	THERMAL_TYPE_SUMO,
-	THERMAL_TYPE_NI,
-	THERMAL_TYPE_SI,
-	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
-	THERMAL_TYPE_CI,
-	THERMAL_TYPE_KV,
-};
-
-struct radeon_voltage {
-	enum radeon_voltage_type type;
-	/* gpio voltage */
-	struct radeon_gpio_rec gpio;
-	u32 delay; /* delay in usec from voltage drop to sclk change */
-	bool active_high; /* voltage drop is active when bit is high */
-	/* VDDC voltage */
-	u8 vddc_id; /* index into vddc voltage table */
-	u8 vddci_id; /* index into vddci voltage table */
-	bool vddci_enabled;
-	/* r6xx+ sw */
-	u16 voltage;
-	/* evergreen+ vddci */
-	u16 vddci;
-};
-
-/* clock mode flags */
-#define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
-
-struct radeon_pm_clock_info {
-	/* memory clock */
-	u32 mclk;
-	/* engine clock */
-	u32 sclk;
-	/* voltage info */
-	struct radeon_voltage voltage;
-	/* standardized clock flags */
-	u32 flags;
-};
-
-/* state flags */
-#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
-
-struct radeon_power_state {
-	enum radeon_pm_state_type type;
-	struct radeon_pm_clock_info *clock_info;
-	/* number of valid clock modes in this power state */
-	int num_clock_modes;
-	struct radeon_pm_clock_info *default_clock_mode;
-	/* standardized state flags */
-	u32 flags;
-	u32 misc; /* vbios specific flags */
-	u32 misc2; /* vbios specific flags */
-	int pcie_lanes; /* pcie lanes */
-};
-
-/*
- * Some modes are overclocked by very low value, accept them
- */
-#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
-
-enum radeon_dpm_auto_throttle_src {
-	RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
-	RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
-};
-
-enum radeon_dpm_event_src {
-	RADEON_DPM_EVENT_SRC_ANALOG = 0,
-	RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
-	RADEON_DPM_EVENT_SRC_DIGITAL = 2,
-	RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
-	RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
-};
-
-#define RADEON_MAX_VCE_LEVELS 6
-
-enum radeon_vce_level {
-	RADEON_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
-	RADEON_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
-	RADEON_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
-	RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
-	RADEON_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
-	RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
-};
-
-struct radeon_ps {
-	u32 caps; /* vbios flags */
-	u32 class; /* vbios flags */
-	u32 class2; /* vbios flags */
-	/* UVD clocks */
-	u32 vclk;
-	u32 dclk;
-	/* VCE clocks */
-	u32 evclk;
-	u32 ecclk;
-	bool vce_active;
-	enum radeon_vce_level vce_level;
-	/* asic priv */
-	void *ps_priv;
-};
-
-struct radeon_dpm_thermal {
-	/* thermal interrupt work */
-	struct work_struct work;
-	/* low temperature threshold */
-	int                min_temp;
-	/* high temperature threshold */
-	int                max_temp;
-	/* was interrupt low to high or high to low */
-	bool               high_to_low;
-};
-
-enum radeon_clk_action
-{
-	RADEON_SCLK_UP = 1,
-	RADEON_SCLK_DOWN
-};
-
-struct radeon_blacklist_clocks
-{
-	u32 sclk;
-	u32 mclk;
-	enum radeon_clk_action action;
-};
-
-struct radeon_clock_and_voltage_limits {
-	u32 sclk;
-	u32 mclk;
-	u16 vddc;
-	u16 vddci;
-};
-
-struct radeon_clock_array {
-	u32 count;
-	u32 *values;
-};
-
-struct radeon_clock_voltage_dependency_entry {
-	u32 clk;
-	u16 v;
-};
-
-struct radeon_clock_voltage_dependency_table {
-	u32 count;
-	struct radeon_clock_voltage_dependency_entry *entries;
-};
-
-union radeon_cac_leakage_entry {
-	struct {
-		u16 vddc;
-		u32 leakage;
-	};
-	struct {
-		u16 vddc1;
-		u16 vddc2;
-		u16 vddc3;
-	};
-};
-
-struct radeon_cac_leakage_table {
-	u32 count;
-	union radeon_cac_leakage_entry *entries;
-};
-
-struct radeon_phase_shedding_limits_entry {
-	u16 voltage;
-	u32 sclk;
-	u32 mclk;
-};
-
-struct radeon_phase_shedding_limits_table {
-	u32 count;
-	struct radeon_phase_shedding_limits_entry *entries;
-};
-
-struct radeon_uvd_clock_voltage_dependency_entry {
-	u32 vclk;
-	u32 dclk;
-	u16 v;
-};
-
-struct radeon_uvd_clock_voltage_dependency_table {
-	u8 count;
-	struct radeon_uvd_clock_voltage_dependency_entry *entries;
-};
-
-struct radeon_vce_clock_voltage_dependency_entry {
-	u32 ecclk;
-	u32 evclk;
-	u16 v;
-};
-
-struct radeon_vce_clock_voltage_dependency_table {
-	u8 count;
-	struct radeon_vce_clock_voltage_dependency_entry *entries;
-};
-
-struct radeon_ppm_table {
-	u8 ppm_design;
-	u16 cpu_core_number;
-	u32 platform_tdp;
-	u32 small_ac_platform_tdp;
-	u32 platform_tdc;
-	u32 small_ac_platform_tdc;
-	u32 apu_tdp;
-	u32 dgpu_tdp;
-	u32 dgpu_ulv_power;
-	u32 tj_max;
-};
-
-struct radeon_cac_tdp_table {
-	u16 tdp;
-	u16 configurable_tdp;
-	u16 tdc;
-	u16 battery_power_limit;
-	u16 small_power_limit;
-	u16 low_cac_leakage;
-	u16 high_cac_leakage;
-	u16 maximum_power_delivery_limit;
-};
-
-struct radeon_dpm_dynamic_state {
-	struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
-	struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
-	struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
-	struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
-	struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
-	struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
-	struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
-	struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
-	struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
-	struct radeon_clock_array valid_sclk_values;
-	struct radeon_clock_array valid_mclk_values;
-	struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
-	struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
-	u32 mclk_sclk_ratio;
-	u32 sclk_mclk_delta;
-	u16 vddc_vddci_delta;
-	u16 min_vddc_for_pcie_gen2;
-	struct radeon_cac_leakage_table cac_leakage_table;
-	struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
-	struct radeon_ppm_table *ppm_table;
-	struct radeon_cac_tdp_table *cac_tdp_table;
-};
-
-struct radeon_dpm_fan {
-	u16 t_min;
-	u16 t_med;
-	u16 t_high;
-	u16 pwm_min;
-	u16 pwm_med;
-	u16 pwm_high;
-	u8 t_hyst;
-	u32 cycle_delay;
-	u16 t_max;
-	u8 control_mode;
-	u16 default_max_fan_pwm;
-	u16 default_fan_output_sensitivity;
-	u16 fan_output_sensitivity;
-	bool ucode_fan_control;
-};
-
-enum radeon_pcie_gen {
-	RADEON_PCIE_GEN1 = 0,
-	RADEON_PCIE_GEN2 = 1,
-	RADEON_PCIE_GEN3 = 2,
-	RADEON_PCIE_GEN_INVALID = 0xffff
-};
-
-enum radeon_dpm_forced_level {
-	RADEON_DPM_FORCED_LEVEL_AUTO = 0,
-	RADEON_DPM_FORCED_LEVEL_LOW = 1,
-	RADEON_DPM_FORCED_LEVEL_HIGH = 2,
-};
-
-struct radeon_vce_state {
-	/* vce clocks */
-	u32 evclk;
-	u32 ecclk;
-	/* gpu clocks */
-	u32 sclk;
-	u32 mclk;
-	u8 clk_idx;
-	u8 pstate;
-};
-
-struct radeon_dpm {
-	struct radeon_ps        *ps;
-	/* number of valid power states */
-	int                     num_ps;
-	/* current power state that is active */
-	struct radeon_ps        *current_ps;
-	/* requested power state */
-	struct radeon_ps        *requested_ps;
-	/* boot up power state */
-	struct radeon_ps        *boot_ps;
-	/* default uvd power state */
-	struct radeon_ps        *uvd_ps;
-	/* vce requirements */
-	struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
-	enum radeon_vce_level vce_level;
-	enum radeon_pm_state_type state;
-	enum radeon_pm_state_type user_state;
-	u32                     platform_caps;
-	u32                     voltage_response_time;
-	u32                     backbias_response_time;
-	void                    *priv;
-	u32			new_active_crtcs;
-	int			new_active_crtc_count;
-	u32			current_active_crtcs;
-	int			current_active_crtc_count;
-	bool single_display;
-	struct radeon_dpm_dynamic_state dyn_state;
-	struct radeon_dpm_fan fan;
-	u32 tdp_limit;
-	u32 near_tdp_limit;
-	u32 near_tdp_limit_adjusted;
-	u32 sq_ramping_threshold;
-	u32 cac_leakage;
-	u16 tdp_od_limit;
-	u32 tdp_adjustment;
-	u16 load_line_slope;
-	bool power_control;
-	bool ac_power;
-	/* special states active */
-	bool                    thermal_active;
-	bool                    uvd_active;
-	bool                    vce_active;
-	/* thermal handling */
-	struct radeon_dpm_thermal thermal;
-	/* forced levels */
-	enum radeon_dpm_forced_level forced_level;
-	/* track UVD streams */
-	unsigned sd;
-	unsigned hd;
-};
-
-void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
-void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
-
-struct radeon_pm {
-	struct mutex		mutex;
-	/* write locked while reprogramming mclk */
-	struct rw_semaphore	mclk_lock;
-	u32			active_crtcs;
-	int			active_crtc_count;
-	int			req_vblank;
-	bool			vblank_sync;
-	fixed20_12		max_bandwidth;
-	fixed20_12		igp_sideport_mclk;
-	fixed20_12		igp_system_mclk;
-	fixed20_12		igp_ht_link_clk;
-	fixed20_12		igp_ht_link_width;
-	fixed20_12		k8_bandwidth;
-	fixed20_12		sideport_bandwidth;
-	fixed20_12		ht_bandwidth;
-	fixed20_12		core_bandwidth;
-	fixed20_12		sclk;
-	fixed20_12		mclk;
-	fixed20_12		needed_bandwidth;
-	struct radeon_power_state *power_state;
-	/* number of valid power states */
-	int                     num_power_states;
-	int                     current_power_state_index;
-	int                     current_clock_mode_index;
-	int                     requested_power_state_index;
-	int                     requested_clock_mode_index;
-	int                     default_power_state_index;
-	u32                     current_sclk;
-	u32                     current_mclk;
-	u16                     current_vddc;
-	u16                     current_vddci;
-	u32                     default_sclk;
-	u32                     default_mclk;
-	u16                     default_vddc;
-	u16                     default_vddci;
-	struct radeon_i2c_chan *i2c_bus;
-	/* selected pm method */
-	enum radeon_pm_method     pm_method;
-	/* dynpm power management */
-	struct delayed_work	dynpm_idle_work;
-	enum radeon_dynpm_state	dynpm_state;
-	enum radeon_dynpm_action	dynpm_planned_action;
-	unsigned long		dynpm_action_timeout;
-	bool                    dynpm_can_upclock;
-	bool                    dynpm_can_downclock;
-	/* profile-based power management */
-	enum radeon_pm_profile_type profile;
-	int                     profile_index;
-	struct radeon_pm_profile profiles[PM_PROFILE_MAX];
-	/* internal thermal controller on rv6xx+ */
-	enum radeon_int_thermal_type int_thermal_type;
-	struct device	        *int_hwmon_dev;
-	/* fan control parameters */
-	bool                    no_fan;
-	u8                      fan_pulses_per_revolution;
-	u8                      fan_min_rpm;
-	u8                      fan_max_rpm;
-	/* dpm */
-	bool                    dpm_enabled;
-	bool                    sysfs_initialized;
-	struct radeon_dpm       dpm;
-};
-
-#define RADEON_PCIE_SPEED_25 1
-#define RADEON_PCIE_SPEED_50 2
-#define RADEON_PCIE_SPEED_80 4
-
-int radeon_pm_get_type_index(struct radeon_device *rdev,
-			     enum radeon_pm_state_type ps_type,
-			     int instance);
-/*
- * UVD
- */
-#define RADEON_DEFAULT_UVD_HANDLES	10
-#define RADEON_MAX_UVD_HANDLES		30
-#define RADEON_UVD_STACK_SIZE		(200*1024)
-#define RADEON_UVD_HEAP_SIZE		(256*1024)
-#define RADEON_UVD_SESSION_SIZE		(50*1024)
-
-struct radeon_uvd {
-	bool			fw_header_present;
-	struct radeon_bo	*vcpu_bo;
-	void			*cpu_addr;
-	uint64_t		gpu_addr;
-	unsigned		max_handles;
-	atomic_t		handles[RADEON_MAX_UVD_HANDLES];
-	struct drm_file		*filp[RADEON_MAX_UVD_HANDLES];
-	unsigned		img_size[RADEON_MAX_UVD_HANDLES];
-	struct delayed_work	idle_work;
-};
-
-int radeon_uvd_init(struct radeon_device *rdev);
-void radeon_uvd_fini(struct radeon_device *rdev);
-int radeon_uvd_suspend(struct radeon_device *rdev);
-int radeon_uvd_resume(struct radeon_device *rdev);
-int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
-			      uint32_t handle, struct radeon_fence **fence);
-int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
-			       uint32_t handle, struct radeon_fence **fence);
-void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
-				       uint32_t allowed_domains);
-void radeon_uvd_free_handles(struct radeon_device *rdev,
-			     struct drm_file *filp);
-int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
-void radeon_uvd_note_usage(struct radeon_device *rdev);
-int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
-				  unsigned vclk, unsigned dclk,
-				  unsigned vco_min, unsigned vco_max,
-				  unsigned fb_factor, unsigned fb_mask,
-				  unsigned pd_min, unsigned pd_max,
-				  unsigned pd_even,
-				  unsigned *optimal_fb_div,
-				  unsigned *optimal_vclk_div,
-				  unsigned *optimal_dclk_div);
-int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
-                                unsigned cg_upll_func_cntl);
-
-/*
- * VCE
- */
-#define RADEON_MAX_VCE_HANDLES	16
-
-struct radeon_vce {
-	struct radeon_bo	*vcpu_bo;
-	uint64_t		gpu_addr;
-	unsigned		fw_version;
-	unsigned		fb_version;
-	atomic_t		handles[RADEON_MAX_VCE_HANDLES];
-	struct drm_file		*filp[RADEON_MAX_VCE_HANDLES];
-	unsigned		img_size[RADEON_MAX_VCE_HANDLES];
-	struct delayed_work	idle_work;
-	uint32_t		keyselect;
-};
-
-int radeon_vce_init(struct radeon_device *rdev);
-void radeon_vce_fini(struct radeon_device *rdev);
-int radeon_vce_suspend(struct radeon_device *rdev);
-int radeon_vce_resume(struct radeon_device *rdev);
-int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
-			      uint32_t handle, struct radeon_fence **fence);
-int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
-			       uint32_t handle, struct radeon_fence **fence);
-void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
-void radeon_vce_note_usage(struct radeon_device *rdev);
-int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
-int radeon_vce_cs_parse(struct radeon_cs_parser *p);
-bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
-			       struct radeon_ring *ring,
-			       struct radeon_semaphore *semaphore,
-			       bool emit_wait);
-void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-void radeon_vce_fence_emit(struct radeon_device *rdev,
-			   struct radeon_fence *fence);
-int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
-int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
-
-struct r600_audio_pin {
-	int			channels;
-	int			rate;
-	int			bits_per_sample;
-	u8			status_bits;
-	u8			category_code;
-	u32			offset;
-	bool			connected;
-	u32			id;
-};
-
-struct r600_audio {
-	bool enabled;
-	struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
-	int num_pins;
-	struct radeon_audio_funcs *hdmi_funcs;
-	struct radeon_audio_funcs *dp_funcs;
-	struct radeon_audio_basic_funcs *funcs;
-};
-
-/*
- * Benchmarking
- */
-void radeon_benchmark(struct radeon_device *rdev, int test_number);
-
-
-/*
- * Testing
- */
-void radeon_test_moves(struct radeon_device *rdev);
-void radeon_test_ring_sync(struct radeon_device *rdev,
-			   struct radeon_ring *cpA,
-			   struct radeon_ring *cpB);
-void radeon_test_syncing(struct radeon_device *rdev);
-
-/*
- * MMU Notifier
- */
-#if defined(CONFIG_MMU_NOTIFIER)
-int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
-void radeon_mn_unregister(struct radeon_bo *bo);
-#else
-static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
-{
-	return -ENODEV;
-}
-static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
-#endif
-
-/*
- * Debugfs
- */
-struct radeon_debugfs {
-	struct drm_info_list	*files;
-	unsigned		num_files;
-};
-
-int radeon_debugfs_add_files(struct radeon_device *rdev,
-			     struct drm_info_list *files,
-			     unsigned nfiles);
-int radeon_debugfs_fence_init(struct radeon_device *rdev);
-
-/*
- * ASIC ring specific functions.
- */
-struct radeon_asic_ring {
-	/* ring read/write ptr handling */
-	u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
-	u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
-	void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
-
-	/* validating and patching of IBs */
-	int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
-	int (*cs_parse)(struct radeon_cs_parser *p);
-
-	/* command emmit functions */
-	void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
-	void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
-	void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
-	bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
-			       struct radeon_semaphore *semaphore, bool emit_wait);
-	void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
-			 unsigned vm_id, uint64_t pd_addr);
-
-	/* testing functions */
-	int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
-	int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
-	bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
-
-	/* deprecated */
-	void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
-};
-
-/*
- * ASIC specific functions.
- */
-struct radeon_asic {
-	int (*init)(struct radeon_device *rdev);
-	void (*fini)(struct radeon_device *rdev);
-	int (*resume)(struct radeon_device *rdev);
-	int (*suspend)(struct radeon_device *rdev);
-	void (*vga_set_state)(struct radeon_device *rdev, bool state);
-	int (*asic_reset)(struct radeon_device *rdev, bool hard);
-	/* Flush the HDP cache via MMIO */
-	void (*mmio_hdp_flush)(struct radeon_device *rdev);
-	/* check if 3D engine is idle */
-	bool (*gui_idle)(struct radeon_device *rdev);
-	/* wait for mc_idle */
-	int (*mc_wait_for_idle)(struct radeon_device *rdev);
-	/* get the reference clock */
-	u32 (*get_xclk)(struct radeon_device *rdev);
-	/* get the gpu clock counter */
-	uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
-	/* get register for info ioctl */
-	int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
-	/* gart */
-	struct {
-		void (*tlb_flush)(struct radeon_device *rdev);
-		uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
-		void (*set_page)(struct radeon_device *rdev, unsigned i,
-				 uint64_t entry);
-	} gart;
-	struct {
-		int (*init)(struct radeon_device *rdev);
-		void (*fini)(struct radeon_device *rdev);
-		void (*copy_pages)(struct radeon_device *rdev,
-				   struct radeon_ib *ib,
-				   uint64_t pe, uint64_t src,
-				   unsigned count);
-		void (*write_pages)(struct radeon_device *rdev,
-				    struct radeon_ib *ib,
-				    uint64_t pe,
-				    uint64_t addr, unsigned count,
-				    uint32_t incr, uint32_t flags);
-		void (*set_pages)(struct radeon_device *rdev,
-				  struct radeon_ib *ib,
-				  uint64_t pe,
-				  uint64_t addr, unsigned count,
-				  uint32_t incr, uint32_t flags);
-		void (*pad_ib)(struct radeon_ib *ib);
-	} vm;
-	/* ring specific callbacks */
-	const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
-	/* irqs */
-	struct {
-		int (*set)(struct radeon_device *rdev);
-		int (*process)(struct radeon_device *rdev);
-	} irq;
-	/* displays */
-	struct {
-		/* display watermarks */
-		void (*bandwidth_update)(struct radeon_device *rdev);
-		/* get frame count */
-		u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
-		/* wait for vblank */
-		void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
-		/* set backlight level */
-		void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
-		/* get backlight level */
-		u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
-		/* audio callbacks */
-		void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
-		void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
-	} display;
-	/* copy functions for bo handling */
-	struct {
-		struct radeon_fence *(*blit)(struct radeon_device *rdev,
-					     uint64_t src_offset,
-					     uint64_t dst_offset,
-					     unsigned num_gpu_pages,
-					     struct reservation_object *resv);
-		u32 blit_ring_index;
-		struct radeon_fence *(*dma)(struct radeon_device *rdev,
-					    uint64_t src_offset,
-					    uint64_t dst_offset,
-					    unsigned num_gpu_pages,
-					    struct reservation_object *resv);
-		u32 dma_ring_index;
-		/* method used for bo copy */
-		struct radeon_fence *(*copy)(struct radeon_device *rdev,
-					     uint64_t src_offset,
-					     uint64_t dst_offset,
-					     unsigned num_gpu_pages,
-					     struct reservation_object *resv);
-		/* ring used for bo copies */
-		u32 copy_ring_index;
-	} copy;
-	/* surfaces */
-	struct {
-		int (*set_reg)(struct radeon_device *rdev, int reg,
-				       uint32_t tiling_flags, uint32_t pitch,
-				       uint32_t offset, uint32_t obj_size);
-		void (*clear_reg)(struct radeon_device *rdev, int reg);
-	} surface;
-	/* hotplug detect */
-	struct {
-		void (*init)(struct radeon_device *rdev);
-		void (*fini)(struct radeon_device *rdev);
-		bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
-		void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
-	} hpd;
-	/* static power management */
-	struct {
-		void (*misc)(struct radeon_device *rdev);
-		void (*prepare)(struct radeon_device *rdev);
-		void (*finish)(struct radeon_device *rdev);
-		void (*init_profile)(struct radeon_device *rdev);
-		void (*get_dynpm_state)(struct radeon_device *rdev);
-		uint32_t (*get_engine_clock)(struct radeon_device *rdev);
-		void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
-		uint32_t (*get_memory_clock)(struct radeon_device *rdev);
-		void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
-		int (*get_pcie_lanes)(struct radeon_device *rdev);
-		void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
-		void (*set_clock_gating)(struct radeon_device *rdev, int enable);
-		int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
-		int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
-		int (*get_temperature)(struct radeon_device *rdev);
-	} pm;
-	/* dynamic power management */
-	struct {
-		int (*init)(struct radeon_device *rdev);
-		void (*setup_asic)(struct radeon_device *rdev);
-		int (*enable)(struct radeon_device *rdev);
-		int (*late_enable)(struct radeon_device *rdev);
-		void (*disable)(struct radeon_device *rdev);
-		int (*pre_set_power_state)(struct radeon_device *rdev);
-		int (*set_power_state)(struct radeon_device *rdev);
-		void (*post_set_power_state)(struct radeon_device *rdev);
-		void (*display_configuration_changed)(struct radeon_device *rdev);
-		void (*fini)(struct radeon_device *rdev);
-		u32 (*get_sclk)(struct radeon_device *rdev, bool low);
-		u32 (*get_mclk)(struct radeon_device *rdev, bool low);
-		void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
-		void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
-		int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
-		bool (*vblank_too_short)(struct radeon_device *rdev);
-		void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
-		void (*enable_bapm)(struct radeon_device *rdev, bool enable);
-		void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
-		u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
-		int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
-		int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
-		u32 (*get_current_sclk)(struct radeon_device *rdev);
-		u32 (*get_current_mclk)(struct radeon_device *rdev);
-	} dpm;
-	/* pageflipping */
-	struct {
-		void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
-		bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
-	} pflip;
-};
-
-/*
- * Asic structures
- */
-struct r100_asic {
-	const unsigned		*reg_safe_bm;
-	unsigned		reg_safe_bm_size;
-	u32			hdp_cntl;
-};
-
-struct r300_asic {
-	const unsigned		*reg_safe_bm;
-	unsigned		reg_safe_bm_size;
-	u32			resync_scratch;
-	u32			hdp_cntl;
-};
-
-struct r600_asic {
-	unsigned		max_pipes;
-	unsigned		max_tile_pipes;
-	unsigned		max_simds;
-	unsigned		max_backends;
-	unsigned		max_gprs;
-	unsigned		max_threads;
-	unsigned		max_stack_entries;
-	unsigned		max_hw_contexts;
-	unsigned		max_gs_threads;
-	unsigned		sx_max_export_size;
-	unsigned		sx_max_export_pos_size;
-	unsigned		sx_max_export_smx_size;
-	unsigned		sq_num_cf_insts;
-	unsigned		tiling_nbanks;
-	unsigned		tiling_npipes;
-	unsigned		tiling_group_size;
-	unsigned		tile_config;
-	unsigned		backend_map;
-	unsigned		active_simds;
-};
-
-struct rv770_asic {
-	unsigned		max_pipes;
-	unsigned		max_tile_pipes;
-	unsigned		max_simds;
-	unsigned		max_backends;
-	unsigned		max_gprs;
-	unsigned		max_threads;
-	unsigned		max_stack_entries;
-	unsigned		max_hw_contexts;
-	unsigned		max_gs_threads;
-	unsigned		sx_max_export_size;
-	unsigned		sx_max_export_pos_size;
-	unsigned		sx_max_export_smx_size;
-	unsigned		sq_num_cf_insts;
-	unsigned		sx_num_of_sets;
-	unsigned		sc_prim_fifo_size;
-	unsigned		sc_hiz_tile_fifo_size;
-	unsigned		sc_earlyz_tile_fifo_fize;
-	unsigned		tiling_nbanks;
-	unsigned		tiling_npipes;
-	unsigned		tiling_group_size;
-	unsigned		tile_config;
-	unsigned		backend_map;
-	unsigned		active_simds;
-};
-
-struct evergreen_asic {
-	unsigned num_ses;
-	unsigned max_pipes;
-	unsigned max_tile_pipes;
-	unsigned max_simds;
-	unsigned max_backends;
-	unsigned max_gprs;
-	unsigned max_threads;
-	unsigned max_stack_entries;
-	unsigned max_hw_contexts;
-	unsigned max_gs_threads;
-	unsigned sx_max_export_size;
-	unsigned sx_max_export_pos_size;
-	unsigned sx_max_export_smx_size;
-	unsigned sq_num_cf_insts;
-	unsigned sx_num_of_sets;
-	unsigned sc_prim_fifo_size;
-	unsigned sc_hiz_tile_fifo_size;
-	unsigned sc_earlyz_tile_fifo_size;
-	unsigned tiling_nbanks;
-	unsigned tiling_npipes;
-	unsigned tiling_group_size;
-	unsigned tile_config;
-	unsigned backend_map;
-	unsigned active_simds;
-};
-
-struct cayman_asic {
-	unsigned max_shader_engines;
-	unsigned max_pipes_per_simd;
-	unsigned max_tile_pipes;
-	unsigned max_simds_per_se;
-	unsigned max_backends_per_se;
-	unsigned max_texture_channel_caches;
-	unsigned max_gprs;
-	unsigned max_threads;
-	unsigned max_gs_threads;
-	unsigned max_stack_entries;
-	unsigned sx_num_of_sets;
-	unsigned sx_max_export_size;
-	unsigned sx_max_export_pos_size;
-	unsigned sx_max_export_smx_size;
-	unsigned max_hw_contexts;
-	unsigned sq_num_cf_insts;
-	unsigned sc_prim_fifo_size;
-	unsigned sc_hiz_tile_fifo_size;
-	unsigned sc_earlyz_tile_fifo_size;
-
-	unsigned num_shader_engines;
-	unsigned num_shader_pipes_per_simd;
-	unsigned num_tile_pipes;
-	unsigned num_simds_per_se;
-	unsigned num_backends_per_se;
-	unsigned backend_disable_mask_per_asic;
-	unsigned backend_map;
-	unsigned num_texture_channel_caches;
-	unsigned mem_max_burst_length_bytes;
-	unsigned mem_row_size_in_kb;
-	unsigned shader_engine_tile_size;
-	unsigned num_gpus;
-	unsigned multi_gpu_tile_size;
-
-	unsigned tile_config;
-	unsigned active_simds;
-};
-
-struct si_asic {
-	unsigned max_shader_engines;
-	unsigned max_tile_pipes;
-	unsigned max_cu_per_sh;
-	unsigned max_sh_per_se;
-	unsigned max_backends_per_se;
-	unsigned max_texture_channel_caches;
-	unsigned max_gprs;
-	unsigned max_gs_threads;
-	unsigned max_hw_contexts;
-	unsigned sc_prim_fifo_size_frontend;
-	unsigned sc_prim_fifo_size_backend;
-	unsigned sc_hiz_tile_fifo_size;
-	unsigned sc_earlyz_tile_fifo_size;
-
-	unsigned num_tile_pipes;
-	unsigned backend_enable_mask;
-	unsigned backend_disable_mask_per_asic;
-	unsigned backend_map;
-	unsigned num_texture_channel_caches;
-	unsigned mem_max_burst_length_bytes;
-	unsigned mem_row_size_in_kb;
-	unsigned shader_engine_tile_size;
-	unsigned num_gpus;
-	unsigned multi_gpu_tile_size;
-
-	unsigned tile_config;
-	uint32_t tile_mode_array[32];
-	uint32_t active_cus;
-};
-
-struct cik_asic {
-	unsigned max_shader_engines;
-	unsigned max_tile_pipes;
-	unsigned max_cu_per_sh;
-	unsigned max_sh_per_se;
-	unsigned max_backends_per_se;
-	unsigned max_texture_channel_caches;
-	unsigned max_gprs;
-	unsigned max_gs_threads;
-	unsigned max_hw_contexts;
-	unsigned sc_prim_fifo_size_frontend;
-	unsigned sc_prim_fifo_size_backend;
-	unsigned sc_hiz_tile_fifo_size;
-	unsigned sc_earlyz_tile_fifo_size;
-
-	unsigned num_tile_pipes;
-	unsigned backend_enable_mask;
-	unsigned backend_disable_mask_per_asic;
-	unsigned backend_map;
-	unsigned num_texture_channel_caches;
-	unsigned mem_max_burst_length_bytes;
-	unsigned mem_row_size_in_kb;
-	unsigned shader_engine_tile_size;
-	unsigned num_gpus;
-	unsigned multi_gpu_tile_size;
-
-	unsigned tile_config;
-	uint32_t tile_mode_array[32];
-	uint32_t macrotile_mode_array[16];
-	uint32_t active_cus;
-};
-
-union radeon_asic_config {
-	struct r300_asic	r300;
-	struct r100_asic	r100;
-	struct r600_asic	r600;
-	struct rv770_asic	rv770;
-	struct evergreen_asic	evergreen;
-	struct cayman_asic	cayman;
-	struct si_asic		si;
-	struct cik_asic		cik;
-};
-
-/*
- * asic initizalization from radeon_asic.c
- */
-void radeon_agp_disable(struct radeon_device *rdev);
-int radeon_asic_init(struct radeon_device *rdev);
-
-
-/*
- * IOCTL.
- */
-int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
-			  struct drm_file *filp);
-int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
-			    struct drm_file *filp);
-int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
-			     struct drm_file *filp);
-int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
-			 struct drm_file *file_priv);
-int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
-			   struct drm_file *file_priv);
-int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
-			    struct drm_file *file_priv);
-int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
-			   struct drm_file *file_priv);
-int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
-				struct drm_file *filp);
-int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
-			  struct drm_file *filp);
-int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
-			  struct drm_file *filp);
-int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
-			      struct drm_file *filp);
-int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
-			  struct drm_file *filp);
-int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
-			struct drm_file *filp);
-int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
-int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
-				struct drm_file *filp);
-int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
-				struct drm_file *filp);
-
-/* VRAM scratch page for HDP bug, default vram page */
-struct r600_vram_scratch {
-	struct radeon_bo		*robj;
-	volatile uint32_t		*ptr;
-	u64				gpu_addr;
-};
-
-/*
- * ACPI
- */
-struct radeon_atif_notification_cfg {
-	bool enabled;
-	int command_code;
-};
-
-struct radeon_atif_notifications {
-	bool display_switch;
-	bool expansion_mode_change;
-	bool thermal_state;
-	bool forced_power_state;
-	bool system_power_state;
-	bool display_conf_change;
-	bool px_gfx_switch;
-	bool brightness_change;
-	bool dgpu_display_event;
-};
-
-struct radeon_atif_functions {
-	bool system_params;
-	bool sbios_requests;
-	bool select_active_disp;
-	bool lid_state;
-	bool get_tv_standard;
-	bool set_tv_standard;
-	bool get_panel_expansion_mode;
-	bool set_panel_expansion_mode;
-	bool temperature_change;
-	bool graphics_device_types;
-};
-
-struct radeon_atif {
-	struct radeon_atif_notifications notifications;
-	struct radeon_atif_functions functions;
-	struct radeon_atif_notification_cfg notification_cfg;
-	struct radeon_encoder *encoder_for_bl;
-};
-
-struct radeon_atcs_functions {
-	bool get_ext_state;
-	bool pcie_perf_req;
-	bool pcie_dev_rdy;
-	bool pcie_bus_width;
-};
-
-struct radeon_atcs {
-	struct radeon_atcs_functions functions;
-};
-
-/*
- * Core structure, functions and helpers.
- */
-typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
-typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
-
-struct radeon_device {
-	struct device			*dev;
-	struct drm_device		*ddev;
-	struct pci_dev			*pdev;
-	struct rw_semaphore		exclusive_lock;
-	/* ASIC */
-	union radeon_asic_config	config;
-	enum radeon_family		family;
-	unsigned long			flags;
-	int				usec_timeout;
-	enum radeon_pll_errata		pll_errata;
-	int				num_gb_pipes;
-	int				num_z_pipes;
-	int				disp_priority;
-	/* BIOS */
-	uint8_t				*bios;
-	bool				is_atom_bios;
-	uint16_t			bios_header_start;
-	struct radeon_bo		*stolen_vga_memory;
-	/* Register mmio */
-	resource_size_t			rmmio_base;
-	resource_size_t			rmmio_size;
-	/* protects concurrent MM_INDEX/DATA based register access */
-	spinlock_t mmio_idx_lock;
-	/* protects concurrent SMC based register access */
-	spinlock_t smc_idx_lock;
-	/* protects concurrent PLL register access */
-	spinlock_t pll_idx_lock;
-	/* protects concurrent MC register access */
-	spinlock_t mc_idx_lock;
-	/* protects concurrent PCIE register access */
-	spinlock_t pcie_idx_lock;
-	/* protects concurrent PCIE_PORT register access */
-	spinlock_t pciep_idx_lock;
-	/* protects concurrent PIF register access */
-	spinlock_t pif_idx_lock;
-	/* protects concurrent CG register access */
-	spinlock_t cg_idx_lock;
-	/* protects concurrent UVD register access */
-	spinlock_t uvd_idx_lock;
-	/* protects concurrent RCU register access */
-	spinlock_t rcu_idx_lock;
-	/* protects concurrent DIDT register access */
-	spinlock_t didt_idx_lock;
-	/* protects concurrent ENDPOINT (audio) register access */
-	spinlock_t end_idx_lock;
-	void __iomem			*rmmio;
-	radeon_rreg_t			mc_rreg;
-	radeon_wreg_t			mc_wreg;
-	radeon_rreg_t			pll_rreg;
-	radeon_wreg_t			pll_wreg;
-	uint32_t                        pcie_reg_mask;
-	radeon_rreg_t			pciep_rreg;
-	radeon_wreg_t			pciep_wreg;
-	/* io port */
-	void __iomem                    *rio_mem;
-	resource_size_t			rio_mem_size;
-	struct radeon_clock             clock;
-	struct radeon_mc		mc;
-	struct radeon_gart		gart;
-	struct radeon_mode_info		mode_info;
-	struct radeon_scratch		scratch;
-	struct radeon_doorbell		doorbell;
-	struct radeon_mman		mman;
-	struct radeon_fence_driver	fence_drv[RADEON_NUM_RINGS];
-	wait_queue_head_t		fence_queue;
-	u64				fence_context;
-	struct mutex			ring_lock;
-	struct radeon_ring		ring[RADEON_NUM_RINGS];
-	bool				ib_pool_ready;
-	struct radeon_sa_manager	ring_tmp_bo;
-	struct radeon_irq		irq;
-	struct radeon_asic		*asic;
-	struct radeon_gem		gem;
-	struct radeon_pm		pm;
-	struct radeon_uvd		uvd;
-	struct radeon_vce		vce;
-	uint32_t			bios_scratch[RADEON_BIOS_NUM_SCRATCH];
-	struct radeon_wb		wb;
-	struct radeon_dummy_page	dummy_page;
-	bool				shutdown;
-	bool				need_dma32;
-	bool				need_swiotlb;
-	bool				accel_working;
-	bool				fastfb_working; /* IGP feature*/
-	bool				needs_reset, in_reset;
-	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
-	const struct firmware *me_fw;	/* all family ME firmware */
-	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */
-	const struct firmware *rlc_fw;	/* r6/700 RLC firmware */
-	const struct firmware *mc_fw;	/* NI MC firmware */
-	const struct firmware *ce_fw;	/* SI CE firmware */
-	const struct firmware *mec_fw;	/* CIK MEC firmware */
-	const struct firmware *mec2_fw;	/* KV MEC2 firmware */
-	const struct firmware *sdma_fw;	/* CIK SDMA firmware */
-	const struct firmware *smc_fw;	/* SMC firmware */
-	const struct firmware *uvd_fw;	/* UVD firmware */
-	const struct firmware *vce_fw;	/* VCE firmware */
-	bool new_fw;
-	struct r600_vram_scratch vram_scratch;
-	int msi_enabled; /* msi enabled */
-	struct r600_ih ih; /* r6/700 interrupt ring */
-	struct radeon_rlc rlc;
-	struct radeon_mec mec;
-	struct delayed_work hotplug_work;
-	struct work_struct dp_work;
-	struct work_struct audio_work;
-	int num_crtc; /* number of crtcs */
-	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
-	bool has_uvd;
-	bool has_vce;
-	struct r600_audio audio; /* audio stuff */
-	struct notifier_block acpi_nb;
-	/* only one userspace can use Hyperz features or CMASK at a time */
-	struct drm_file *hyperz_filp;
-	struct drm_file *cmask_filp;
-	/* i2c buses */
-	struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
-	/* debugfs */
-	struct radeon_debugfs	debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
-	unsigned 		debugfs_count;
-	/* virtual memory */
-	struct radeon_vm_manager	vm_manager;
-	struct mutex			gpu_clock_mutex;
-	/* memory stats */
-	atomic64_t			vram_usage;
-	atomic64_t			gtt_usage;
-	atomic64_t			num_bytes_moved;
-	atomic_t			gpu_reset_counter;
-	/* ACPI interface */
-	struct radeon_atif		atif;
-	struct radeon_atcs		atcs;
-	/* srbm instance registers */
-	struct mutex			srbm_mutex;
-	/* clock, powergating flags */
-	u32 cg_flags;
-	u32 pg_flags;
-
-	struct dev_pm_domain vga_pm_domain;
-	bool have_disp_power_ref;
-	u32 px_quirk_flags;
-
-	/* tracking pinned memory */
-	u64 vram_pin_size;
-	u64 gart_pin_size;
-
-	struct mutex	mn_lock;
-	DECLARE_HASHTABLE(mn_hash, 7);
-};
-
-bool radeon_is_px(struct drm_device *dev);
-int radeon_device_init(struct radeon_device *rdev,
-		       struct drm_device *ddev,
-		       struct pci_dev *pdev,
-		       uint32_t flags);
-void radeon_device_fini(struct radeon_device *rdev);
-int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
-
-#define RADEON_MIN_MMIO_SIZE 0x10000
-
-uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
-void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
-				    bool always_indirect)
-{
-	/* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
-	if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
-		return readl(((void __iomem *)rdev->rmmio) + reg);
-	else
-		return r100_mm_rreg_slow(rdev, reg);
-}
-static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
-				bool always_indirect)
-{
-	if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
-		writel(v, ((void __iomem *)rdev->rmmio) + reg);
-	else
-		r100_mm_wreg_slow(rdev, reg, v);
-}
-
-u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
-void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
-
-u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
-void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
-
-/*
- * Cast helper
- */
-extern const struct dma_fence_ops radeon_fence_ops;
-
-static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
-{
-	struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
-
-	if (__f->base.ops == &radeon_fence_ops)
-		return __f;
-
-	return NULL;
-}
-
-/*
- * Registers read & write functions.
- */
-#define RREG8(reg) readb((rdev->rmmio) + (reg))
-#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
-#define RREG16(reg) readw((rdev->rmmio) + (reg))
-#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
-#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
-#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
-#define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n",	\
-			    r100_mm_rreg(rdev, (reg), false))
-#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
-#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
-#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
-#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
-#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
-#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
-#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
-#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
-#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
-#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
-#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
-#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
-#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
-#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
-#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
-#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
-#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
-#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
-#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
-#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
-#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
-#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
-#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
-#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
-#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
-#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
-#define WREG32_P(reg, val, mask)				\
-	do {							\
-		uint32_t tmp_ = RREG32(reg);			\
-		tmp_ &= (mask);					\
-		tmp_ |= ((val) & ~(mask));			\
-		WREG32(reg, tmp_);				\
-	} while (0)
-#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
-#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
-#define WREG32_PLL_P(reg, val, mask)				\
-	do {							\
-		uint32_t tmp_ = RREG32_PLL(reg);		\
-		tmp_ &= (mask);					\
-		tmp_ |= ((val) & ~(mask));			\
-		WREG32_PLL(reg, tmp_);				\
-	} while (0)
-#define WREG32_SMC_P(reg, val, mask)				\
-	do {							\
-		uint32_t tmp_ = RREG32_SMC(reg);		\
-		tmp_ &= (mask);					\
-		tmp_ |= ((val) & ~(mask));			\
-		WREG32_SMC(reg, tmp_);				\
-	} while (0)
-#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
-#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
-#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
-
-#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
-#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
-
-/*
- * Indirect registers accessors.
- * They used to be inlined, but this increases code size by ~65 kbytes.
- * Since each performs a pair of MMIO ops
- * within a spin_lock_irqsave/spin_unlock_irqrestore region,
- * the cost of call+ret is almost negligible. MMIO and locking
- * costs several dozens of cycles each at best, call+ret is ~5 cycles.
- */
-uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
-void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
-void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
-u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
-void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
-u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
-void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
-u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
-void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
-u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
-void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
-u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
-void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
-u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
-void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
-
-void r100_pll_errata_after_index(struct radeon_device *rdev);
-
-
-/*
- * ASICs helpers.
- */
-#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
-			    (rdev->pdev->device == 0x5969))
-#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
-		(rdev->family == CHIP_RV200) || \
-		(rdev->family == CHIP_RS100) || \
-		(rdev->family == CHIP_RS200) || \
-		(rdev->family == CHIP_RV250) || \
-		(rdev->family == CHIP_RV280) || \
-		(rdev->family == CHIP_RS300))
-#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||	\
-		(rdev->family == CHIP_RV350) ||			\
-		(rdev->family == CHIP_R350)  ||			\
-		(rdev->family == CHIP_RV380) ||			\
-		(rdev->family == CHIP_R420)  ||			\
-		(rdev->family == CHIP_R423)  ||			\
-		(rdev->family == CHIP_RV410) ||			\
-		(rdev->family == CHIP_RS400) ||			\
-		(rdev->family == CHIP_RS480))
-#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
-		(rdev->ddev->pdev->device == 0x9443) || \
-		(rdev->ddev->pdev->device == 0x944B) || \
-		(rdev->ddev->pdev->device == 0x9506) || \
-		(rdev->ddev->pdev->device == 0x9509) || \
-		(rdev->ddev->pdev->device == 0x950F) || \
-		(rdev->ddev->pdev->device == 0x689C) || \
-		(rdev->ddev->pdev->device == 0x689D))
-#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
-#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||	\
-			    (rdev->family == CHIP_RS690)  ||	\
-			    (rdev->family == CHIP_RS740)  ||	\
-			    (rdev->family >= CHIP_R600))
-#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
-#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
-#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
-#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
-			     (rdev->flags & RADEON_IS_IGP))
-#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
-#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
-#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
-			     (rdev->flags & RADEON_IS_IGP))
-#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
-#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
-#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
-#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
-#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
-#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
-			     (rdev->family == CHIP_MULLINS))
-
-#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
-			      (rdev->ddev->pdev->device == 0x6850) || \
-			      (rdev->ddev->pdev->device == 0x6858) || \
-			      (rdev->ddev->pdev->device == 0x6859) || \
-			      (rdev->ddev->pdev->device == 0x6840) || \
-			      (rdev->ddev->pdev->device == 0x6841) || \
-			      (rdev->ddev->pdev->device == 0x6842) || \
-			      (rdev->ddev->pdev->device == 0x6843))
-
-/*
- * BIOS helpers.
- */
-#define RBIOS8(i) (rdev->bios[i])
-#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
-#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
-
-int radeon_combios_init(struct radeon_device *rdev);
-void radeon_combios_fini(struct radeon_device *rdev);
-int radeon_atombios_init(struct radeon_device *rdev);
-void radeon_atombios_fini(struct radeon_device *rdev);
-
-
-/*
- * RING helpers.
- */
-
-/**
- * radeon_ring_write - write a value to the ring
- *
- * @ring: radeon_ring structure holding ring information
- * @v: dword (dw) value to write
- *
- * Write a value to the requested ring buffer (all asics).
- */
-static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
-{
-	if (ring->count_dw <= 0)
-		DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
-
-	ring->ring[ring->wptr++] = v;
-	ring->wptr &= ring->ptr_mask;
-	ring->count_dw--;
-	ring->ring_free_dw--;
-}
-
-/*
- * ASICs macro.
- */
-#define radeon_init(rdev) (rdev)->asic->init((rdev))
-#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
-#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
-#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
-#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
-#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
-#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
-#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
-#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
-#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
-#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
-#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
-#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
-#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
-#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
-#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
-#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
-#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
-#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
-#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
-#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
-#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
-#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
-#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
-#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
-#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
-#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
-#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
-#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
-#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
-#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
-#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
-#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
-#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
-#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
-#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
-#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
-#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
-#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
-#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
-#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
-#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
-#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
-#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
-#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
-#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
-#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
-#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
-#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
-#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
-#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
-#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
-#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
-#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
-#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
-#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
-#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
-#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
-#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
-#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
-#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
-#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
-#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
-#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
-#define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
-#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
-#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
-#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
-#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
-#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
-#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
-#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
-#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
-#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
-#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
-#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
-#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
-#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
-#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
-#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
-#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
-#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
-#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
-#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
-#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
-#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
-#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
-#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
-#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
-#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
-#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
-
-/* Common functions */
-/* AGP */
-extern int radeon_gpu_reset(struct radeon_device *rdev);
-extern void radeon_pci_config_reset(struct radeon_device *rdev);
-extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
-extern void radeon_agp_disable(struct radeon_device *rdev);
-extern int radeon_modeset_init(struct radeon_device *rdev);
-extern void radeon_modeset_fini(struct radeon_device *rdev);
-extern bool radeon_card_posted(struct radeon_device *rdev);
-extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
-extern void radeon_update_display_priority(struct radeon_device *rdev);
-extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
-extern void radeon_scratch_init(struct radeon_device *rdev);
-extern void radeon_wb_fini(struct radeon_device *rdev);
-extern int radeon_wb_init(struct radeon_device *rdev);
-extern void radeon_wb_disable(struct radeon_device *rdev);
-extern void radeon_surface_init(struct radeon_device *rdev);
-extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
-extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
-extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
-extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
-extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
-extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
-				     uint32_t flags);
-extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
-extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
-extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
-extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
-extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
-extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
-			      bool fbcon, bool freeze);
-extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
-extern void radeon_program_register_sequence(struct radeon_device *rdev,
-					     const u32 *registers,
-					     const u32 array_size);
-
-/*
- * vm
- */
-int radeon_vm_manager_init(struct radeon_device *rdev);
-void radeon_vm_manager_fini(struct radeon_device *rdev);
-int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
-void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
-struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
-					  struct radeon_vm *vm,
-                                          struct list_head *head);
-struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
-				       struct radeon_vm *vm, int ring);
-void radeon_vm_flush(struct radeon_device *rdev,
-                     struct radeon_vm *vm,
-		     int ring, struct radeon_fence *fence);
-void radeon_vm_fence(struct radeon_device *rdev,
-		     struct radeon_vm *vm,
-		     struct radeon_fence *fence);
-uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
-int radeon_vm_update_page_directory(struct radeon_device *rdev,
-				    struct radeon_vm *vm);
-int radeon_vm_clear_freed(struct radeon_device *rdev,
-			  struct radeon_vm *vm);
-int radeon_vm_clear_invalids(struct radeon_device *rdev,
-			     struct radeon_vm *vm);
-int radeon_vm_bo_update(struct radeon_device *rdev,
-			struct radeon_bo_va *bo_va,
-			struct ttm_mem_reg *mem);
-void radeon_vm_bo_invalidate(struct radeon_device *rdev,
-			     struct radeon_bo *bo);
-struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
-				       struct radeon_bo *bo);
-struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
-				      struct radeon_vm *vm,
-				      struct radeon_bo *bo);
-int radeon_vm_bo_set_addr(struct radeon_device *rdev,
-			  struct radeon_bo_va *bo_va,
-			  uint64_t offset,
-			  uint32_t flags);
-void radeon_vm_bo_rmv(struct radeon_device *rdev,
-		      struct radeon_bo_va *bo_va);
-
-/* audio */
-void r600_audio_update_hdmi(struct work_struct *work);
-struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
-struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
-void r600_audio_enable(struct radeon_device *rdev,
-		       struct r600_audio_pin *pin,
-		       u8 enable_mask);
-void dce6_audio_enable(struct radeon_device *rdev,
-		       struct r600_audio_pin *pin,
-		       u8 enable_mask);
-
-/*
- * R600 vram scratch functions
- */
-int r600_vram_scratch_init(struct radeon_device *rdev);
-void r600_vram_scratch_fini(struct radeon_device *rdev);
-
-/*
- * r600 cs checking helper
- */
-unsigned r600_mip_minify(unsigned size, unsigned level);
-bool r600_fmt_is_valid_color(u32 format);
-bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
-int r600_fmt_get_blocksize(u32 format);
-int r600_fmt_get_nblocksx(u32 format, u32 w);
-int r600_fmt_get_nblocksy(u32 format, u32 h);
-
-/*
- * r600 functions used by radeon_encoder.c
- */
-struct radeon_hdmi_acr {
-	u32 clock;
-
-	int n_32khz;
-	int cts_32khz;
-
-	int n_44_1khz;
-	int cts_44_1khz;
-
-	int n_48khz;
-	int cts_48khz;
-
-};
-
-extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
-
-extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
-				     u32 tiling_pipe_num,
-				     u32 max_rb_num,
-				     u32 total_max_rb_num,
-				     u32 enabled_rb_mask);
-
-/*
- * evergreen functions used by radeon_encoder.c
- */
-
-extern int ni_init_microcode(struct radeon_device *rdev);
-extern int ni_mc_load_microcode(struct radeon_device *rdev);
-
-/* radeon_acpi.c */
-#if defined(CONFIG_ACPI)
-extern int radeon_acpi_init(struct radeon_device *rdev);
-extern void radeon_acpi_fini(struct radeon_device *rdev);
-extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
-extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
-						u8 perf_req, bool advertise);
-extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
-#else
-static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
-static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
-#endif
-
-int radeon_cs_packet_parse(struct radeon_cs_parser *p,
-			   struct radeon_cs_packet *pkt,
-			   unsigned idx);
-bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
-void radeon_cs_dump_packet(struct radeon_cs_parser *p,
-			   struct radeon_cs_packet *pkt);
-int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
-				struct radeon_bo_list **cs_reloc,
-				int nomm);
-int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
-			       uint32_t *vline_start_end,
-			       uint32_t *vline_status);
-
-/* interrupt control register helpers */
-void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
-				      u32 reg, u32 mask,
-				      bool enable, const char *name,
-				      unsigned n);
-
-#include "radeon_object.h"
-
-#endif
diff --git a/hw/display/radeon_acpi.h b/hw/display/radeon_acpi.h
deleted file mode 100644
index 35202a453e..0000000000
--- a/hw/display/radeon_acpi.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/*
- * Copyright 2012 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef RADEON_ACPI_H
-#define RADEON_ACPI_H
-
-struct radeon_device;
-struct acpi_bus_event;
-
-/* AMD hw uses four ACPI control methods:
- * 1. ATIF
- * ARG0: (ACPI_INTEGER) function code
- * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
- * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
- * ATIF provides an entry point for the gfx driver to interact with the sbios.
- * The AMD ACPI notification mechanism uses Notify (VGA, 0x81) or a custom
- * notification. Which notification is used as indicated by the ATIF Control
- * Method GET_SYSTEM_PARAMETERS. When the driver receives Notify (VGA, 0x81) or
- * a custom notification it invokes ATIF Control Method GET_SYSTEM_BIOS_REQUESTS
- * to identify pending System BIOS requests and associated parameters. For
- * example, if one of the pending requests is DISPLAY_SWITCH_REQUEST, the driver
- * will perform display device detection and invoke ATIF Control Method
- * SELECT_ACTIVE_DISPLAYS.
- *
- * 2. ATPX
- * ARG0: (ACPI_INTEGER) function code
- * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
- * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
- * ATPX methods are used on PowerXpress systems to handle mux switching and
- * discrete GPU power control.
- *
- * 3. ATRM
- * ARG0: (ACPI_INTEGER) offset of vbios rom data
- * ARG1: (ACPI_BUFFER) size of the buffer to fill (up to 4K).
- * OUTPUT: (ACPI_BUFFER) output buffer
- * ATRM provides an interfacess to access the discrete GPU vbios image on
- * PowerXpress systems with multiple GPUs.
- *
- * 4. ATCS
- * ARG0: (ACPI_INTEGER) function code
- * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
- * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
- * ATCS provides an interface to AMD chipset specific functionality.
- *
- */
-/* ATIF */
-#define ATIF_FUNCTION_VERIFY_INTERFACE                             0x0
-/* ARG0: ATIF_FUNCTION_VERIFY_INTERFACE
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - version
- * DWORD - supported notifications mask
- * DWORD - supported functions bit vector
- */
-/* Notifications mask */
-#       define ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED               (1 << 0)
-#       define ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED        (1 << 1)
-#       define ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED         (1 << 2)
-#       define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED    (1 << 3)
-#       define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED   (1 << 4)
-#       define ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED          (1 << 5)
-#       define ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED                (1 << 6)
-#       define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED      (1 << 7)
-#       define ATIF_DGPU_DISPLAY_EVENT_SUPPORTED                   (1 << 8)
-/* supported functions vector */
-#       define ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED               (1 << 0)
-#       define ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED            (1 << 1)
-#       define ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED              (1 << 2)
-#       define ATIF_GET_LID_STATE_SUPPORTED                       (1 << 3)
-#       define ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED           (1 << 4)
-#       define ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED             (1 << 5)
-#       define ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED  (1 << 6)
-#       define ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED    (1 << 7)
-#       define ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED     (1 << 12)
-#       define ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED           (1 << 14)
-#       define ATIF_GET_EXTERNAL_GPU_INFORMATION_SUPPORTED        (1 << 20)
-#define ATIF_FUNCTION_GET_SYSTEM_PARAMETERS                        0x1
-/* ARG0: ATIF_FUNCTION_GET_SYSTEM_PARAMETERS
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * DWORD - valid flags mask
- * DWORD - flags
- *
- * OR
- *
- * WORD  - structure size in bytes (includes size field)
- * DWORD - valid flags mask
- * DWORD - flags
- * BYTE  - notify command code
- *
- * flags
- * bits 1:0:
- * 0 - Notify(VGA, 0x81) is not used for notification
- * 1 - Notify(VGA, 0x81) is used for notification
- * 2 - Notify(VGA, n) is used for notification where
- * n (0xd0-0xd9) is specified in notify command code.
- * bit 2:
- * 1 - lid changes not reported though int10
- */
-#define ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS                     0x2
-/* ARG0: ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * DWORD - pending sbios requests
- * BYTE  - panel expansion mode
- * BYTE  - thermal state: target gfx controller
- * BYTE  - thermal state: state id (0: exit state, non-0: state)
- * BYTE  - forced power state: target gfx controller
- * BYTE  - forced power state: state id
- * BYTE  - system power source
- * BYTE  - panel backlight level (0-255)
- */
-/* pending sbios requests */
-#       define ATIF_DISPLAY_SWITCH_REQUEST                         (1 << 0)
-#       define ATIF_EXPANSION_MODE_CHANGE_REQUEST                  (1 << 1)
-#       define ATIF_THERMAL_STATE_CHANGE_REQUEST                   (1 << 2)
-#       define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST              (1 << 3)
-#       define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST             (1 << 4)
-#       define ATIF_DISPLAY_CONF_CHANGE_REQUEST                    (1 << 5)
-#       define ATIF_PX_GFX_SWITCH_REQUEST                          (1 << 6)
-#       define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST                (1 << 7)
-#       define ATIF_DGPU_DISPLAY_EVENT                             (1 << 8)
-/* panel expansion mode */
-#       define ATIF_PANEL_EXPANSION_DISABLE                        0
-#       define ATIF_PANEL_EXPANSION_FULL                           1
-#       define ATIF_PANEL_EXPANSION_ASPECT                         2
-/* target gfx controller */
-#       define ATIF_TARGET_GFX_SINGLE                              0
-#       define ATIF_TARGET_GFX_PX_IGPU                             1
-#       define ATIF_TARGET_GFX_PX_DGPU                             2
-/* system power source */
-#       define ATIF_POWER_SOURCE_AC                                1
-#       define ATIF_POWER_SOURCE_DC                                2
-#       define ATIF_POWER_SOURCE_RESTRICTED_AC_1                   3
-#       define ATIF_POWER_SOURCE_RESTRICTED_AC_2                   4
-#define ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS                       0x3
-/* ARG0: ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - selected displays
- * WORD  - connected displays
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - selected displays
- */
-#       define ATIF_LCD1                                           (1 << 0)
-#       define ATIF_CRT1                                           (1 << 1)
-#       define ATIF_TV                                             (1 << 2)
-#       define ATIF_DFP1                                           (1 << 3)
-#       define ATIF_CRT2                                           (1 << 4)
-#       define ATIF_LCD2                                           (1 << 5)
-#       define ATIF_DFP2                                           (1 << 7)
-#       define ATIF_CV                                             (1 << 8)
-#       define ATIF_DFP3                                           (1 << 9)
-#       define ATIF_DFP4                                           (1 << 10)
-#       define ATIF_DFP5                                           (1 << 11)
-#       define ATIF_DFP6                                           (1 << 12)
-#define ATIF_FUNCTION_GET_LID_STATE                                0x4
-/* ARG0: ATIF_FUNCTION_GET_LID_STATE
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - lid state (0: open, 1: closed)
- *
- * GET_LID_STATE only works at boot and resume, for general lid
- * status, use the kernel provided status
- */
-#define ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS                    0x5
-/* ARG0: ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - 0
- * BYTE  - TV standard
- */
-#       define ATIF_TV_STD_NTSC                                    0
-#       define ATIF_TV_STD_PAL                                     1
-#       define ATIF_TV_STD_PALM                                    2
-#       define ATIF_TV_STD_PAL60                                   3
-#       define ATIF_TV_STD_NTSCJ                                   4
-#       define ATIF_TV_STD_PALCN                                   5
-#       define ATIF_TV_STD_PALN                                    6
-#       define ATIF_TV_STD_SCART_RGB                               9
-#define ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS                      0x6
-/* ARG0: ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - 0
- * BYTE  - TV standard
- * OUTPUT: none
- */
-#define ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS           0x7
-/* ARG0: ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - panel expansion mode
- */
-#define ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS             0x8
-/* ARG0: ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - panel expansion mode
- * OUTPUT: none
- */
-#define ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION              0xD
-/* ARG0: ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - gfx controller id
- * BYTE  - current temperature (degress Celsius)
- * OUTPUT: none
- */
-#define ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES                    0xF
-/* ARG0: ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES
- * ARG1: none
- * OUTPUT:
- * WORD  - number of gfx devices
- * WORD  - device structure size in bytes (excludes device size field)
- * DWORD - flags         \
- * WORD  - bus number     } repeated structure
- * WORD  - device number /
- */
-/* flags */
-#       define ATIF_PX_REMOVABLE_GRAPHICS_DEVICE                   (1 << 0)
-#       define ATIF_XGP_PORT                                       (1 << 1)
-#       define ATIF_VGA_ENABLED_GRAPHICS_DEVICE                    (1 << 2)
-#       define ATIF_XGP_PORT_IN_DOCK                               (1 << 3)
-#define ATIF_FUNCTION_GET_EXTERNAL_GPU_INFORMATION                 0x15
-/* ARG0: ATIF_FUNCTION_GET_EXTERNAL_GPU_INFORMATION
- * ARG1: none
- * OUTPUT:
- * WORD  - number of reported external gfx devices
- * WORD  - device structure size in bytes (excludes device size field)
- * WORD  - flags         \
- * WORD  - bus number    / repeated structure
- */
-/* flags */
-#       define ATIF_EXTERNAL_GRAPHICS_PORT                         (1 << 0)
-
-/* ATPX */
-#define ATPX_FUNCTION_VERIFY_INTERFACE                             0x0
-/* ARG0: ATPX_FUNCTION_VERIFY_INTERFACE
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - version
- * DWORD - supported functions bit vector
- */
-/* supported functions vector */
-#       define ATPX_GET_PX_PARAMETERS_SUPPORTED                    (1 << 0)
-#       define ATPX_POWER_CONTROL_SUPPORTED                        (1 << 1)
-#       define ATPX_DISPLAY_MUX_CONTROL_SUPPORTED                  (1 << 2)
-#       define ATPX_I2C_MUX_CONTROL_SUPPORTED                      (1 << 3)
-#       define ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED (1 << 4)
-#       define ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED   (1 << 5)
-#       define ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED       (1 << 7)
-#       define ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED          (1 << 8)
-#define ATPX_FUNCTION_GET_PX_PARAMETERS                            0x1
-/* ARG0: ATPX_FUNCTION_GET_PX_PARAMETERS
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * DWORD - valid flags mask
- * DWORD - flags
- */
-/* flags */
-#       define ATPX_LVDS_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 0)
-#       define ATPX_CRT1_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 1)
-#       define ATPX_DVI1_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 2)
-#       define ATPX_CRT1_RGB_SIGNAL_MUXED                          (1 << 3)
-#       define ATPX_TV_SIGNAL_MUXED                                (1 << 4)
-#       define ATPX_DFP_SIGNAL_MUXED                               (1 << 5)
-#       define ATPX_SEPARATE_MUX_FOR_I2C                           (1 << 6)
-#       define ATPX_DYNAMIC_PX_SUPPORTED                           (1 << 7)
-#       define ATPX_ACF_NOT_SUPPORTED                              (1 << 8)
-#       define ATPX_FIXED_NOT_SUPPORTED                            (1 << 9)
-#       define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED               (1 << 10)
-#       define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS                    (1 << 11)
-#       define ATPX_DGPU_CAN_DRIVE_DISPLAYS                        (1 << 12)
-#       define ATPX_MS_HYBRID_GFX_SUPPORTED                        (1 << 14)
-#define ATPX_FUNCTION_POWER_CONTROL                                0x2
-/* ARG0: ATPX_FUNCTION_POWER_CONTROL
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - dGPU power state (0: power off, 1: power on)
- * OUTPUT: none
- */
-#define ATPX_FUNCTION_DISPLAY_MUX_CONTROL                          0x3
-/* ARG0: ATPX_FUNCTION_DISPLAY_MUX_CONTROL
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - display mux control (0: iGPU, 1: dGPU)
- * OUTPUT: none
- */
-#       define ATPX_INTEGRATED_GPU                                 0
-#       define ATPX_DISCRETE_GPU                                   1
-#define ATPX_FUNCTION_I2C_MUX_CONTROL                              0x4
-/* ARG0: ATPX_FUNCTION_I2C_MUX_CONTROL
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - i2c/aux/hpd mux control (0: iGPU, 1: dGPU)
- * OUTPUT: none
- */
-#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION    0x5
-/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - target gpu (0: iGPU, 1: dGPU)
- * OUTPUT: none
- */
-#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION      0x6
-/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - target gpu (0: iGPU, 1: dGPU)
- * OUTPUT: none
- */
-#define ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING               0x8
-/* ARG0: ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING
- * ARG1: none
- * OUTPUT:
- * WORD  - number of display connectors
- * WORD  - connector structure size in bytes (excludes connector size field)
- * BYTE  - flags                                                     \
- * BYTE  - ATIF display vector bit position                           } repeated
- * BYTE  - adapter id (0: iGPU, 1-n: dGPU ordered by pcie bus number) } structure
- * WORD  - connector ACPI id                                         /
- */
-/* flags */
-#       define ATPX_DISPLAY_OUTPUT_SUPPORTED_BY_ADAPTER_ID_DEVICE  (1 << 0)
-#       define ATPX_DISPLAY_HPD_SUPPORTED_BY_ADAPTER_ID_DEVICE     (1 << 1)
-#       define ATPX_DISPLAY_I2C_SUPPORTED_BY_ADAPTER_ID_DEVICE     (1 << 2)
-#define ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS                  0x9
-/* ARG0: ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS
- * ARG1: none
- * OUTPUT:
- * WORD  - number of HPD/DDC ports
- * WORD  - port structure size in bytes (excludes port size field)
- * BYTE  - ATIF display vector bit position \
- * BYTE  - hpd id                            } reapeated structure
- * BYTE  - ddc id                           /
- *
- * available on A+A systems only
- */
-/* hpd id */
-#       define ATPX_HPD_NONE                                       0
-#       define ATPX_HPD1                                           1
-#       define ATPX_HPD2                                           2
-#       define ATPX_HPD3                                           3
-#       define ATPX_HPD4                                           4
-#       define ATPX_HPD5                                           5
-#       define ATPX_HPD6                                           6
-/* ddc id */
-#       define ATPX_DDC_NONE                                       0
-#       define ATPX_DDC1                                           1
-#       define ATPX_DDC2                                           2
-#       define ATPX_DDC3                                           3
-#       define ATPX_DDC4                                           4
-#       define ATPX_DDC5                                           5
-#       define ATPX_DDC6                                           6
-#       define ATPX_DDC7                                           7
-#       define ATPX_DDC8                                           8
-
-/* ATCS */
-#define ATCS_FUNCTION_VERIFY_INTERFACE                             0x0
-/* ARG0: ATCS_FUNCTION_VERIFY_INTERFACE
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - version
- * DWORD - supported functions bit vector
- */
-/* supported functions vector */
-#       define ATCS_GET_EXTERNAL_STATE_SUPPORTED                   (1 << 0)
-#       define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED             (1 << 1)
-#       define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED       (1 << 2)
-#       define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED                   (1 << 3)
-#define ATCS_FUNCTION_GET_EXTERNAL_STATE                           0x1
-/* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE
- * ARG1: none
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * DWORD - valid flags mask
- * DWORD - flags (0: undocked, 1: docked)
- */
-/* flags */
-#       define ATCS_DOCKED                                         (1 << 0)
-#define ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST                     0x2
-/* ARG0: ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
- * WORD  - valid flags mask
- * WORD  - flags
- * BYTE  - request type
- * BYTE  - performance request
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - return value
- */
-/* flags */
-#       define ATCS_ADVERTISE_CAPS                                 (1 << 0)
-#       define ATCS_WAIT_FOR_COMPLETION                            (1 << 1)
-/* request type */
-#       define ATCS_PCIE_LINK_SPEED                                1
-/* performance request */
-#       define ATCS_REMOVE                                         0
-#       define ATCS_FORCE_LOW_POWER                                1
-#       define ATCS_PERF_LEVEL_1                                   2 /* PCIE Gen 1 */
-#       define ATCS_PERF_LEVEL_2                                   3 /* PCIE Gen 2 */
-#       define ATCS_PERF_LEVEL_3                                   4 /* PCIE Gen 3 */
-/* return value */
-#       define ATCS_REQUEST_REFUSED                                1
-#       define ATCS_REQUEST_COMPLETE                               2
-#       define ATCS_REQUEST_IN_PROGRESS                            3
-#define ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION               0x3
-/* ARG0: ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION
- * ARG1: none
- * OUTPUT: none
- */
-#define ATCS_FUNCTION_SET_PCIE_BUS_WIDTH                           0x4
-/* ARG0: ATCS_FUNCTION_SET_PCIE_BUS_WIDTH
- * ARG1:
- * WORD  - structure size in bytes (includes size field)
- * WORD  - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
- * BYTE  - number of active lanes
- * OUTPUT:
- * WORD  - structure size in bytes (includes size field)
- * BYTE  - number of active lanes
- */
-
-#endif
diff --git a/hw/display/radeon_asic.h b/hw/display/radeon_asic.h
deleted file mode 100644
index e3f036c20d..0000000000
--- a/hw/display/radeon_asic.h
+++ /dev/null
@@ -1,986 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RADEON_ASIC_H__
-#define __RADEON_ASIC_H__
-
-/*
- * common functions
- */
-uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
-void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
-uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
-void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
-
-uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
-void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
-uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
-void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
-void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
-
-void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
-u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
-void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
-u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
-
-/*
- * r100,rv100,rs100,rv200,rs200
- */
-struct r100_mc_save {
-	u32	GENMO_WT;
-	u32	CRTC_EXT_CNTL;
-	u32	CRTC_GEN_CNTL;
-	u32	CRTC2_GEN_CNTL;
-	u32	CUR_OFFSET;
-	u32	CUR2_OFFSET;
-};
-int r100_init(struct radeon_device *rdev);
-void r100_fini(struct radeon_device *rdev);
-int r100_suspend(struct radeon_device *rdev);
-int r100_resume(struct radeon_device *rdev);
-void r100_vga_set_state(struct radeon_device *rdev, bool state);
-bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
-int r100_asic_reset(struct radeon_device *rdev, bool hard);
-u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
-void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
-uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags);
-void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
-			    uint64_t entry);
-void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
-int r100_irq_set(struct radeon_device *rdev);
-int r100_irq_process(struct radeon_device *rdev);
-void r100_fence_ring_emit(struct radeon_device *rdev,
-			  struct radeon_fence *fence);
-bool r100_semaphore_ring_emit(struct radeon_device *rdev,
-			      struct radeon_ring *cp,
-			      struct radeon_semaphore *semaphore,
-			      bool emit_wait);
-int r100_cs_parse(struct radeon_cs_parser *p);
-void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
-struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
-				    uint64_t src_offset,
-				    uint64_t dst_offset,
-				    unsigned num_gpu_pages,
-				    struct reservation_object *resv);
-int r100_set_surface_reg(struct radeon_device *rdev, int reg,
-			 uint32_t tiling_flags, uint32_t pitch,
-			 uint32_t offset, uint32_t obj_size);
-void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
-void r100_bandwidth_update(struct radeon_device *rdev);
-void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
-void r100_hpd_init(struct radeon_device *rdev);
-void r100_hpd_fini(struct radeon_device *rdev);
-bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
-void r100_hpd_set_polarity(struct radeon_device *rdev,
-			   enum radeon_hpd_id hpd);
-int r100_debugfs_rbbm_init(struct radeon_device *rdev);
-int r100_debugfs_cp_init(struct radeon_device *rdev);
-void r100_cp_disable(struct radeon_device *rdev);
-int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
-void r100_cp_fini(struct radeon_device *rdev);
-int r100_pci_gart_init(struct radeon_device *rdev);
-void r100_pci_gart_fini(struct radeon_device *rdev);
-int r100_pci_gart_enable(struct radeon_device *rdev);
-void r100_pci_gart_disable(struct radeon_device *rdev);
-int r100_debugfs_mc_info_init(struct radeon_device *rdev);
-int r100_gui_wait_for_idle(struct radeon_device *rdev);
-int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
-void r100_irq_disable(struct radeon_device *rdev);
-void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
-void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
-void r100_vram_init_sizes(struct radeon_device *rdev);
-int r100_cp_reset(struct radeon_device *rdev);
-void r100_vga_render_disable(struct radeon_device *rdev);
-void r100_restore_sanity(struct radeon_device *rdev);
-int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
-					 struct radeon_cs_packet *pkt,
-					 struct radeon_bo *robj);
-int r100_cs_parse_packet0(struct radeon_cs_parser *p,
-			  struct radeon_cs_packet *pkt,
-			  const unsigned *auth, unsigned n,
-			  radeon_packet0_check_t check);
-int r100_cs_packet_parse(struct radeon_cs_parser *p,
-			 struct radeon_cs_packet *pkt,
-			 unsigned idx);
-void r100_enable_bm(struct radeon_device *rdev);
-void r100_set_common_regs(struct radeon_device *rdev);
-void r100_bm_disable(struct radeon_device *rdev);
-extern bool r100_gui_idle(struct radeon_device *rdev);
-extern void r100_pm_misc(struct radeon_device *rdev);
-extern void r100_pm_prepare(struct radeon_device *rdev);
-extern void r100_pm_finish(struct radeon_device *rdev);
-extern void r100_pm_init_profile(struct radeon_device *rdev);
-extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
-extern void r100_page_flip(struct radeon_device *rdev, int crtc,
-			   u64 crtc_base, bool async);
-extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc);
-extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
-extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
-
-u32 r100_gfx_get_rptr(struct radeon_device *rdev,
-		      struct radeon_ring *ring);
-u32 r100_gfx_get_wptr(struct radeon_device *rdev,
-		      struct radeon_ring *ring);
-void r100_gfx_set_wptr(struct radeon_device *rdev,
-		       struct radeon_ring *ring);
-
-/*
- * r200,rv250,rs300,rv280
- */
-struct radeon_fence *r200_copy_dma(struct radeon_device *rdev,
-				   uint64_t src_offset,
-				   uint64_t dst_offset,
-				   unsigned num_gpu_pages,
-				   struct reservation_object *resv);
-void r200_set_safe_registers(struct radeon_device *rdev);
-
-/*
- * r300,r350,rv350,rv380
- */
-extern int r300_init(struct radeon_device *rdev);
-extern void r300_fini(struct radeon_device *rdev);
-extern int r300_suspend(struct radeon_device *rdev);
-extern int r300_resume(struct radeon_device *rdev);
-extern int r300_asic_reset(struct radeon_device *rdev, bool hard);
-extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
-extern void r300_fence_ring_emit(struct radeon_device *rdev,
-				struct radeon_fence *fence);
-extern int r300_cs_parse(struct radeon_cs_parser *p);
-extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
-extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags);
-extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
-				     uint64_t entry);
-extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
-extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
-extern void r300_set_reg_safe(struct radeon_device *rdev);
-extern void r300_mc_program(struct radeon_device *rdev);
-extern void r300_mc_init(struct radeon_device *rdev);
-extern void r300_clock_startup(struct radeon_device *rdev);
-extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
-extern int rv370_pcie_gart_init(struct radeon_device *rdev);
-extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
-extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
-extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
-extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
-
-/*
- * r420,r423,rv410
- */
-extern int r420_init(struct radeon_device *rdev);
-extern void r420_fini(struct radeon_device *rdev);
-extern int r420_suspend(struct radeon_device *rdev);
-extern int r420_resume(struct radeon_device *rdev);
-extern void r420_pm_init_profile(struct radeon_device *rdev);
-extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
-extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
-extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
-extern void r420_pipes_init(struct radeon_device *rdev);
-
-/*
- * rs400,rs480
- */
-extern int rs400_init(struct radeon_device *rdev);
-extern void rs400_fini(struct radeon_device *rdev);
-extern int rs400_suspend(struct radeon_device *rdev);
-extern int rs400_resume(struct radeon_device *rdev);
-void rs400_gart_tlb_flush(struct radeon_device *rdev);
-uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags);
-void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
-			 uint64_t entry);
-uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
-void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-int rs400_gart_init(struct radeon_device *rdev);
-int rs400_gart_enable(struct radeon_device *rdev);
-void rs400_gart_adjust_size(struct radeon_device *rdev);
-void rs400_gart_disable(struct radeon_device *rdev);
-void rs400_gart_fini(struct radeon_device *rdev);
-extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
-
-/*
- * rs600.
- */
-extern int rs600_asic_reset(struct radeon_device *rdev, bool hard);
-extern int rs600_init(struct radeon_device *rdev);
-extern void rs600_fini(struct radeon_device *rdev);
-extern int rs600_suspend(struct radeon_device *rdev);
-extern int rs600_resume(struct radeon_device *rdev);
-int rs600_irq_set(struct radeon_device *rdev);
-int rs600_irq_process(struct radeon_device *rdev);
-void rs600_irq_disable(struct radeon_device *rdev);
-u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
-void rs600_gart_tlb_flush(struct radeon_device *rdev);
-uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags);
-void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
-			 uint64_t entry);
-uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
-void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-void rs600_bandwidth_update(struct radeon_device *rdev);
-void rs600_hpd_init(struct radeon_device *rdev);
-void rs600_hpd_fini(struct radeon_device *rdev);
-bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
-void rs600_hpd_set_polarity(struct radeon_device *rdev,
-			    enum radeon_hpd_id hpd);
-extern void rs600_pm_misc(struct radeon_device *rdev);
-extern void rs600_pm_prepare(struct radeon_device *rdev);
-extern void rs600_pm_finish(struct radeon_device *rdev);
-extern void rs600_page_flip(struct radeon_device *rdev, int crtc,
-			    u64 crtc_base, bool async);
-extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc);
-void rs600_set_safe_registers(struct radeon_device *rdev);
-extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
-extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
-
-/*
- * rs690,rs740
- */
-int rs690_init(struct radeon_device *rdev);
-void rs690_fini(struct radeon_device *rdev);
-int rs690_resume(struct radeon_device *rdev);
-int rs690_suspend(struct radeon_device *rdev);
-uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
-void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-void rs690_bandwidth_update(struct radeon_device *rdev);
-void rs690_line_buffer_adjust(struct radeon_device *rdev,
-					struct drm_display_mode *mode1,
-					struct drm_display_mode *mode2);
-extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
-
-/*
- * rv515
- */
-struct rv515_mc_save {
-	u32 vga_render_control;
-	u32 vga_hdp_control;
-	bool crtc_enabled[2];
-};
-
-int rv515_init(struct radeon_device *rdev);
-void rv515_fini(struct radeon_device *rdev);
-uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
-void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
-void rv515_bandwidth_update(struct radeon_device *rdev);
-int rv515_resume(struct radeon_device *rdev);
-int rv515_suspend(struct radeon_device *rdev);
-void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
-void rv515_vga_render_disable(struct radeon_device *rdev);
-void rv515_set_safe_registers(struct radeon_device *rdev);
-void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
-void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
-void rv515_clock_startup(struct radeon_device *rdev);
-void rv515_debugfs(struct radeon_device *rdev);
-int rv515_mc_wait_for_idle(struct radeon_device *rdev);
-
-/*
- * r520,rv530,rv560,rv570,r580
- */
-int r520_init(struct radeon_device *rdev);
-int r520_resume(struct radeon_device *rdev);
-int r520_mc_wait_for_idle(struct radeon_device *rdev);
-
-/*
- * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
- */
-int r600_init(struct radeon_device *rdev);
-void r600_fini(struct radeon_device *rdev);
-int r600_suspend(struct radeon_device *rdev);
-int r600_resume(struct radeon_device *rdev);
-void r600_vga_set_state(struct radeon_device *rdev, bool state);
-int r600_wb_init(struct radeon_device *rdev);
-void r600_wb_fini(struct radeon_device *rdev);
-void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
-uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
-void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-int r600_cs_parse(struct radeon_cs_parser *p);
-int r600_dma_cs_parse(struct radeon_cs_parser *p);
-void r600_fence_ring_emit(struct radeon_device *rdev,
-			  struct radeon_fence *fence);
-bool r600_semaphore_ring_emit(struct radeon_device *rdev,
-			      struct radeon_ring *cp,
-			      struct radeon_semaphore *semaphore,
-			      bool emit_wait);
-void r600_dma_fence_ring_emit(struct radeon_device *rdev,
-			      struct radeon_fence *fence);
-bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
-				  struct radeon_ring *ring,
-				  struct radeon_semaphore *semaphore,
-				  bool emit_wait);
-void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
-bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
-int r600_asic_reset(struct radeon_device *rdev, bool hard);
-int r600_set_surface_reg(struct radeon_device *rdev, int reg,
-			 uint32_t tiling_flags, uint32_t pitch,
-			 uint32_t offset, uint32_t obj_size);
-void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
-int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
-int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
-void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
-int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
-struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
-				     uint64_t src_offset, uint64_t dst_offset,
-				     unsigned num_gpu_pages,
-				     struct reservation_object *resv);
-struct radeon_fence *r600_copy_dma(struct radeon_device *rdev,
-				   uint64_t src_offset, uint64_t dst_offset,
-				   unsigned num_gpu_pages,
-				   struct reservation_object *resv);
-void r600_hpd_init(struct radeon_device *rdev);
-void r600_hpd_fini(struct radeon_device *rdev);
-bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
-void r600_hpd_set_polarity(struct radeon_device *rdev,
-			   enum radeon_hpd_id hpd);
-extern void r600_mmio_hdp_flush(struct radeon_device *rdev);
-extern bool r600_gui_idle(struct radeon_device *rdev);
-extern void r600_pm_misc(struct radeon_device *rdev);
-extern void r600_pm_init_profile(struct radeon_device *rdev);
-extern void rs780_pm_init_profile(struct radeon_device *rdev);
-extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
-extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
-extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
-extern int r600_get_pcie_lanes(struct radeon_device *rdev);
-bool r600_card_posted(struct radeon_device *rdev);
-void r600_cp_stop(struct radeon_device *rdev);
-int r600_cp_start(struct radeon_device *rdev);
-void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
-int r600_cp_resume(struct radeon_device *rdev);
-void r600_cp_fini(struct radeon_device *rdev);
-int r600_count_pipe_bits(uint32_t val);
-int r600_mc_wait_for_idle(struct radeon_device *rdev);
-int r600_pcie_gart_init(struct radeon_device *rdev);
-void r600_scratch_init(struct radeon_device *rdev);
-int r600_init_microcode(struct radeon_device *rdev);
-u32 r600_gfx_get_rptr(struct radeon_device *rdev,
-		      struct radeon_ring *ring);
-u32 r600_gfx_get_wptr(struct radeon_device *rdev,
-		      struct radeon_ring *ring);
-void r600_gfx_set_wptr(struct radeon_device *rdev,
-		       struct radeon_ring *ring);
-int r600_get_allowed_info_register(struct radeon_device *rdev,
-				   u32 reg, u32 *val);
-/* r600 irq */
-int r600_irq_process(struct radeon_device *rdev);
-int r600_irq_init(struct radeon_device *rdev);
-void r600_irq_fini(struct radeon_device *rdev);
-void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
-int r600_irq_set(struct radeon_device *rdev);
-void r600_irq_suspend(struct radeon_device *rdev);
-void r600_disable_interrupts(struct radeon_device *rdev);
-void r600_rlc_stop(struct radeon_device *rdev);
-/* r600 audio */
-void r600_audio_fini(struct radeon_device *rdev);
-void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
-void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
-				    size_t size);
-void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);
-void r600_hdmi_audio_workaround(struct drm_encoder *encoder);
-int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
-void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
-int r600_mc_wait_for_idle(struct radeon_device *rdev);
-u32 r600_get_xclk(struct radeon_device *rdev);
-uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
-int rv6xx_get_temp(struct radeon_device *rdev);
-int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
-int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
-void r600_dpm_post_set_power_state(struct radeon_device *rdev);
-int r600_dpm_late_enable(struct radeon_device *rdev);
-/* r600 dma */
-uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
-			   struct radeon_ring *ring);
-uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
-			   struct radeon_ring *ring);
-void r600_dma_set_wptr(struct radeon_device *rdev,
-		       struct radeon_ring *ring);
-/* rv6xx dpm */
-int rv6xx_dpm_init(struct radeon_device *rdev);
-int rv6xx_dpm_enable(struct radeon_device *rdev);
-void rv6xx_dpm_disable(struct radeon_device *rdev);
-int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
-void rv6xx_setup_asic(struct radeon_device *rdev);
-void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
-void rv6xx_dpm_fini(struct radeon_device *rdev);
-u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
-u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
-void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
-				 struct radeon_ps *ps);
-void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
-						       struct seq_file *m);
-int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
-				      enum radeon_dpm_forced_level level);
-u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev);
-u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev);
-/* rs780 dpm */
-int rs780_dpm_init(struct radeon_device *rdev);
-int rs780_dpm_enable(struct radeon_device *rdev);
-void rs780_dpm_disable(struct radeon_device *rdev);
-int rs780_dpm_set_power_state(struct radeon_device *rdev);
-void rs780_dpm_setup_asic(struct radeon_device *rdev);
-void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
-void rs780_dpm_fini(struct radeon_device *rdev);
-u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
-u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
-void rs780_dpm_print_power_state(struct radeon_device *rdev,
-				 struct radeon_ps *ps);
-void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
-						       struct seq_file *m);
-int rs780_dpm_force_performance_level(struct radeon_device *rdev,
-				      enum radeon_dpm_forced_level level);
-u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev);
-u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev);
-
-/*
- * rv770,rv730,rv710,rv740
- */
-int rv770_init(struct radeon_device *rdev);
-void rv770_fini(struct radeon_device *rdev);
-int rv770_suspend(struct radeon_device *rdev);
-int rv770_resume(struct radeon_device *rdev);
-void rv770_pm_misc(struct radeon_device *rdev);
-void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base,
-		     bool async);
-bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc);
-void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
-void r700_cp_stop(struct radeon_device *rdev);
-void r700_cp_fini(struct radeon_device *rdev);
-struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,
-				    uint64_t src_offset, uint64_t dst_offset,
-				    unsigned num_gpu_pages,
-				    struct reservation_object *resv);
-u32 rv770_get_xclk(struct radeon_device *rdev);
-int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
-int rv770_get_temp(struct radeon_device *rdev);
-/* rv7xx pm */
-int rv770_dpm_init(struct radeon_device *rdev);
-int rv770_dpm_enable(struct radeon_device *rdev);
-int rv770_dpm_late_enable(struct radeon_device *rdev);
-void rv770_dpm_disable(struct radeon_device *rdev);
-int rv770_dpm_set_power_state(struct radeon_device *rdev);
-void rv770_dpm_setup_asic(struct radeon_device *rdev);
-void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
-void rv770_dpm_fini(struct radeon_device *rdev);
-u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
-u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
-void rv770_dpm_print_power_state(struct radeon_device *rdev,
-				 struct radeon_ps *ps);
-void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
-						       struct seq_file *m);
-int rv770_dpm_force_performance_level(struct radeon_device *rdev,
-				      enum radeon_dpm_forced_level level);
-bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
-u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev);
-u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev);
-
-/*
- * evergreen
- */
-struct evergreen_mc_save {
-	u32 vga_render_control;
-	u32 vga_hdp_control;
-	bool crtc_enabled[RADEON_MAX_CRTCS];
-};
-
-void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
-int evergreen_init(struct radeon_device *rdev);
-void evergreen_fini(struct radeon_device *rdev);
-int evergreen_suspend(struct radeon_device *rdev);
-int evergreen_resume(struct radeon_device *rdev);
-bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
-bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
-int evergreen_asic_reset(struct radeon_device *rdev, bool hard);
-void evergreen_bandwidth_update(struct radeon_device *rdev);
-void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-void evergreen_hpd_init(struct radeon_device *rdev);
-void evergreen_hpd_fini(struct radeon_device *rdev);
-bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
-void evergreen_hpd_set_polarity(struct radeon_device *rdev,
-				enum radeon_hpd_id hpd);
-u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
-int evergreen_irq_set(struct radeon_device *rdev);
-int evergreen_irq_process(struct radeon_device *rdev);
-extern int evergreen_cs_parse(struct radeon_cs_parser *p);
-extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
-extern void evergreen_pm_misc(struct radeon_device *rdev);
-extern void evergreen_pm_prepare(struct radeon_device *rdev);
-extern void evergreen_pm_finish(struct radeon_device *rdev);
-extern void sumo_pm_init_profile(struct radeon_device *rdev);
-extern void btc_pm_init_profile(struct radeon_device *rdev);
-int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
-int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
-extern void evergreen_page_flip(struct radeon_device *rdev, int crtc,
-				u64 crtc_base, bool async);
-extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc);
-extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
-void evergreen_disable_interrupt_state(struct radeon_device *rdev);
-int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
-void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
-				   struct radeon_fence *fence);
-void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
-				   struct radeon_ib *ib);
-struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev,
-					uint64_t src_offset, uint64_t dst_offset,
-					unsigned num_gpu_pages,
-					struct reservation_object *resv);
-int evergreen_get_temp(struct radeon_device *rdev);
-int evergreen_get_allowed_info_register(struct radeon_device *rdev,
-					u32 reg, u32 *val);
-int sumo_get_temp(struct radeon_device *rdev);
-int tn_get_temp(struct radeon_device *rdev);
-int cypress_dpm_init(struct radeon_device *rdev);
-void cypress_dpm_setup_asic(struct radeon_device *rdev);
-int cypress_dpm_enable(struct radeon_device *rdev);
-void cypress_dpm_disable(struct radeon_device *rdev);
-int cypress_dpm_set_power_state(struct radeon_device *rdev);
-void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
-void cypress_dpm_fini(struct radeon_device *rdev);
-bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
-int btc_dpm_init(struct radeon_device *rdev);
-void btc_dpm_setup_asic(struct radeon_device *rdev);
-int btc_dpm_enable(struct radeon_device *rdev);
-void btc_dpm_disable(struct radeon_device *rdev);
-int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
-int btc_dpm_set_power_state(struct radeon_device *rdev);
-void btc_dpm_post_set_power_state(struct radeon_device *rdev);
-void btc_dpm_fini(struct radeon_device *rdev);
-u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
-u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
-bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
-void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
-						     struct seq_file *m);
-u32 btc_dpm_get_current_sclk(struct radeon_device *rdev);
-u32 btc_dpm_get_current_mclk(struct radeon_device *rdev);
-int sumo_dpm_init(struct radeon_device *rdev);
-int sumo_dpm_enable(struct radeon_device *rdev);
-int sumo_dpm_late_enable(struct radeon_device *rdev);
-void sumo_dpm_disable(struct radeon_device *rdev);
-int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
-int sumo_dpm_set_power_state(struct radeon_device *rdev);
-void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
-void sumo_dpm_setup_asic(struct radeon_device *rdev);
-void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
-void sumo_dpm_fini(struct radeon_device *rdev);
-u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
-u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
-void sumo_dpm_print_power_state(struct radeon_device *rdev,
-				struct radeon_ps *ps);
-void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
-						      struct seq_file *m);
-int sumo_dpm_force_performance_level(struct radeon_device *rdev,
-				     enum radeon_dpm_forced_level level);
-u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev);
-u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev);
-
-/*
- * cayman
- */
-void cayman_fence_ring_emit(struct radeon_device *rdev,
-			    struct radeon_fence *fence);
-void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
-int cayman_init(struct radeon_device *rdev);
-void cayman_fini(struct radeon_device *rdev);
-int cayman_suspend(struct radeon_device *rdev);
-int cayman_resume(struct radeon_device *rdev);
-int cayman_asic_reset(struct radeon_device *rdev, bool hard);
-void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-int cayman_vm_init(struct radeon_device *rdev);
-void cayman_vm_fini(struct radeon_device *rdev);
-void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
-		     unsigned vm_id, uint64_t pd_addr);
-uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
-int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
-int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
-void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
-				struct radeon_ib *ib);
-bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
-bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
-
-void cayman_dma_vm_copy_pages(struct radeon_device *rdev,
-			      struct radeon_ib *ib,
-			      uint64_t pe, uint64_t src,
-			      unsigned count);
-void cayman_dma_vm_write_pages(struct radeon_device *rdev,
-			       struct radeon_ib *ib,
-			       uint64_t pe,
-			       uint64_t addr, unsigned count,
-			       uint32_t incr, uint32_t flags);
-void cayman_dma_vm_set_pages(struct radeon_device *rdev,
-			     struct radeon_ib *ib,
-			     uint64_t pe,
-			     uint64_t addr, unsigned count,
-			     uint32_t incr, uint32_t flags);
-void cayman_dma_vm_pad_ib(struct radeon_ib *ib);
-
-void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
-			 unsigned vm_id, uint64_t pd_addr);
-
-u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
-			struct radeon_ring *ring);
-u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
-			struct radeon_ring *ring);
-void cayman_gfx_set_wptr(struct radeon_device *rdev,
-			 struct radeon_ring *ring);
-uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
-			     struct radeon_ring *ring);
-uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
-			     struct radeon_ring *ring);
-void cayman_dma_set_wptr(struct radeon_device *rdev,
-			 struct radeon_ring *ring);
-int cayman_get_allowed_info_register(struct radeon_device *rdev,
-				     u32 reg, u32 *val);
-
-int ni_dpm_init(struct radeon_device *rdev);
-void ni_dpm_setup_asic(struct radeon_device *rdev);
-int ni_dpm_enable(struct radeon_device *rdev);
-void ni_dpm_disable(struct radeon_device *rdev);
-int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
-int ni_dpm_set_power_state(struct radeon_device *rdev);
-void ni_dpm_post_set_power_state(struct radeon_device *rdev);
-void ni_dpm_fini(struct radeon_device *rdev);
-u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
-u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
-void ni_dpm_print_power_state(struct radeon_device *rdev,
-			      struct radeon_ps *ps);
-void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
-						    struct seq_file *m);
-int ni_dpm_force_performance_level(struct radeon_device *rdev,
-				   enum radeon_dpm_forced_level level);
-bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
-u32 ni_dpm_get_current_sclk(struct radeon_device *rdev);
-u32 ni_dpm_get_current_mclk(struct radeon_device *rdev);
-int trinity_dpm_init(struct radeon_device *rdev);
-int trinity_dpm_enable(struct radeon_device *rdev);
-int trinity_dpm_late_enable(struct radeon_device *rdev);
-void trinity_dpm_disable(struct radeon_device *rdev);
-int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
-int trinity_dpm_set_power_state(struct radeon_device *rdev);
-void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
-void trinity_dpm_setup_asic(struct radeon_device *rdev);
-void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
-void trinity_dpm_fini(struct radeon_device *rdev);
-u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
-u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
-void trinity_dpm_print_power_state(struct radeon_device *rdev,
-				   struct radeon_ps *ps);
-void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
-							 struct seq_file *m);
-int trinity_dpm_force_performance_level(struct radeon_device *rdev,
-					enum radeon_dpm_forced_level level);
-void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
-u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev);
-u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev);
-int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
-
-/* DCE6 - SI */
-void dce6_bandwidth_update(struct radeon_device *rdev);
-void dce6_audio_fini(struct radeon_device *rdev);
-
-/*
- * si
- */
-void si_fence_ring_emit(struct radeon_device *rdev,
-			struct radeon_fence *fence);
-void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
-int si_init(struct radeon_device *rdev);
-void si_fini(struct radeon_device *rdev);
-int si_suspend(struct radeon_device *rdev);
-int si_resume(struct radeon_device *rdev);
-bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
-bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
-int si_asic_reset(struct radeon_device *rdev, bool hard);
-void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-int si_irq_set(struct radeon_device *rdev);
-int si_irq_process(struct radeon_device *rdev);
-int si_vm_init(struct radeon_device *rdev);
-void si_vm_fini(struct radeon_device *rdev);
-void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
-		 unsigned vm_id, uint64_t pd_addr);
-int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
-struct radeon_fence *si_copy_dma(struct radeon_device *rdev,
-				 uint64_t src_offset, uint64_t dst_offset,
-				 unsigned num_gpu_pages,
-				 struct reservation_object *resv);
-
-void si_dma_vm_copy_pages(struct radeon_device *rdev,
-			  struct radeon_ib *ib,
-			  uint64_t pe, uint64_t src,
-			  unsigned count);
-void si_dma_vm_write_pages(struct radeon_device *rdev,
-			   struct radeon_ib *ib,
-			   uint64_t pe,
-			   uint64_t addr, unsigned count,
-			   uint32_t incr, uint32_t flags);
-void si_dma_vm_set_pages(struct radeon_device *rdev,
-			 struct radeon_ib *ib,
-			 uint64_t pe,
-			 uint64_t addr, unsigned count,
-			 uint32_t incr, uint32_t flags);
-
-void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
-		     unsigned vm_id, uint64_t pd_addr);
-u32 si_get_xclk(struct radeon_device *rdev);
-uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
-int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
-int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
-int si_get_temp(struct radeon_device *rdev);
-int si_get_allowed_info_register(struct radeon_device *rdev,
-				 u32 reg, u32 *val);
-int si_dpm_init(struct radeon_device *rdev);
-void si_dpm_setup_asic(struct radeon_device *rdev);
-int si_dpm_enable(struct radeon_device *rdev);
-int si_dpm_late_enable(struct radeon_device *rdev);
-void si_dpm_disable(struct radeon_device *rdev);
-int si_dpm_pre_set_power_state(struct radeon_device *rdev);
-int si_dpm_set_power_state(struct radeon_device *rdev);
-void si_dpm_post_set_power_state(struct radeon_device *rdev);
-void si_dpm_fini(struct radeon_device *rdev);
-void si_dpm_display_configuration_changed(struct radeon_device *rdev);
-void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
-						    struct seq_file *m);
-int si_dpm_force_performance_level(struct radeon_device *rdev,
-				   enum radeon_dpm_forced_level level);
-int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
-						 u32 *speed);
-int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
-						 u32 speed);
-u32 si_fan_ctrl_get_mode(struct radeon_device *rdev);
-void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);
-u32 si_dpm_get_current_sclk(struct radeon_device *rdev);
-u32 si_dpm_get_current_mclk(struct radeon_device *rdev);
-
-/* DCE8 - CIK */
-void dce8_bandwidth_update(struct radeon_device *rdev);
-
-/*
- * cik
- */
-uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
-u32 cik_get_xclk(struct radeon_device *rdev);
-uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
-void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
-int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
-void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
-			      struct radeon_fence *fence);
-bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
-				  struct radeon_ring *ring,
-				  struct radeon_semaphore *semaphore,
-				  bool emit_wait);
-void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-struct radeon_fence *cik_copy_dma(struct radeon_device *rdev,
-				  uint64_t src_offset, uint64_t dst_offset,
-				  unsigned num_gpu_pages,
-				  struct reservation_object *resv);
-struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
-				    uint64_t src_offset, uint64_t dst_offset,
-				    unsigned num_gpu_pages,
-				    struct reservation_object *resv);
-int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
-int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
-bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
-void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
-			     struct radeon_fence *fence);
-void cik_fence_compute_ring_emit(struct radeon_device *rdev,
-				 struct radeon_fence *fence);
-bool cik_semaphore_ring_emit(struct radeon_device *rdev,
-			     struct radeon_ring *cp,
-			     struct radeon_semaphore *semaphore,
-			     bool emit_wait);
-void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
-int cik_init(struct radeon_device *rdev);
-void cik_fini(struct radeon_device *rdev);
-int cik_suspend(struct radeon_device *rdev);
-int cik_resume(struct radeon_device *rdev);
-bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
-int cik_asic_reset(struct radeon_device *rdev, bool hard);
-void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
-int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
-int cik_irq_set(struct radeon_device *rdev);
-int cik_irq_process(struct radeon_device *rdev);
-int cik_vm_init(struct radeon_device *rdev);
-void cik_vm_fini(struct radeon_device *rdev);
-void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
-		  unsigned vm_id, uint64_t pd_addr);
-
-void cik_sdma_vm_copy_pages(struct radeon_device *rdev,
-			    struct radeon_ib *ib,
-			    uint64_t pe, uint64_t src,
-			    unsigned count);
-void cik_sdma_vm_write_pages(struct radeon_device *rdev,
-			     struct radeon_ib *ib,
-			     uint64_t pe,
-			     uint64_t addr, unsigned count,
-			     uint32_t incr, uint32_t flags);
-void cik_sdma_vm_set_pages(struct radeon_device *rdev,
-			   struct radeon_ib *ib,
-			   uint64_t pe,
-			   uint64_t addr, unsigned count,
-			   uint32_t incr, uint32_t flags);
-void cik_sdma_vm_pad_ib(struct radeon_ib *ib);
-
-void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
-		      unsigned vm_id, uint64_t pd_addr);
-int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
-u32 cik_gfx_get_rptr(struct radeon_device *rdev,
-		     struct radeon_ring *ring);
-u32 cik_gfx_get_wptr(struct radeon_device *rdev,
-		     struct radeon_ring *ring);
-void cik_gfx_set_wptr(struct radeon_device *rdev,
-		      struct radeon_ring *ring);
-u32 cik_compute_get_rptr(struct radeon_device *rdev,
-			 struct radeon_ring *ring);
-u32 cik_compute_get_wptr(struct radeon_device *rdev,
-			 struct radeon_ring *ring);
-void cik_compute_set_wptr(struct radeon_device *rdev,
-			  struct radeon_ring *ring);
-u32 cik_sdma_get_rptr(struct radeon_device *rdev,
-		      struct radeon_ring *ring);
-u32 cik_sdma_get_wptr(struct radeon_device *rdev,
-		      struct radeon_ring *ring);
-void cik_sdma_set_wptr(struct radeon_device *rdev,
-		       struct radeon_ring *ring);
-int ci_get_temp(struct radeon_device *rdev);
-int kv_get_temp(struct radeon_device *rdev);
-int cik_get_allowed_info_register(struct radeon_device *rdev,
-				  u32 reg, u32 *val);
-
-int ci_dpm_init(struct radeon_device *rdev);
-int ci_dpm_enable(struct radeon_device *rdev);
-int ci_dpm_late_enable(struct radeon_device *rdev);
-void ci_dpm_disable(struct radeon_device *rdev);
-int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
-int ci_dpm_set_power_state(struct radeon_device *rdev);
-void ci_dpm_post_set_power_state(struct radeon_device *rdev);
-void ci_dpm_setup_asic(struct radeon_device *rdev);
-void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
-void ci_dpm_fini(struct radeon_device *rdev);
-u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
-u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
-void ci_dpm_print_power_state(struct radeon_device *rdev,
-			      struct radeon_ps *ps);
-void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
-						    struct seq_file *m);
-int ci_dpm_force_performance_level(struct radeon_device *rdev,
-				   enum radeon_dpm_forced_level level);
-bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
-void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
-u32 ci_dpm_get_current_sclk(struct radeon_device *rdev);
-u32 ci_dpm_get_current_mclk(struct radeon_device *rdev);
-
-int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
-						 u32 *speed);
-int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
-						 u32 speed);
-u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev);
-void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);
-
-int kv_dpm_init(struct radeon_device *rdev);
-int kv_dpm_enable(struct radeon_device *rdev);
-int kv_dpm_late_enable(struct radeon_device *rdev);
-void kv_dpm_disable(struct radeon_device *rdev);
-int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
-int kv_dpm_set_power_state(struct radeon_device *rdev);
-void kv_dpm_post_set_power_state(struct radeon_device *rdev);
-void kv_dpm_setup_asic(struct radeon_device *rdev);
-void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
-void kv_dpm_fini(struct radeon_device *rdev);
-u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
-u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
-void kv_dpm_print_power_state(struct radeon_device *rdev,
-			      struct radeon_ps *ps);
-void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
-						    struct seq_file *m);
-int kv_dpm_force_performance_level(struct radeon_device *rdev,
-				   enum radeon_dpm_forced_level level);
-void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
-void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
-u32 kv_dpm_get_current_sclk(struct radeon_device *rdev);
-u32 kv_dpm_get_current_mclk(struct radeon_device *rdev);
-
-/* uvd v1.0 */
-uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
-                           struct radeon_ring *ring);
-uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
-                           struct radeon_ring *ring);
-void uvd_v1_0_set_wptr(struct radeon_device *rdev,
-                       struct radeon_ring *ring);
-int uvd_v1_0_resume(struct radeon_device *rdev);
-
-int uvd_v1_0_init(struct radeon_device *rdev);
-void uvd_v1_0_fini(struct radeon_device *rdev);
-int uvd_v1_0_start(struct radeon_device *rdev);
-void uvd_v1_0_stop(struct radeon_device *rdev);
-
-int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
-void uvd_v1_0_fence_emit(struct radeon_device *rdev,
-			 struct radeon_fence *fence);
-int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
-bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
-			     struct radeon_ring *ring,
-			     struct radeon_semaphore *semaphore,
-			     bool emit_wait);
-void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-
-/* uvd v2.2 */
-int uvd_v2_2_resume(struct radeon_device *rdev);
-void uvd_v2_2_fence_emit(struct radeon_device *rdev,
-			 struct radeon_fence *fence);
-bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
-			     struct radeon_ring *ring,
-			     struct radeon_semaphore *semaphore,
-			     bool emit_wait);
-
-/* uvd v3.1 */
-bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
-			     struct radeon_ring *ring,
-			     struct radeon_semaphore *semaphore,
-			     bool emit_wait);
-
-/* uvd v4.2 */
-int uvd_v4_2_resume(struct radeon_device *rdev);
-
-/* vce v1.0 */
-uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
-			   struct radeon_ring *ring);
-uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
-			   struct radeon_ring *ring);
-void vce_v1_0_set_wptr(struct radeon_device *rdev,
-		       struct radeon_ring *ring);
-int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data);
-unsigned vce_v1_0_bo_size(struct radeon_device *rdev);
-int vce_v1_0_resume(struct radeon_device *rdev);
-int vce_v1_0_init(struct radeon_device *rdev);
-int vce_v1_0_start(struct radeon_device *rdev);
-
-/* vce v2.0 */
-unsigned vce_v2_0_bo_size(struct radeon_device *rdev);
-int vce_v2_0_resume(struct radeon_device *rdev);
-
-#endif
diff --git a/hw/display/radeon_drv.h b/hw/display/radeon_drv.h
deleted file mode 100644
index 173deb4634..0000000000
--- a/hw/display/radeon_drv.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Kevin E. Martin <martin@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __RADEON_DRV_H__
-#define __RADEON_DRV_H__
-
-#include <linux/firmware.h>
-#include <linux/platform_device.h>
-#include <drm/drm_legacy.h>
-
-#include "radeon_family.h"
-
-/* General customization:
- */
-
-#define DRIVER_AUTHOR		"Gareth Hughes, Keith Whitwell, others."
-
-#define DRIVER_NAME		"radeon"
-#define DRIVER_DESC		"ATI Radeon"
-#define DRIVER_DATE		"20080528"
-
-/* Interface history:
- *
- * 1.1 - ??
- * 1.2 - Add vertex2 ioctl (keith)
- *     - Add stencil capability to clear ioctl (gareth, keith)
- *     - Increase MAX_TEXTURE_LEVELS (brian)
- * 1.3 - Add cmdbuf ioctl (keith)
- *     - Add support for new radeon packets (keith)
- *     - Add getparam ioctl (keith)
- *     - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
- * 1.4 - Add scratch registers to get_param ioctl.
- * 1.5 - Add r200 packets to cmdbuf ioctl
- *     - Add r200 function to init ioctl
- *     - Add 'scalar2' instruction to cmdbuf
- * 1.6 - Add static GART memory manager
- *       Add irq handler (won't be turned on unless X server knows to)
- *       Add irq ioctls and irq_active getparam.
- *       Add wait command for cmdbuf ioctl
- *       Add GART offset query for getparam
- * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
- *       and R200_PP_CUBIC_OFFSET_F1_[0..5].
- *       Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
- *       R200_EMIT_PP_CUBIC_OFFSETS_[0..5].  (brian)
- * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
- *       Add 'GET' queries for starting additional clients on different VT's.
- * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
- *       Add texture rectangle support for r100.
- * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
- *       clients use to tell the DRM where they think the framebuffer is
- *       located in the card's address space
- * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
- *       and GL_EXT_blend_[func|equation]_separate on r200
- * 1.12- Add R300 CP microcode support - this just loads the CP on r300
- *       (No 3D support yet - just microcode loading).
- * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
- *     - Add hyperz support, add hyperz flags to clear ioctl.
- * 1.14- Add support for color tiling
- *     - Add R100/R200 surface allocation/free support
- * 1.15- Add support for texture micro tiling
- *     - Add support for r100 cube maps
- * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
- *       texture filtering on r200
- * 1.17- Add initial support for R300 (3D).
- * 1.18- Add support for GL_ATI_fragment_shader, new packets
- *       R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
- *       R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
- *       (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
- * 1.19- Add support for gart table in FB memory and PCIE r300
- * 1.20- Add support for r300 texrect
- * 1.21- Add support for card type getparam
- * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
- * 1.23- Add new radeon memory map work from benh
- * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
- * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
- *       new packet type)
- * 1.26- Add support for variable size PCI(E) gart aperture
- * 1.27- Add support for IGP GART
- * 1.28- Add support for VBL on CRTC2
- * 1.29- R500 3D cmd buffer support
- * 1.30- Add support for occlusion queries
- * 1.31- Add support for num Z pipes from GET_PARAM
- * 1.32- fixes for rv740 setup
- * 1.33- Add r6xx/r7xx const buffer support
- * 1.34- fix evergreen/cayman GS register
- */
-#define DRIVER_MAJOR		1
-#define DRIVER_MINOR		34
-#define DRIVER_PATCHLEVEL	0
-
-long radeon_drm_ioctl(struct file *filp,
-		      unsigned int cmd, unsigned long arg);
-
-#endif				/* __RADEON_DRV_H__ */
diff --git a/hw/display/radeon_family.h b/hw/display/radeon_family.h
deleted file mode 100644
index 4b7b87f71a..0000000000
--- a/hw/display/radeon_family.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-
-/* this file defines the CHIP_  and family flags used in the pciids,
- * its is common between kms and non-kms because duplicating it and
- * changing one place is fail.
- */
-#ifndef RADEON_FAMILY_H
-#define RADEON_FAMILY_H
-/*
- * Radeon chip families
- */
-enum radeon_family {
-	CHIP_R100 = 0,
-	CHIP_RV100,
-	CHIP_RS100,
-	CHIP_RV200,
-	CHIP_RS200,
-	CHIP_R200,
-	CHIP_RV250,
-	CHIP_RS300,
-	CHIP_RV280,
-	CHIP_R300,
-	CHIP_R350,
-	CHIP_RV350,
-	CHIP_RV380,
-	CHIP_R420,
-	CHIP_R423,
-	CHIP_RV410,
-	CHIP_RS400,
-	CHIP_RS480,
-	CHIP_RS600,
-	CHIP_RS690,
-	CHIP_RS740,
-	CHIP_RV515,
-	CHIP_R520,
-	CHIP_RV530,
-	CHIP_RV560,
-	CHIP_RV570,
-	CHIP_R580,
-	CHIP_R600,
-	CHIP_RV610,
-	CHIP_RV630,
-	CHIP_RV670,
-	CHIP_RV620,
-	CHIP_RV635,
-	CHIP_RS780,
-	CHIP_RS880,
-	CHIP_RV770,
-	CHIP_RV730,
-	CHIP_RV710,
-	CHIP_RV740,
-	CHIP_CEDAR,
-	CHIP_REDWOOD,
-	CHIP_JUNIPER,
-	CHIP_CYPRESS,
-	CHIP_HEMLOCK,
-	CHIP_PALM,
-	CHIP_SUMO,
-	CHIP_SUMO2,
-	CHIP_BARTS,
-	CHIP_TURKS,
-	CHIP_CAICOS,
-	CHIP_CAYMAN,
-	CHIP_ARUBA,
-	CHIP_TAHITI,
-	CHIP_PITCAIRN,
-	CHIP_VERDE,
-	CHIP_OLAND,
-	CHIP_HAINAN,
-	CHIP_BONAIRE,
-	CHIP_KAVERI,
-	CHIP_KABINI,
-	CHIP_HAWAII,
-	CHIP_MULLINS,
-	CHIP_LAST,
-};
-
-/*
- * Chip flags
- */
-enum radeon_chip_flags {
-	RADEON_FAMILY_MASK = 0x0000ffffUL,
-	RADEON_FLAGS_MASK = 0xffff0000UL,
-	RADEON_IS_MOBILITY = 0x00010000UL,
-	RADEON_IS_IGP = 0x00020000UL,
-	RADEON_SINGLE_CRTC = 0x00040000UL,
-	RADEON_IS_AGP = 0x00080000UL,
-	RADEON_HAS_HIERZ = 0x00100000UL,
-	RADEON_IS_PCIE = 0x00200000UL,
-	RADEON_NEW_MEMMAP = 0x00400000UL,
-	RADEON_IS_PCI = 0x00800000UL,
-	RADEON_IS_IGPGART = 0x01000000UL,
-	RADEON_IS_PX = 0x02000000UL,
-};
-
-#endif
diff --git a/hw/display/radeon_mode.h b/hw/display/radeon_mode.h
deleted file mode 100644
index fd470d6bf3..0000000000
--- a/hw/display/radeon_mode.h
+++ /dev/null
@@ -1,1002 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- *                VA Linux Systems Inc., Fremont, California.
- * Copyright 2008 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Original Authors:
- *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
- *
- * Kernel port Author: Dave Airlie
- */
-
-#ifndef RADEON_MODE_H
-#define RADEON_MODE_H
-
-#include <drm/drm_crtc.h>
-#include <drm/drm_edid.h>
-#include <drm/drm_encoder.h>
-#include <drm/drm_dp_helper.h>
-#include <drm/drm_dp_mst_helper.h>
-#include <drm/drm_fixed.h>
-#include <drm/drm_crtc_helper.h>
-#include <linux/i2c.h>
-#include <linux/i2c-algo-bit.h>
-
-struct radeon_bo;
-struct radeon_device;
-
-#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
-#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
-#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
-
-#define RADEON_MAX_HPD_PINS 7
-#define RADEON_MAX_CRTCS 6
-#define RADEON_MAX_AFMT_BLOCKS 7
-
-enum radeon_rmx_type {
-	RMX_OFF,
-	RMX_FULL,
-	RMX_CENTER,
-	RMX_ASPECT
-};
-
-enum radeon_tv_std {
-	TV_STD_NTSC,
-	TV_STD_PAL,
-	TV_STD_PAL_M,
-	TV_STD_PAL_60,
-	TV_STD_NTSC_J,
-	TV_STD_SCART_PAL,
-	TV_STD_SECAM,
-	TV_STD_PAL_CN,
-	TV_STD_PAL_N,
-};
-
-enum radeon_underscan_type {
-	UNDERSCAN_OFF,
-	UNDERSCAN_ON,
-	UNDERSCAN_AUTO,
-};
-
-enum radeon_hpd_id {
-	RADEON_HPD_1 = 0,
-	RADEON_HPD_2,
-	RADEON_HPD_3,
-	RADEON_HPD_4,
-	RADEON_HPD_5,
-	RADEON_HPD_6,
-	RADEON_HPD_NONE = 0xff,
-};
-
-enum radeon_output_csc {
-	RADEON_OUTPUT_CSC_BYPASS = 0,
-	RADEON_OUTPUT_CSC_TVRGB = 1,
-	RADEON_OUTPUT_CSC_YCBCR601 = 2,
-	RADEON_OUTPUT_CSC_YCBCR709 = 3,
-};
-
-#define RADEON_MAX_I2C_BUS 16
-
-/* radeon gpio-based i2c
- * 1. "mask" reg and bits
- *    grabs the gpio pins for software use
- *    0=not held  1=held
- * 2. "a" reg and bits
- *    output pin value
- *    0=low 1=high
- * 3. "en" reg and bits
- *    sets the pin direction
- *    0=input 1=output
- * 4. "y" reg and bits
- *    input pin value
- *    0=low 1=high
- */
-struct radeon_i2c_bus_rec {
-	bool valid;
-	/* id used by atom */
-	uint8_t i2c_id;
-	/* id used by atom */
-	enum radeon_hpd_id hpd;
-	/* can be used with hw i2c engine */
-	bool hw_capable;
-	/* uses multi-media i2c engine */
-	bool mm_i2c;
-	/* regs and bits */
-	uint32_t mask_clk_reg;
-	uint32_t mask_data_reg;
-	uint32_t a_clk_reg;
-	uint32_t a_data_reg;
-	uint32_t en_clk_reg;
-	uint32_t en_data_reg;
-	uint32_t y_clk_reg;
-	uint32_t y_data_reg;
-	uint32_t mask_clk_mask;
-	uint32_t mask_data_mask;
-	uint32_t a_clk_mask;
-	uint32_t a_data_mask;
-	uint32_t en_clk_mask;
-	uint32_t en_data_mask;
-	uint32_t y_clk_mask;
-	uint32_t y_data_mask;
-};
-
-struct radeon_tmds_pll {
-    uint32_t freq;
-    uint32_t value;
-};
-
-#define RADEON_MAX_BIOS_CONNECTOR 16
-
-/* pll flags */
-#define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
-#define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
-#define RADEON_PLL_USE_REF_DIV          (1 << 2)
-#define RADEON_PLL_LEGACY               (1 << 3)
-#define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
-#define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
-#define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
-#define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
-#define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
-#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
-#define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
-#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
-#define RADEON_PLL_USE_POST_DIV         (1 << 12)
-#define RADEON_PLL_IS_LCD               (1 << 13)
-#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
-
-struct radeon_pll {
-	/* reference frequency */
-	uint32_t reference_freq;
-
-	/* fixed dividers */
-	uint32_t reference_div;
-	uint32_t post_div;
-
-	/* pll in/out limits */
-	uint32_t pll_in_min;
-	uint32_t pll_in_max;
-	uint32_t pll_out_min;
-	uint32_t pll_out_max;
-	uint32_t lcd_pll_out_min;
-	uint32_t lcd_pll_out_max;
-	uint32_t best_vco;
-
-	/* divider limits */
-	uint32_t min_ref_div;
-	uint32_t max_ref_div;
-	uint32_t min_post_div;
-	uint32_t max_post_div;
-	uint32_t min_feedback_div;
-	uint32_t max_feedback_div;
-	uint32_t min_frac_feedback_div;
-	uint32_t max_frac_feedback_div;
-
-	/* flags for the current clock */
-	uint32_t flags;
-
-	/* pll id */
-	uint32_t id;
-};
-
-struct radeon_i2c_chan {
-	struct i2c_adapter adapter;
-	struct drm_device *dev;
-	struct i2c_algo_bit_data bit;
-	struct radeon_i2c_bus_rec rec;
-	struct drm_dp_aux aux;
-	bool has_aux;
-	struct mutex mutex;
-};
-
-/* mostly for macs, but really any system without connector tables */
-enum radeon_connector_table {
-	CT_NONE = 0,
-	CT_GENERIC,
-	CT_IBOOK,
-	CT_POWERBOOK_EXTERNAL,
-	CT_POWERBOOK_INTERNAL,
-	CT_POWERBOOK_VGA,
-	CT_MINI_EXTERNAL,
-	CT_MINI_INTERNAL,
-	CT_IMAC_G5_ISIGHT,
-	CT_EMAC,
-	CT_RN50_POWER,
-	CT_MAC_X800,
-	CT_MAC_G5_9600,
-	CT_SAM440EP,
-	CT_MAC_G4_SILVER
-};
-
-enum radeon_dvo_chip {
-	DVO_SIL164,
-	DVO_SIL1178,
-};
-
-struct radeon_fbdev;
-
-struct radeon_afmt {
-	bool enabled;
-	int offset;
-	bool last_buffer_filled_status;
-	int id;
-};
-
-struct radeon_mode_info {
-	struct atom_context *atom_context;
-	struct card_info *atom_card_info;
-	enum radeon_connector_table connector_table;
-	bool mode_config_initialized;
-	struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
-	struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
-	/* DVI-I properties */
-	struct drm_property *coherent_mode_property;
-	/* DAC enable load detect */
-	struct drm_property *load_detect_property;
-	/* TV standard */
-	struct drm_property *tv_std_property;
-	/* legacy TMDS PLL detect */
-	struct drm_property *tmds_pll_property;
-	/* underscan */
-	struct drm_property *underscan_property;
-	struct drm_property *underscan_hborder_property;
-	struct drm_property *underscan_vborder_property;
-	/* audio */
-	struct drm_property *audio_property;
-	/* FMT dithering */
-	struct drm_property *dither_property;
-	/* Output CSC */
-	struct drm_property *output_csc_property;
-	/* hardcoded DFP edid from BIOS */
-	struct edid *bios_hardcoded_edid;
-	int bios_hardcoded_edid_size;
-
-	/* pointer to fbdev info structure */
-	struct radeon_fbdev *rfbdev;
-	/* firmware flags */
-	u16 firmware_flags;
-	/* pointer to backlight encoder */
-	struct radeon_encoder *bl_encoder;
-
-	/* bitmask for active encoder frontends */
-	uint32_t active_encoders;
-};
-
-#define RADEON_MAX_BL_LEVEL 0xFF
-
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
-struct radeon_backlight_privdata {
-	struct radeon_encoder *encoder;
-	uint8_t negative;
-};
-
-#endif
-
-#define MAX_H_CODE_TIMING_LEN 32
-#define MAX_V_CODE_TIMING_LEN 32
-
-/* need to store these as reading
-   back code tables is excessive */
-struct radeon_tv_regs {
-	uint32_t tv_uv_adr;
-	uint32_t timing_cntl;
-	uint32_t hrestart;
-	uint32_t vrestart;
-	uint32_t frestart;
-	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
-	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
-};
-
-struct radeon_atom_ss {
-	uint16_t percentage;
-	uint16_t percentage_divider;
-	uint8_t type;
-	uint16_t step;
-	uint8_t delay;
-	uint8_t range;
-	uint8_t refdiv;
-	/* asic_ss */
-	uint16_t rate;
-	uint16_t amount;
-};
-
-enum radeon_flip_status {
-	RADEON_FLIP_NONE,
-	RADEON_FLIP_PENDING,
-	RADEON_FLIP_SUBMITTED
-};
-
-struct radeon_crtc {
-	struct drm_crtc base;
-	int crtc_id;
-	u16 lut_r[256], lut_g[256], lut_b[256];
-	bool enabled;
-	bool can_tile;
-	bool cursor_out_of_bounds;
-	uint32_t crtc_offset;
-	struct drm_gem_object *cursor_bo;
-	uint64_t cursor_addr;
-	int cursor_x;
-	int cursor_y;
-	int cursor_hot_x;
-	int cursor_hot_y;
-	int cursor_width;
-	int cursor_height;
-	int max_cursor_width;
-	int max_cursor_height;
-	uint32_t legacy_display_base_addr;
-	enum radeon_rmx_type rmx_type;
-	u8 h_border;
-	u8 v_border;
-	fixed20_12 vsc;
-	fixed20_12 hsc;
-	struct drm_display_mode native_mode;
-	int pll_id;
-	/* page flipping */
-	struct workqueue_struct *flip_queue;
-	struct radeon_flip_work *flip_work;
-	enum radeon_flip_status flip_status;
-	/* pll sharing */
-	struct radeon_atom_ss ss;
-	bool ss_enabled;
-	u32 adjusted_clock;
-	int bpc;
-	u32 pll_reference_div;
-	u32 pll_post_div;
-	u32 pll_flags;
-	struct drm_encoder *encoder;
-	struct drm_connector *connector;
-	/* for dpm */
-	u32 line_time;
-	u32 wm_low;
-	u32 wm_high;
-	u32 lb_vblank_lead_lines;
-	struct drm_display_mode hw_mode;
-	enum radeon_output_csc output_csc;
-};
-
-struct radeon_encoder_primary_dac {
-	/* legacy primary dac */
-	uint32_t ps2_pdac_adj;
-};
-
-struct radeon_encoder_lvds {
-	/* legacy lvds */
-	uint16_t panel_vcc_delay;
-	uint8_t  panel_pwr_delay;
-	uint8_t  panel_digon_delay;
-	uint8_t  panel_blon_delay;
-	uint16_t panel_ref_divider;
-	uint8_t  panel_post_divider;
-	uint16_t panel_fb_divider;
-	bool     use_bios_dividers;
-	uint32_t lvds_gen_cntl;
-	/* panel mode */
-	struct drm_display_mode native_mode;
-	struct backlight_device *bl_dev;
-	int      dpms_mode;
-	uint8_t  backlight_level;
-};
-
-struct radeon_encoder_tv_dac {
-	/* legacy tv dac */
-	uint32_t ps2_tvdac_adj;
-	uint32_t ntsc_tvdac_adj;
-	uint32_t pal_tvdac_adj;
-
-	int               h_pos;
-	int               v_pos;
-	int               h_size;
-	int               supported_tv_stds;
-	bool              tv_on;
-	enum radeon_tv_std tv_std;
-	struct radeon_tv_regs tv;
-};
-
-struct radeon_encoder_int_tmds {
-	/* legacy int tmds */
-	struct radeon_tmds_pll tmds_pll[4];
-};
-
-struct radeon_encoder_ext_tmds {
-	/* tmds over dvo */
-	struct radeon_i2c_chan *i2c_bus;
-	uint8_t slave_addr;
-	enum radeon_dvo_chip dvo_chip;
-};
-
-/* spread spectrum */
-struct radeon_encoder_atom_dig {
-	bool linkb;
-	/* atom dig */
-	bool coherent_mode;
-	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
-	/* atom lvds/edp */
-	uint32_t lcd_misc;
-	uint16_t panel_pwr_delay;
-	uint32_t lcd_ss_id;
-	/* panel mode */
-	struct drm_display_mode native_mode;
-	struct backlight_device *bl_dev;
-	int dpms_mode;
-	uint8_t backlight_level;
-	int panel_mode;
-	struct radeon_afmt *afmt;
-	struct r600_audio_pin *pin;
-	int active_mst_links;
-};
-
-struct radeon_encoder_atom_dac {
-	enum radeon_tv_std tv_std;
-};
-
-struct radeon_encoder_mst {
-	int crtc;
-	struct radeon_encoder *primary;
-	struct radeon_connector *connector;
-	struct drm_dp_mst_port *port;
-	int pbn;
-	int fe;
-	bool fe_from_be;
-	bool enc_active;
-};
-
-struct radeon_encoder {
-	struct drm_encoder base;
-	uint32_t encoder_enum;
-	uint32_t encoder_id;
-	uint32_t devices;
-	uint32_t active_device;
-	uint32_t flags;
-	uint32_t pixel_clock;
-	enum radeon_rmx_type rmx_type;
-	enum radeon_underscan_type underscan_type;
-	uint32_t underscan_hborder;
-	uint32_t underscan_vborder;
-	struct drm_display_mode native_mode;
-	void *enc_priv;
-	int audio_polling_active;
-	bool is_ext_encoder;
-	u16 caps;
-	struct radeon_audio_funcs *audio;
-	enum radeon_output_csc output_csc;
-	bool can_mst;
-	uint32_t offset;
-	bool is_mst_encoder;
-	/* front end for this mst encoder */
-};
-
-struct radeon_connector_atom_dig {
-	uint32_t igp_lane_info;
-	/* displayport */
-	u8 dpcd[DP_RECEIVER_CAP_SIZE];
-	u8 dp_sink_type;
-	int dp_clock;
-	int dp_lane_count;
-	bool edp_on;
-	bool is_mst;
-};
-
-struct radeon_gpio_rec {
-	bool valid;
-	u8 id;
-	u32 reg;
-	u32 mask;
-	u32 shift;
-};
-
-struct radeon_hpd {
-	enum radeon_hpd_id hpd;
-	u8 plugged_state;
-	struct radeon_gpio_rec gpio;
-};
-
-struct radeon_router {
-	u32 router_id;
-	struct radeon_i2c_bus_rec i2c_info;
-	u8 i2c_addr;
-	/* i2c mux */
-	bool ddc_valid;
-	u8 ddc_mux_type;
-	u8 ddc_mux_control_pin;
-	u8 ddc_mux_state;
-	/* clock/data mux */
-	bool cd_valid;
-	u8 cd_mux_type;
-	u8 cd_mux_control_pin;
-	u8 cd_mux_state;
-};
-
-enum radeon_connector_audio {
-	RADEON_AUDIO_DISABLE = 0,
-	RADEON_AUDIO_ENABLE = 1,
-	RADEON_AUDIO_AUTO = 2
-};
-
-enum radeon_connector_dither {
-	RADEON_FMT_DITHER_DISABLE = 0,
-	RADEON_FMT_DITHER_ENABLE = 1,
-};
-
-struct stream_attribs {
-	uint16_t fe;
-	uint16_t slots;
-};
-
-struct radeon_connector {
-	struct drm_connector base;
-	uint32_t connector_id;
-	uint32_t devices;
-	struct radeon_i2c_chan *ddc_bus;
-	/* some systems have an hdmi and vga port with a shared ddc line */
-	bool shared_ddc;
-	bool use_digital;
-	/* we need to mind the EDID between detect
-	   and get modes due to analog/digital/tvencoder */
-	struct edid *edid;
-	void *con_priv;
-	bool dac_load_detect;
-	bool detected_by_load; /* if the connection status was determined by load */
-	bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
-	uint16_t connector_object_id;
-	struct radeon_hpd hpd;
-	struct radeon_router router;
-	struct radeon_i2c_chan *router_bus;
-	enum radeon_connector_audio audio;
-	enum radeon_connector_dither dither;
-	int pixelclock_for_modeset;
-	bool is_mst_connector;
-	struct radeon_connector *mst_port;
-	struct drm_dp_mst_port *port;
-	struct drm_dp_mst_topology_mgr mst_mgr;
-
-	struct radeon_encoder *mst_encoder;
-	struct stream_attribs cur_stream_attribs[6];
-	int enabled_attribs;
-};
-
-#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
-				((em) == ATOM_ENCODER_MODE_DP_MST))
-
-struct atom_clock_dividers {
-	u32 post_div;
-	union {
-		struct {
-#ifdef __BIG_ENDIAN
-			u32 reserved : 6;
-			u32 whole_fb_div : 12;
-			u32 frac_fb_div : 14;
-#else
-			u32 frac_fb_div : 14;
-			u32 whole_fb_div : 12;
-			u32 reserved : 6;
-#endif
-		};
-		u32 fb_div;
-	};
-	u32 ref_div;
-	bool enable_post_div;
-	bool enable_dithen;
-	u32 vco_mode;
-	u32 real_clock;
-	/* added for CI */
-	u32 post_divider;
-	u32 flags;
-};
-
-struct atom_mpll_param {
-	union {
-		struct {
-#ifdef __BIG_ENDIAN
-			u32 reserved : 8;
-			u32 clkfrac : 12;
-			u32 clkf : 12;
-#else
-			u32 clkf : 12;
-			u32 clkfrac : 12;
-			u32 reserved : 8;
-#endif
-		};
-		u32 fb_div;
-	};
-	u32 post_div;
-	u32 bwcntl;
-	u32 dll_speed;
-	u32 vco_mode;
-	u32 yclk_sel;
-	u32 qdr;
-	u32 half_rate;
-};
-
-#define MEM_TYPE_GDDR5  0x50
-#define MEM_TYPE_GDDR4  0x40
-#define MEM_TYPE_GDDR3  0x30
-#define MEM_TYPE_DDR2   0x20
-#define MEM_TYPE_GDDR1  0x10
-#define MEM_TYPE_DDR3   0xb0
-#define MEM_TYPE_MASK   0xf0
-
-struct atom_memory_info {
-	u8 mem_vendor;
-	u8 mem_type;
-};
-
-#define MAX_AC_TIMING_ENTRIES 16
-
-struct atom_memory_clock_range_table
-{
-	u8 num_entries;
-	u8 rsv[3];
-	u32 mclk[MAX_AC_TIMING_ENTRIES];
-};
-
-#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
-#define VBIOS_MAX_AC_TIMING_ENTRIES 20
-
-struct atom_mc_reg_entry {
-	u32 mclk_max;
-	u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
-};
-
-struct atom_mc_register_address {
-	u16 s1;
-	u8 pre_reg_data;
-};
-
-struct atom_mc_reg_table {
-	u8 last;
-	u8 num_entries;
-	struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
-	struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
-};
-
-#define MAX_VOLTAGE_ENTRIES 32
-
-struct atom_voltage_table_entry
-{
-	u16 value;
-	u32 smio_low;
-};
-
-struct atom_voltage_table
-{
-	u32 count;
-	u32 mask_low;
-	u32 phase_delay;
-	struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
-};
-
-/* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
-#define DRM_SCANOUTPOS_VALID        (1 << 0)
-#define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
-#define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
-#define USE_REAL_VBLANKSTART 		(1 << 30)
-#define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)
-
-extern void
-radeon_add_atom_connector(struct drm_device *dev,
-			  uint32_t connector_id,
-			  uint32_t supported_device,
-			  int connector_type,
-			  struct radeon_i2c_bus_rec *i2c_bus,
-			  uint32_t igp_lane_info,
-			  uint16_t connector_object_id,
-			  struct radeon_hpd *hpd,
-			  struct radeon_router *router);
-extern void
-radeon_add_legacy_connector(struct drm_device *dev,
-			    uint32_t connector_id,
-			    uint32_t supported_device,
-			    int connector_type,
-			    struct radeon_i2c_bus_rec *i2c_bus,
-			    uint16_t connector_object_id,
-			    struct radeon_hpd *hpd);
-extern uint32_t
-radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
-			uint8_t dac);
-extern void radeon_link_encoder_connector(struct drm_device *dev);
-
-extern enum radeon_tv_std
-radeon_combios_get_tv_info(struct radeon_device *rdev);
-extern enum radeon_tv_std
-radeon_atombios_get_tv_info(struct radeon_device *rdev);
-extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
-						 u16 *vddc, u16 *vddci, u16 *mvdd);
-
-extern void
-radeon_combios_connected_scratch_regs(struct drm_connector *connector,
-				      struct drm_encoder *encoder,
-				      bool connected);
-extern void
-radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
-				       struct drm_encoder *encoder,
-				       bool connected);
-
-extern struct drm_connector *
-radeon_get_connector_for_encoder(struct drm_encoder *encoder);
-extern struct drm_connector *
-radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
-extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
-				    u32 pixel_clock);
-
-extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
-extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
-extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
-extern int radeon_get_monitor_bpc(struct drm_connector *connector);
-
-extern struct edid *radeon_connector_edid(struct drm_connector *connector);
-
-extern void radeon_connector_hotplug(struct drm_connector *connector);
-extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
-				       struct drm_display_mode *mode);
-extern void radeon_dp_set_link_config(struct drm_connector *connector,
-				      const struct drm_display_mode *mode);
-extern void radeon_dp_link_train(struct drm_encoder *encoder,
-				 struct drm_connector *connector);
-extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
-extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
-extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
-extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
-				    struct drm_connector *connector);
-extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
-					 u8 power_state);
-extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
-extern ssize_t
-radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
-
-extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
-extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
-extern void radeon_atom_encoder_init(struct radeon_device *rdev);
-extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
-extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
-					   int action, uint8_t lane_num,
-					   uint8_t lane_set);
-extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
-					    int action, uint8_t lane_num,
-					    uint8_t lane_set, int fe);
-extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder,
-						 int fe);
-extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
-extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
-void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
-
-extern void radeon_i2c_init(struct radeon_device *rdev);
-extern void radeon_i2c_fini(struct radeon_device *rdev);
-extern void radeon_combios_i2c_init(struct radeon_device *rdev);
-extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
-extern void radeon_i2c_add(struct radeon_device *rdev,
-			   struct radeon_i2c_bus_rec *rec,
-			   const char *name);
-extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
-						 struct radeon_i2c_bus_rec *i2c_bus);
-extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
-						 struct radeon_i2c_bus_rec *rec,
-						 const char *name);
-extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
-extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
-				u8 slave_addr,
-				u8 addr,
-				u8 *val);
-extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
-				u8 slave_addr,
-				u8 addr,
-				u8 val);
-extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
-extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
-extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
-
-extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
-					     struct radeon_atom_ss *ss,
-					     int id);
-extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
-					     struct radeon_atom_ss *ss,
-					     int id, u32 clock);
-extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
-							  u8 id);
-
-extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
-				      uint64_t freq,
-				      uint32_t *dot_clock_p,
-				      uint32_t *fb_div_p,
-				      uint32_t *frac_fb_div_p,
-				      uint32_t *ref_div_p,
-				      uint32_t *post_div_p);
-
-extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
-				     u32 freq,
-				     u32 *dot_clock_p,
-				     u32 *fb_div_p,
-				     u32 *frac_fb_div_p,
-				     u32 *ref_div_p,
-				     u32 *post_div_p);
-
-extern void radeon_setup_encoder_clones(struct drm_device *dev);
-
-struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
-struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
-struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
-struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
-struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
-extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
-extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
-extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
-extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
-extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
-extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
-
-extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
-extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
-				   struct drm_framebuffer *old_fb);
-extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
-					 struct drm_framebuffer *fb,
-					 int x, int y,
-					 enum mode_set_atomic state);
-extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
-				   struct drm_display_mode *mode,
-				   struct drm_display_mode *adjusted_mode,
-				   int x, int y,
-				   struct drm_framebuffer *old_fb);
-extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
-
-extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
-				 struct drm_framebuffer *old_fb);
-extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
-				       struct drm_framebuffer *fb,
-				       int x, int y,
-				       enum mode_set_atomic state);
-extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
-				   struct drm_framebuffer *fb,
-				   int x, int y, int atomic);
-extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
-				   struct drm_file *file_priv,
-				   uint32_t handle,
-				   uint32_t width,
-				   uint32_t height,
-				   int32_t hot_x,
-				   int32_t hot_y);
-extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
-				   int x, int y);
-extern void radeon_cursor_reset(struct drm_crtc *crtc);
-
-extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
-				      unsigned int flags, int *vpos, int *hpos,
-				      ktime_t *stime, ktime_t *etime,
-				      const struct drm_display_mode *mode);
-
-extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
-extern struct edid *
-radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
-extern bool radeon_atom_get_clock_info(struct drm_device *dev);
-extern bool radeon_combios_get_clock_info(struct drm_device *dev);
-extern struct radeon_encoder_atom_dig *
-radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
-extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
-					  struct radeon_encoder_int_tmds *tmds);
-extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
-						     struct radeon_encoder_int_tmds *tmds);
-extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
-						   struct radeon_encoder_int_tmds *tmds);
-extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
-							 struct radeon_encoder_ext_tmds *tmds);
-extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
-						       struct radeon_encoder_ext_tmds *tmds);
-extern struct radeon_encoder_primary_dac *
-radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
-extern struct radeon_encoder_tv_dac *
-radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
-extern struct radeon_encoder_lvds *
-radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
-extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
-extern struct radeon_encoder_tv_dac *
-radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
-extern struct radeon_encoder_primary_dac *
-radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
-extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
-extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
-extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
-extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
-extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
-extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
-extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
-extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
-extern void
-radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
-extern void
-radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
-extern void
-radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
-extern void
-radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
-int radeon_framebuffer_init(struct drm_device *dev,
-			     struct drm_framebuffer *rfb,
-			     const struct drm_mode_fb_cmd2 *mode_cmd,
-			     struct drm_gem_object *obj);
-
-int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
-bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
-bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
-void radeon_atombios_init_crtc(struct drm_device *dev,
-			       struct radeon_crtc *radeon_crtc);
-void radeon_legacy_init_crtc(struct drm_device *dev,
-			     struct radeon_crtc *radeon_crtc);
-
-void radeon_get_clock_info(struct drm_device *dev);
-
-extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
-extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
-
-void radeon_enc_destroy(struct drm_encoder *encoder);
-void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
-void radeon_combios_asic_init(struct drm_device *dev);
-bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
-					const struct drm_display_mode *mode,
-					struct drm_display_mode *adjusted_mode);
-void radeon_panel_mode_fixup(struct drm_encoder *encoder,
-			     struct drm_display_mode *adjusted_mode);
-void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
-
-/* legacy tv */
-void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
-				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
-				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
-void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
-				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
-				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
-void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
-				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
-				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
-void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode);
-
-/* fmt blocks */
-void avivo_program_fmt(struct drm_encoder *encoder);
-void dce3_program_fmt(struct drm_encoder *encoder);
-void dce4_program_fmt(struct drm_encoder *encoder);
-void dce8_program_fmt(struct drm_encoder *encoder);
-
-/* fbdev layer */
-int radeon_fbdev_init(struct radeon_device *rdev);
-void radeon_fbdev_fini(struct radeon_device *rdev);
-void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
-bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
-
-void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
-
-void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector);
-void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector);
-
-void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
-
-int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
-
-/* mst */
-int radeon_dp_mst_init(struct radeon_connector *radeon_connector);
-int radeon_dp_mst_probe(struct radeon_connector *radeon_connector);
-int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector);
-int radeon_mst_debugfs_init(struct radeon_device *rdev);
-void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode);
-
-void radeon_setup_mst_connector(struct drm_device *dev);
-
-int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
-void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
-#endif
diff --git a/hw/display/radeon_object.h b/hw/display/radeon_object.h
deleted file mode 100644
index 9ffd8215d3..0000000000
--- a/hw/display/radeon_object.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RADEON_OBJECT_H__
-#define __RADEON_OBJECT_H__
-
-#include <drm/radeon_drm.h>
-#include "radeon.h"
-
-/**
- * radeon_mem_type_to_domain - return domain corresponding to mem_type
- * @mem_type:	ttm memory type
- *
- * Returns corresponding domain of the ttm mem_type
- */
-static inline unsigned radeon_mem_type_to_domain(u32 mem_type)
-{
-	switch (mem_type) {
-	case TTM_PL_VRAM:
-		return RADEON_GEM_DOMAIN_VRAM;
-	case TTM_PL_TT:
-		return RADEON_GEM_DOMAIN_GTT;
-	case TTM_PL_SYSTEM:
-		return RADEON_GEM_DOMAIN_CPU;
-	default:
-		break;
-	}
-	return 0;
-}
-
-/**
- * radeon_bo_reserve - reserve bo
- * @bo:		bo structure
- * @no_intr:	don't return -ERESTARTSYS on pending signal
- *
- * Returns:
- * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
- * a signal. Release all buffer reservations and return to user-space.
- */
-static inline int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
-{
-	int r;
-
-	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
-	if (unlikely(r != 0)) {
-		if (r != -ERESTARTSYS)
-			dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
-		return r;
-	}
-	return 0;
-}
-
-static inline void radeon_bo_unreserve(struct radeon_bo *bo)
-{
-	ttm_bo_unreserve(&bo->tbo);
-}
-
-/**
- * radeon_bo_gpu_offset - return GPU offset of bo
- * @bo:	radeon object for which we query the offset
- *
- * Returns current GPU offset of the object.
- *
- * Note: object should either be pinned or reserved when calling this
- * function, it might be useful to add check for this for debugging.
- */
-static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
-{
-	return bo->tbo.offset;
-}
-
-static inline unsigned long radeon_bo_size(struct radeon_bo *bo)
-{
-	return bo->tbo.num_pages << PAGE_SHIFT;
-}
-
-static inline unsigned radeon_bo_ngpu_pages(struct radeon_bo *bo)
-{
-	return (bo->tbo.num_pages << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
-}
-
-static inline unsigned radeon_bo_gpu_page_alignment(struct radeon_bo *bo)
-{
-	return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
-}
-
-/**
- * radeon_bo_mmap_offset - return mmap offset of bo
- * @bo:	radeon object for which we query the offset
- *
- * Returns mmap offset of the object.
- */
-static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo)
-{
-	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
-}
-
-extern int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,
-			  bool no_wait);
-
-extern int radeon_bo_create(struct radeon_device *rdev,
-			    unsigned long size, int byte_align,
-			    bool kernel, u32 domain, u32 flags,
-			    struct sg_table *sg,
-			    struct reservation_object *resv,
-			    struct radeon_bo **bo_ptr);
-extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr);
-extern void radeon_bo_kunmap(struct radeon_bo *bo);
-extern struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo);
-extern void radeon_bo_unref(struct radeon_bo **bo);
-extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
-extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain,
-				    u64 max_offset, u64 *gpu_addr);
-extern int radeon_bo_unpin(struct radeon_bo *bo);
-extern int radeon_bo_evict_vram(struct radeon_device *rdev);
-extern void radeon_bo_force_delete(struct radeon_device *rdev);
-extern int radeon_bo_init(struct radeon_device *rdev);
-extern void radeon_bo_fini(struct radeon_device *rdev);
-extern int radeon_bo_list_validate(struct radeon_device *rdev,
-				   struct ww_acquire_ctx *ticket,
-				   struct list_head *head, int ring);
-extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
-				u32 tiling_flags, u32 pitch);
-extern void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
-				u32 *tiling_flags, u32 *pitch);
-extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
-				bool force_drop);
-extern void radeon_bo_move_notify(struct ttm_buffer_object *bo,
-				  bool evict,
-				  struct ttm_mem_reg *new_mem);
-extern int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
-extern int radeon_bo_get_surface_reg(struct radeon_bo *bo);
-extern void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
-			    bool shared);
-
-/*
- * sub allocation
- */
-
-static inline uint64_t radeon_sa_bo_gpu_addr(struct radeon_sa_bo *sa_bo)
-{
-	return sa_bo->manager->gpu_addr + sa_bo->soffset;
-}
-
-static inline void * radeon_sa_bo_cpu_addr(struct radeon_sa_bo *sa_bo)
-{
-	return sa_bo->manager->cpu_ptr + sa_bo->soffset;
-}
-
-extern int radeon_sa_bo_manager_init(struct radeon_device *rdev,
-				     struct radeon_sa_manager *sa_manager,
-				     unsigned size, u32 align, u32 domain,
-				     u32 flags);
-extern void radeon_sa_bo_manager_fini(struct radeon_device *rdev,
-				      struct radeon_sa_manager *sa_manager);
-extern int radeon_sa_bo_manager_start(struct radeon_device *rdev,
-				      struct radeon_sa_manager *sa_manager);
-extern int radeon_sa_bo_manager_suspend(struct radeon_device *rdev,
-					struct radeon_sa_manager *sa_manager);
-extern int radeon_sa_bo_new(struct radeon_device *rdev,
-			    struct radeon_sa_manager *sa_manager,
-			    struct radeon_sa_bo **sa_bo,
-			    unsigned size, unsigned align);
-extern void radeon_sa_bo_free(struct radeon_device *rdev,
-			      struct radeon_sa_bo **sa_bo,
-			      struct radeon_fence *fence);
-#if defined(CONFIG_DEBUG_FS)
-extern void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager,
-					 struct seq_file *m);
-#endif
-
-
-#endif
diff --git a/hw/display/radeon_trace.h b/hw/display/radeon_trace.h
deleted file mode 100644
index c93f3ab3c4..0000000000
--- a/hw/display/radeon_trace.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-#if !defined(_RADEON_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
-#define _RADEON_TRACE_H_
-
-#include <linux/stringify.h>
-#include <linux/tracepoint.h>
-#include <linux/types.h>
-
-#include <drm/drm_file.h>
-
-#undef TRACE_SYSTEM
-#define TRACE_SYSTEM radeon
-#define TRACE_INCLUDE_FILE radeon_trace
-
-TRACE_EVENT(radeon_bo_create,
-	    TP_PROTO(struct radeon_bo *bo),
-	    TP_ARGS(bo),
-	    TP_STRUCT__entry(
-			     __field(struct radeon_bo *, bo)
-			     __field(u32, pages)
-			     ),
-
-	    TP_fast_assign(
-			   __entry->bo = bo;
-			   __entry->pages = bo->tbo.num_pages;
-			   ),
-	    TP_printk("bo=%p, pages=%u", __entry->bo, __entry->pages)
-);
-
-TRACE_EVENT(radeon_cs,
-	    TP_PROTO(struct radeon_cs_parser *p),
-	    TP_ARGS(p),
-	    TP_STRUCT__entry(
-			     __field(u32, ring)
-			     __field(u32, dw)
-			     __field(u32, fences)
-			     ),
-
-	    TP_fast_assign(
-			   __entry->ring = p->ring;
-			   __entry->dw = p->chunk_ib->length_dw;
-			   __entry->fences = radeon_fence_count_emitted(
-				p->rdev, p->ring);
-			   ),
-	    TP_printk("ring=%u, dw=%u, fences=%u",
-		      __entry->ring, __entry->dw,
-		      __entry->fences)
-);
-
-TRACE_EVENT(radeon_vm_grab_id,
-	    TP_PROTO(unsigned vmid, int ring),
-	    TP_ARGS(vmid, ring),
-	    TP_STRUCT__entry(
-			     __field(u32, vmid)
-			     __field(u32, ring)
-			     ),
-
-	    TP_fast_assign(
-			   __entry->vmid = vmid;
-			   __entry->ring = ring;
-			   ),
-	    TP_printk("vmid=%u, ring=%u", __entry->vmid, __entry->ring)
-);
-
-TRACE_EVENT(radeon_vm_bo_update,
-	    TP_PROTO(struct radeon_bo_va *bo_va),
-	    TP_ARGS(bo_va),
-	    TP_STRUCT__entry(
-			     __field(u64, soffset)
-			     __field(u64, eoffset)
-			     __field(u32, flags)
-			     ),
-
-	    TP_fast_assign(
-			   __entry->soffset = bo_va->it.start;
-			   __entry->eoffset = bo_va->it.last + 1;
-			   __entry->flags = bo_va->flags;
-			   ),
-	    TP_printk("soffs=%010llx, eoffs=%010llx, flags=%08x",
-		      __entry->soffset, __entry->eoffset, __entry->flags)
-);
-
-TRACE_EVENT(radeon_vm_set_page,
-	    TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
-		     uint32_t incr, uint32_t flags),
-	    TP_ARGS(pe, addr, count, incr, flags),
-	    TP_STRUCT__entry(
-			     __field(u64, pe)
-			     __field(u64, addr)
-			     __field(u32, count)
-			     __field(u32, incr)
-			     __field(u32, flags)
-			     ),
-
-	    TP_fast_assign(
-			   __entry->pe = pe;
-			   __entry->addr = addr;
-			   __entry->count = count;
-			   __entry->incr = incr;
-			   __entry->flags = flags;
-			   ),
-	    TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%08x, count=%u",
-		      __entry->pe, __entry->addr, __entry->incr,
-		      __entry->flags, __entry->count)
-);
-
-TRACE_EVENT(radeon_vm_flush,
-	    TP_PROTO(uint64_t pd_addr, unsigned ring, unsigned id),
-	    TP_ARGS(pd_addr, ring, id),
-	    TP_STRUCT__entry(
-			     __field(u64, pd_addr)
-			     __field(u32, ring)
-			     __field(u32, id)
-			     ),
-
-	    TP_fast_assign(
-			   __entry->pd_addr = pd_addr;
-			   __entry->ring = ring;
-			   __entry->id = id;
-			   ),
-	    TP_printk("pd_addr=%010Lx, ring=%u, id=%u",
-		      __entry->pd_addr, __entry->ring, __entry->id)
-);
-
-DECLARE_EVENT_CLASS(radeon_fence_request,
-
-	    TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
-
-	    TP_ARGS(dev, ring, seqno),
-
-	    TP_STRUCT__entry(
-			     __field(u32, dev)
-			     __field(int, ring)
-			     __field(u32, seqno)
-			     ),
-
-	    TP_fast_assign(
-			   __entry->dev = dev->primary->index;
-			   __entry->ring = ring;
-			   __entry->seqno = seqno;
-			   ),
-
-	    TP_printk("dev=%u, ring=%d, seqno=%u",
-		      __entry->dev, __entry->ring, __entry->seqno)
-);
-
-DEFINE_EVENT(radeon_fence_request, radeon_fence_emit,
-
-	    TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
-
-	    TP_ARGS(dev, ring, seqno)
-);
-
-DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_begin,
-
-	    TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
-
-	    TP_ARGS(dev, ring, seqno)
-);
-
-DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_end,
-
-	    TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
-
-	    TP_ARGS(dev, ring, seqno)
-);
-
-DECLARE_EVENT_CLASS(radeon_semaphore_request,
-
-	    TP_PROTO(int ring, struct radeon_semaphore *sem),
-
-	    TP_ARGS(ring, sem),
-
-	    TP_STRUCT__entry(
-			     __field(int, ring)
-			     __field(signed, waiters)
-			     __field(uint64_t, gpu_addr)
-			     ),
-
-	    TP_fast_assign(
-			   __entry->ring = ring;
-			   __entry->waiters = sem->waiters;
-			   __entry->gpu_addr = sem->gpu_addr;
-			   ),
-
-	    TP_printk("ring=%u, waiters=%d, addr=%010Lx", __entry->ring,
-		      __entry->waiters, __entry->gpu_addr)
-);
-
-DEFINE_EVENT(radeon_semaphore_request, radeon_semaphore_signale,
-
-	    TP_PROTO(int ring, struct radeon_semaphore *sem),
-
-	    TP_ARGS(ring, sem)
-);
-
-DEFINE_EVENT(radeon_semaphore_request, radeon_semaphore_wait,
-
-	    TP_PROTO(int ring, struct radeon_semaphore *sem),
-
-	    TP_ARGS(ring, sem)
-);
-
-#endif
-
-/* This part must be outside protection */
-#undef TRACE_INCLUDE_PATH
-#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/radeon
-#include <trace/define_trace.h>
diff --git a/hw/display/radeon_ucode.h b/hw/display/radeon_ucode.h
deleted file mode 100644
index dc4576e4d8..0000000000
--- a/hw/display/radeon_ucode.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Copyright 2012 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __RADEON_UCODE_H__
-#define __RADEON_UCODE_H__
-
-/* CP */
-#define R600_PFP_UCODE_SIZE          576
-#define R600_PM4_UCODE_SIZE          1792
-#define R700_PFP_UCODE_SIZE          848
-#define R700_PM4_UCODE_SIZE          1360
-#define EVERGREEN_PFP_UCODE_SIZE     1120
-#define EVERGREEN_PM4_UCODE_SIZE     1376
-#define CAYMAN_PFP_UCODE_SIZE        2176
-#define CAYMAN_PM4_UCODE_SIZE        2176
-#define SI_PFP_UCODE_SIZE            2144
-#define SI_PM4_UCODE_SIZE            2144
-#define SI_CE_UCODE_SIZE             2144
-#define CIK_PFP_UCODE_SIZE           2144
-#define CIK_ME_UCODE_SIZE            2144
-#define CIK_CE_UCODE_SIZE            2144
-
-/* MEC */
-#define CIK_MEC_UCODE_SIZE           4192
-
-/* RLC */
-#define R600_RLC_UCODE_SIZE          768
-#define R700_RLC_UCODE_SIZE          1024
-#define EVERGREEN_RLC_UCODE_SIZE     768
-#define CAYMAN_RLC_UCODE_SIZE        1024
-#define ARUBA_RLC_UCODE_SIZE         1536
-#define SI_RLC_UCODE_SIZE            2048
-#define BONAIRE_RLC_UCODE_SIZE       2048
-#define KB_RLC_UCODE_SIZE            2560
-#define KV_RLC_UCODE_SIZE            2560
-#define ML_RLC_UCODE_SIZE            2560
-
-/* MC */
-#define BTC_MC_UCODE_SIZE            6024
-#define CAYMAN_MC_UCODE_SIZE         6037
-#define SI_MC_UCODE_SIZE             7769
-#define TAHITI_MC_UCODE_SIZE         7808
-#define PITCAIRN_MC_UCODE_SIZE       7775
-#define VERDE_MC_UCODE_SIZE          7875
-#define OLAND_MC_UCODE_SIZE          7863
-#define BONAIRE_MC_UCODE_SIZE        7866
-#define BONAIRE_MC2_UCODE_SIZE       7948
-#define HAWAII_MC_UCODE_SIZE         7933
-#define HAWAII_MC2_UCODE_SIZE        8091
-
-/* SDMA */
-#define CIK_SDMA_UCODE_SIZE          1050
-#define CIK_SDMA_UCODE_VERSION       64
-
-/* SMC */
-#define RV770_SMC_UCODE_START        0x0100
-#define RV770_SMC_UCODE_SIZE         0x410d
-#define RV770_SMC_INT_VECTOR_START   0xffc0
-#define RV770_SMC_INT_VECTOR_SIZE    0x0040
-
-#define RV730_SMC_UCODE_START        0x0100
-#define RV730_SMC_UCODE_SIZE         0x412c
-#define RV730_SMC_INT_VECTOR_START   0xffc0
-#define RV730_SMC_INT_VECTOR_SIZE    0x0040
-
-#define RV710_SMC_UCODE_START        0x0100
-#define RV710_SMC_UCODE_SIZE         0x3f1f
-#define RV710_SMC_INT_VECTOR_START   0xffc0
-#define RV710_SMC_INT_VECTOR_SIZE    0x0040
-
-#define RV740_SMC_UCODE_START        0x0100
-#define RV740_SMC_UCODE_SIZE         0x41c5
-#define RV740_SMC_INT_VECTOR_START   0xffc0
-#define RV740_SMC_INT_VECTOR_SIZE    0x0040
-
-#define CEDAR_SMC_UCODE_START        0x0100
-#define CEDAR_SMC_UCODE_SIZE         0x5d50
-#define CEDAR_SMC_INT_VECTOR_START   0xffc0
-#define CEDAR_SMC_INT_VECTOR_SIZE    0x0040
-
-#define REDWOOD_SMC_UCODE_START      0x0100
-#define REDWOOD_SMC_UCODE_SIZE       0x5f0a
-#define REDWOOD_SMC_INT_VECTOR_START 0xffc0
-#define REDWOOD_SMC_INT_VECTOR_SIZE  0x0040
-
-#define JUNIPER_SMC_UCODE_START      0x0100
-#define JUNIPER_SMC_UCODE_SIZE       0x5f1f
-#define JUNIPER_SMC_INT_VECTOR_START 0xffc0
-#define JUNIPER_SMC_INT_VECTOR_SIZE  0x0040
-
-#define CYPRESS_SMC_UCODE_START      0x0100
-#define CYPRESS_SMC_UCODE_SIZE       0x61f7
-#define CYPRESS_SMC_INT_VECTOR_START 0xffc0
-#define CYPRESS_SMC_INT_VECTOR_SIZE  0x0040
-
-#define BARTS_SMC_UCODE_START        0x0100
-#define BARTS_SMC_UCODE_SIZE         0x6107
-#define BARTS_SMC_INT_VECTOR_START   0xffc0
-#define BARTS_SMC_INT_VECTOR_SIZE    0x0040
-
-#define TURKS_SMC_UCODE_START        0x0100
-#define TURKS_SMC_UCODE_SIZE         0x605b
-#define TURKS_SMC_INT_VECTOR_START   0xffc0
-#define TURKS_SMC_INT_VECTOR_SIZE    0x0040
-
-#define CAICOS_SMC_UCODE_START       0x0100
-#define CAICOS_SMC_UCODE_SIZE        0x5fbd
-#define CAICOS_SMC_INT_VECTOR_START  0xffc0
-#define CAICOS_SMC_INT_VECTOR_SIZE   0x0040
-
-#define CAYMAN_SMC_UCODE_START       0x0100
-#define CAYMAN_SMC_UCODE_SIZE        0x79ec
-#define CAYMAN_SMC_INT_VECTOR_START  0xffc0
-#define CAYMAN_SMC_INT_VECTOR_SIZE   0x0040
-
-#define TAHITI_SMC_UCODE_START       0x10000
-#define TAHITI_SMC_UCODE_SIZE        0xf458
-
-#define PITCAIRN_SMC_UCODE_START     0x10000
-#define PITCAIRN_SMC_UCODE_SIZE      0xe9f4
-
-#define VERDE_SMC_UCODE_START        0x10000
-#define VERDE_SMC_UCODE_SIZE         0xebe4
-
-#define OLAND_SMC_UCODE_START        0x10000
-#define OLAND_SMC_UCODE_SIZE         0xe7b4
-
-#define HAINAN_SMC_UCODE_START       0x10000
-#define HAINAN_SMC_UCODE_SIZE        0xe67C
-
-#define BONAIRE_SMC_UCODE_START      0x20000
-#define BONAIRE_SMC_UCODE_SIZE       0x1FDEC
-
-#define HAWAII_SMC_UCODE_START       0x20000
-#define HAWAII_SMC_UCODE_SIZE        0x1FDEC
-
-struct common_firmware_header {
-	uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
-	uint32_t header_size_bytes; /* size of just the header in bytes */
-	uint16_t header_version_major; /* header version */
-	uint16_t header_version_minor; /* header version */
-	uint16_t ip_version_major; /* IP version */
-	uint16_t ip_version_minor; /* IP version */
-	uint32_t ucode_version;
-	uint32_t ucode_size_bytes; /* size of ucode in bytes */
-	uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
-	uint32_t crc32;  /* crc32 checksum of the payload */
-};
-
-/* version_major=1, version_minor=0 */
-struct mc_firmware_header_v1_0 {
-	struct common_firmware_header header;
-	uint32_t io_debug_size_bytes; /* size of debug array in dwords */
-	uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
-};
-
-/* version_major=1, version_minor=0 */
-struct smc_firmware_header_v1_0 {
-	struct common_firmware_header header;
-	uint32_t ucode_start_addr;
-};
-
-/* version_major=1, version_minor=0 */
-struct gfx_firmware_header_v1_0 {
-	struct common_firmware_header header;
-	uint32_t ucode_feature_version;
-	uint32_t jt_offset; /* jt location */
-	uint32_t jt_size;  /* size of jt */
-};
-
-/* version_major=1, version_minor=0 */
-struct rlc_firmware_header_v1_0 {
-	struct common_firmware_header header;
-	uint32_t ucode_feature_version;
-	uint32_t save_and_restore_offset;
-	uint32_t clear_state_descriptor_offset;
-	uint32_t avail_scratch_ram_locations;
-	uint32_t master_pkt_description_offset;
-};
-
-/* version_major=1, version_minor=0 */
-struct sdma_firmware_header_v1_0 {
-	struct common_firmware_header header;
-	uint32_t ucode_feature_version;
-	uint32_t ucode_change_version;
-	uint32_t jt_offset; /* jt location */
-	uint32_t jt_size; /* size of jt */
-};
-
-/* header is fixed size */
-union radeon_firmware_header {
-	struct common_firmware_header common;
-	struct mc_firmware_header_v1_0 mc;
-	struct smc_firmware_header_v1_0 smc;
-	struct gfx_firmware_header_v1_0 gfx;
-	struct rlc_firmware_header_v1_0 rlc;
-	struct sdma_firmware_header_v1_0 sdma;
-	uint8_t raw[0x100];
-};
-
-void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
-void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
-void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
-void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
-void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
-int radeon_ucode_validate(const struct firmware *fw);
-
-#endif
diff --git a/hw/display/rs100d.h b/hw/display/rs100d.h
deleted file mode 100644
index 48a913a06c..0000000000
--- a/hw/display/rs100d.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RS100D_H__
-#define __RS100D_H__
-
-/* Registers */
-#define R_00015C_NB_TOM                              0x00015C
-#define   S_00015C_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
-#define   G_00015C_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
-#define   C_00015C_MC_FB_START                         0xFFFF0000
-#define   S_00015C_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
-#define   G_00015C_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
-#define   C_00015C_MC_FB_TOP                           0x0000FFFF
-
-#endif
diff --git a/hw/display/rs400d.h b/hw/display/rs400d.h
deleted file mode 100644
index 6d8bac58ce..0000000000
--- a/hw/display/rs400d.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RS400D_H__
-#define __RS400D_H__
-
-/* Registers */
-#define R_000148_MC_FB_LOCATION                      0x000148
-#define   S_000148_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
-#define   G_000148_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
-#define   C_000148_MC_FB_START                         0xFFFF0000
-#define   S_000148_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
-#define   G_000148_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
-#define   C_000148_MC_FB_TOP                           0x0000FFFF
-#define R_00015C_NB_TOM                              0x00015C
-#define   S_00015C_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
-#define   G_00015C_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
-#define   C_00015C_MC_FB_START                         0xFFFF0000
-#define   S_00015C_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
-#define   G_00015C_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
-#define   C_00015C_MC_FB_TOP                           0x0000FFFF
-#define R_0007C0_CP_STAT                             0x0007C0
-#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
-#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
-#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
-#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
-#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
-#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
-#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
-#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
-#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
-#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
-#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
-#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
-#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
-#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
-#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
-#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
-#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
-#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
-#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
-#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
-#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
-#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
-#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
-#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
-#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
-#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
-#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
-#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
-#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
-#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
-#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
-#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
-#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
-#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
-#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
-#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
-#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
-#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
-#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
-#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
-#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
-#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
-#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
-#define R_000E40_RBBM_STATUS                         0x000E40
-#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
-#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
-#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
-#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
-#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
-#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
-#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
-#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
-#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
-#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
-#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
-#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
-#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
-#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
-#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
-#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
-#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
-#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
-#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
-#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
-#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
-#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
-#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
-#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
-#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
-#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
-#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
-#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
-#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
-#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
-#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
-#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
-#define   C_000E40_E2_BUSY                             0xFFFDFFFF
-#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
-#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
-#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
-#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
-#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
-#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
-#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
-#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
-#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
-#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
-#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
-#define   C_000E40_RE_BUSY                             0xFFDFFFFF
-#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
-#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
-#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
-#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
-#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
-#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
-#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
-#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
-#define   C_000E40_PB_BUSY                             0xFEFFFFFF
-#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
-#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
-#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
-#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
-#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
-#define   C_000E40_GA_BUSY                             0xFBFFFFFF
-#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
-#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
-#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
-#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
-#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
-#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
-
-#endif
diff --git a/hw/display/rs600d.h b/hw/display/rs600d.h
deleted file mode 100644
index f1f89414dc..0000000000
--- a/hw/display/rs600d.h
+++ /dev/null
@@ -1,685 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RS600D_H__
-#define __RS600D_H__
-
-/* Registers */
-#define R_000040_GEN_INT_CNTL                        0x000040
-#define   S_000040_SCRATCH_INT_MASK(x)                 (((x) & 0x1) << 18)
-#define   G_000040_SCRATCH_INT_MASK(x)                 (((x) >> 18) & 0x1)
-#define   C_000040_SCRATCH_INT_MASK                    0xFFFBFFFF
-#define   S_000040_GUI_IDLE_MASK(x)                    (((x) & 0x1) << 19)
-#define   G_000040_GUI_IDLE_MASK(x)                    (((x) >> 19) & 0x1)
-#define   C_000040_GUI_IDLE_MASK                       0xFFF7FFFF
-#define   S_000040_DMA_VIPH1_INT_EN(x)                 (((x) & 0x1) << 13)
-#define   G_000040_DMA_VIPH1_INT_EN(x)                 (((x) >> 13) & 0x1)
-#define   C_000040_DMA_VIPH1_INT_EN                    0xFFFFDFFF
-#define   S_000040_DMA_VIPH2_INT_EN(x)                 (((x) & 0x1) << 14)
-#define   G_000040_DMA_VIPH2_INT_EN(x)                 (((x) >> 14) & 0x1)
-#define   C_000040_DMA_VIPH2_INT_EN                    0xFFFFBFFF
-#define   S_000040_DMA_VIPH3_INT_EN(x)                 (((x) & 0x1) << 15)
-#define   G_000040_DMA_VIPH3_INT_EN(x)                 (((x) >> 15) & 0x1)
-#define   C_000040_DMA_VIPH3_INT_EN                    0xFFFF7FFF
-#define   S_000040_I2C_INT_EN(x)                       (((x) & 0x1) << 17)
-#define   G_000040_I2C_INT_EN(x)                       (((x) >> 17) & 0x1)
-#define   C_000040_I2C_INT_EN                          0xFFFDFFFF
-#define   S_000040_GUI_IDLE(x)                         (((x) & 0x1) << 19)
-#define   G_000040_GUI_IDLE(x)                         (((x) >> 19) & 0x1)
-#define   C_000040_GUI_IDLE                            0xFFF7FFFF
-#define   S_000040_VIPH_INT_EN(x)                      (((x) & 0x1) << 24)
-#define   G_000040_VIPH_INT_EN(x)                      (((x) >> 24) & 0x1)
-#define   C_000040_VIPH_INT_EN                         0xFEFFFFFF
-#define   S_000040_SW_INT_EN(x)                        (((x) & 0x1) << 25)
-#define   G_000040_SW_INT_EN(x)                        (((x) >> 25) & 0x1)
-#define   C_000040_SW_INT_EN                           0xFDFFFFFF
-#define   S_000040_GEYSERVILLE(x)                      (((x) & 0x1) << 27)
-#define   G_000040_GEYSERVILLE(x)                      (((x) >> 27) & 0x1)
-#define   C_000040_GEYSERVILLE                         0xF7FFFFFF
-#define   S_000040_HDCP_AUTHORIZED_INT(x)              (((x) & 0x1) << 28)
-#define   G_000040_HDCP_AUTHORIZED_INT(x)              (((x) >> 28) & 0x1)
-#define   C_000040_HDCP_AUTHORIZED_INT                 0xEFFFFFFF
-#define   S_000040_DVI_I2C_INT(x)                      (((x) & 0x1) << 29)
-#define   G_000040_DVI_I2C_INT(x)                      (((x) >> 29) & 0x1)
-#define   C_000040_DVI_I2C_INT                         0xDFFFFFFF
-#define   S_000040_GUIDMA(x)                           (((x) & 0x1) << 30)
-#define   G_000040_GUIDMA(x)                           (((x) >> 30) & 0x1)
-#define   C_000040_GUIDMA                              0xBFFFFFFF
-#define   S_000040_VIDDMA(x)                           (((x) & 0x1) << 31)
-#define   G_000040_VIDDMA(x)                           (((x) >> 31) & 0x1)
-#define   C_000040_VIDDMA                              0x7FFFFFFF
-#define R_000044_GEN_INT_STATUS                      0x000044
-#define   S_000044_DISPLAY_INT_STAT(x)                 (((x) & 0x1) << 0)
-#define   G_000044_DISPLAY_INT_STAT(x)                 (((x) >> 0) & 0x1)
-#define   C_000044_DISPLAY_INT_STAT                    0xFFFFFFFE
-#define   S_000044_VGA_INT_STAT(x)                     (((x) & 0x1) << 1)
-#define   G_000044_VGA_INT_STAT(x)                     (((x) >> 1) & 0x1)
-#define   C_000044_VGA_INT_STAT                        0xFFFFFFFD
-#define   S_000044_CAP0_INT_ACTIVE(x)                  (((x) & 0x1) << 8)
-#define   G_000044_CAP0_INT_ACTIVE(x)                  (((x) >> 8) & 0x1)
-#define   C_000044_CAP0_INT_ACTIVE                     0xFFFFFEFF
-#define   S_000044_DMA_VIPH0_INT(x)                    (((x) & 0x1) << 12)
-#define   G_000044_DMA_VIPH0_INT(x)                    (((x) >> 12) & 0x1)
-#define   C_000044_DMA_VIPH0_INT                       0xFFFFEFFF
-#define   S_000044_DMA_VIPH1_INT(x)                    (((x) & 0x1) << 13)
-#define   G_000044_DMA_VIPH1_INT(x)                    (((x) >> 13) & 0x1)
-#define   C_000044_DMA_VIPH1_INT                       0xFFFFDFFF
-#define   S_000044_DMA_VIPH2_INT(x)                    (((x) & 0x1) << 14)
-#define   G_000044_DMA_VIPH2_INT(x)                    (((x) >> 14) & 0x1)
-#define   C_000044_DMA_VIPH2_INT                       0xFFFFBFFF
-#define   S_000044_DMA_VIPH3_INT(x)                    (((x) & 0x1) << 15)
-#define   G_000044_DMA_VIPH3_INT(x)                    (((x) >> 15) & 0x1)
-#define   C_000044_DMA_VIPH3_INT                       0xFFFF7FFF
-#define   S_000044_MC_PROBE_FAULT_STAT(x)              (((x) & 0x1) << 16)
-#define   G_000044_MC_PROBE_FAULT_STAT(x)              (((x) >> 16) & 0x1)
-#define   C_000044_MC_PROBE_FAULT_STAT                 0xFFFEFFFF
-#define   S_000044_I2C_INT(x)                          (((x) & 0x1) << 17)
-#define   G_000044_I2C_INT(x)                          (((x) >> 17) & 0x1)
-#define   C_000044_I2C_INT                             0xFFFDFFFF
-#define   S_000044_SCRATCH_INT_STAT(x)                 (((x) & 0x1) << 18)
-#define   G_000044_SCRATCH_INT_STAT(x)                 (((x) >> 18) & 0x1)
-#define   C_000044_SCRATCH_INT_STAT                    0xFFFBFFFF
-#define   S_000044_GUI_IDLE_STAT(x)                    (((x) & 0x1) << 19)
-#define   G_000044_GUI_IDLE_STAT(x)                    (((x) >> 19) & 0x1)
-#define   C_000044_GUI_IDLE_STAT                       0xFFF7FFFF
-#define   S_000044_ATI_OVERDRIVE_INT_STAT(x)           (((x) & 0x1) << 20)
-#define   G_000044_ATI_OVERDRIVE_INT_STAT(x)           (((x) >> 20) & 0x1)
-#define   C_000044_ATI_OVERDRIVE_INT_STAT              0xFFEFFFFF
-#define   S_000044_MC_PROTECTION_FAULT_STAT(x)         (((x) & 0x1) << 21)
-#define   G_000044_MC_PROTECTION_FAULT_STAT(x)         (((x) >> 21) & 0x1)
-#define   C_000044_MC_PROTECTION_FAULT_STAT            0xFFDFFFFF
-#define   S_000044_RBBM_READ_INT_STAT(x)               (((x) & 0x1) << 22)
-#define   G_000044_RBBM_READ_INT_STAT(x)               (((x) >> 22) & 0x1)
-#define   C_000044_RBBM_READ_INT_STAT                  0xFFBFFFFF
-#define   S_000044_CB_CONTEXT_SWITCH_STAT(x)           (((x) & 0x1) << 23)
-#define   G_000044_CB_CONTEXT_SWITCH_STAT(x)           (((x) >> 23) & 0x1)
-#define   C_000044_CB_CONTEXT_SWITCH_STAT              0xFF7FFFFF
-#define   S_000044_VIPH_INT(x)                         (((x) & 0x1) << 24)
-#define   G_000044_VIPH_INT(x)                         (((x) >> 24) & 0x1)
-#define   C_000044_VIPH_INT                            0xFEFFFFFF
-#define   S_000044_SW_INT(x)                           (((x) & 0x1) << 25)
-#define   G_000044_SW_INT(x)                           (((x) >> 25) & 0x1)
-#define   C_000044_SW_INT                              0xFDFFFFFF
-#define   S_000044_SW_INT_SET(x)                       (((x) & 0x1) << 26)
-#define   G_000044_SW_INT_SET(x)                       (((x) >> 26) & 0x1)
-#define   C_000044_SW_INT_SET                          0xFBFFFFFF
-#define   S_000044_IDCT_INT_STAT(x)                    (((x) & 0x1) << 27)
-#define   G_000044_IDCT_INT_STAT(x)                    (((x) >> 27) & 0x1)
-#define   C_000044_IDCT_INT_STAT                       0xF7FFFFFF
-#define   S_000044_GUIDMA_STAT(x)                      (((x) & 0x1) << 30)
-#define   G_000044_GUIDMA_STAT(x)                      (((x) >> 30) & 0x1)
-#define   C_000044_GUIDMA_STAT                         0xBFFFFFFF
-#define   S_000044_VIDDMA_STAT(x)                      (((x) & 0x1) << 31)
-#define   G_000044_VIDDMA_STAT(x)                      (((x) >> 31) & 0x1)
-#define   C_000044_VIDDMA_STAT                         0x7FFFFFFF
-#define R_00004C_BUS_CNTL                            0x00004C
-#define   S_00004C_BUS_MASTER_DIS(x)                   (((x) & 0x1) << 14)
-#define   G_00004C_BUS_MASTER_DIS(x)                   (((x) >> 14) & 0x1)
-#define   C_00004C_BUS_MASTER_DIS                      0xFFFFBFFF
-#define   S_00004C_BUS_MSI_REARM(x)                    (((x) & 0x1) << 20)
-#define   G_00004C_BUS_MSI_REARM(x)                    (((x) >> 20) & 0x1)
-#define   C_00004C_BUS_MSI_REARM                       0xFFEFFFFF
-#define R_000070_MC_IND_INDEX                        0x000070
-#define   S_000070_MC_IND_ADDR(x)                      (((x) & 0xFFFF) << 0)
-#define   G_000070_MC_IND_ADDR(x)                      (((x) >> 0) & 0xFFFF)
-#define   C_000070_MC_IND_ADDR                         0xFFFF0000
-#define   S_000070_MC_IND_SEQ_RBS_0(x)                 (((x) & 0x1) << 16)
-#define   G_000070_MC_IND_SEQ_RBS_0(x)                 (((x) >> 16) & 0x1)
-#define   C_000070_MC_IND_SEQ_RBS_0                    0xFFFEFFFF
-#define   S_000070_MC_IND_SEQ_RBS_1(x)                 (((x) & 0x1) << 17)
-#define   G_000070_MC_IND_SEQ_RBS_1(x)                 (((x) >> 17) & 0x1)
-#define   C_000070_MC_IND_SEQ_RBS_1                    0xFFFDFFFF
-#define   S_000070_MC_IND_SEQ_RBS_2(x)                 (((x) & 0x1) << 18)
-#define   G_000070_MC_IND_SEQ_RBS_2(x)                 (((x) >> 18) & 0x1)
-#define   C_000070_MC_IND_SEQ_RBS_2                    0xFFFBFFFF
-#define   S_000070_MC_IND_SEQ_RBS_3(x)                 (((x) & 0x1) << 19)
-#define   G_000070_MC_IND_SEQ_RBS_3(x)                 (((x) >> 19) & 0x1)
-#define   C_000070_MC_IND_SEQ_RBS_3                    0xFFF7FFFF
-#define   S_000070_MC_IND_AIC_RBS(x)                   (((x) & 0x1) << 20)
-#define   G_000070_MC_IND_AIC_RBS(x)                   (((x) >> 20) & 0x1)
-#define   C_000070_MC_IND_AIC_RBS                      0xFFEFFFFF
-#define   S_000070_MC_IND_CITF_ARB0(x)                 (((x) & 0x1) << 21)
-#define   G_000070_MC_IND_CITF_ARB0(x)                 (((x) >> 21) & 0x1)
-#define   C_000070_MC_IND_CITF_ARB0                    0xFFDFFFFF
-#define   S_000070_MC_IND_CITF_ARB1(x)                 (((x) & 0x1) << 22)
-#define   G_000070_MC_IND_CITF_ARB1(x)                 (((x) >> 22) & 0x1)
-#define   C_000070_MC_IND_CITF_ARB1                    0xFFBFFFFF
-#define   S_000070_MC_IND_WR_EN(x)                     (((x) & 0x1) << 23)
-#define   G_000070_MC_IND_WR_EN(x)                     (((x) >> 23) & 0x1)
-#define   C_000070_MC_IND_WR_EN                        0xFF7FFFFF
-#define   S_000070_MC_IND_RD_INV(x)                    (((x) & 0x1) << 24)
-#define   G_000070_MC_IND_RD_INV(x)                    (((x) >> 24) & 0x1)
-#define   C_000070_MC_IND_RD_INV                       0xFEFFFFFF
-#define R_000074_MC_IND_DATA                         0x000074
-#define   S_000074_MC_IND_DATA(x)                      (((x) & 0xFFFFFFFF) << 0)
-#define   G_000074_MC_IND_DATA(x)                      (((x) >> 0) & 0xFFFFFFFF)
-#define   C_000074_MC_IND_DATA                         0x00000000
-#define R_0000F0_RBBM_SOFT_RESET                     0x0000F0
-#define   S_0000F0_SOFT_RESET_CP(x)                    (((x) & 0x1) << 0)
-#define   G_0000F0_SOFT_RESET_CP(x)                    (((x) >> 0) & 0x1)
-#define   C_0000F0_SOFT_RESET_CP                       0xFFFFFFFE
-#define   S_0000F0_SOFT_RESET_HI(x)                    (((x) & 0x1) << 1)
-#define   G_0000F0_SOFT_RESET_HI(x)                    (((x) >> 1) & 0x1)
-#define   C_0000F0_SOFT_RESET_HI                       0xFFFFFFFD
-#define   S_0000F0_SOFT_RESET_VAP(x)                   (((x) & 0x1) << 2)
-#define   G_0000F0_SOFT_RESET_VAP(x)                   (((x) >> 2) & 0x1)
-#define   C_0000F0_SOFT_RESET_VAP                      0xFFFFFFFB
-#define   S_0000F0_SOFT_RESET_RE(x)                    (((x) & 0x1) << 3)
-#define   G_0000F0_SOFT_RESET_RE(x)                    (((x) >> 3) & 0x1)
-#define   C_0000F0_SOFT_RESET_RE                       0xFFFFFFF7
-#define   S_0000F0_SOFT_RESET_PP(x)                    (((x) & 0x1) << 4)
-#define   G_0000F0_SOFT_RESET_PP(x)                    (((x) >> 4) & 0x1)
-#define   C_0000F0_SOFT_RESET_PP                       0xFFFFFFEF
-#define   S_0000F0_SOFT_RESET_E2(x)                    (((x) & 0x1) << 5)
-#define   G_0000F0_SOFT_RESET_E2(x)                    (((x) >> 5) & 0x1)
-#define   C_0000F0_SOFT_RESET_E2                       0xFFFFFFDF
-#define   S_0000F0_SOFT_RESET_RB(x)                    (((x) & 0x1) << 6)
-#define   G_0000F0_SOFT_RESET_RB(x)                    (((x) >> 6) & 0x1)
-#define   C_0000F0_SOFT_RESET_RB                       0xFFFFFFBF
-#define   S_0000F0_SOFT_RESET_HDP(x)                   (((x) & 0x1) << 7)
-#define   G_0000F0_SOFT_RESET_HDP(x)                   (((x) >> 7) & 0x1)
-#define   C_0000F0_SOFT_RESET_HDP                      0xFFFFFF7F
-#define   S_0000F0_SOFT_RESET_MC(x)                    (((x) & 0x1) << 8)
-#define   G_0000F0_SOFT_RESET_MC(x)                    (((x) >> 8) & 0x1)
-#define   C_0000F0_SOFT_RESET_MC                       0xFFFFFEFF
-#define   S_0000F0_SOFT_RESET_AIC(x)                   (((x) & 0x1) << 9)
-#define   G_0000F0_SOFT_RESET_AIC(x)                   (((x) >> 9) & 0x1)
-#define   C_0000F0_SOFT_RESET_AIC                      0xFFFFFDFF
-#define   S_0000F0_SOFT_RESET_VIP(x)                   (((x) & 0x1) << 10)
-#define   G_0000F0_SOFT_RESET_VIP(x)                   (((x) >> 10) & 0x1)
-#define   C_0000F0_SOFT_RESET_VIP                      0xFFFFFBFF
-#define   S_0000F0_SOFT_RESET_DISP(x)                  (((x) & 0x1) << 11)
-#define   G_0000F0_SOFT_RESET_DISP(x)                  (((x) >> 11) & 0x1)
-#define   C_0000F0_SOFT_RESET_DISP                     0xFFFFF7FF
-#define   S_0000F0_SOFT_RESET_CG(x)                    (((x) & 0x1) << 12)
-#define   G_0000F0_SOFT_RESET_CG(x)                    (((x) >> 12) & 0x1)
-#define   C_0000F0_SOFT_RESET_CG                       0xFFFFEFFF
-#define   S_0000F0_SOFT_RESET_GA(x)                    (((x) & 0x1) << 13)
-#define   G_0000F0_SOFT_RESET_GA(x)                    (((x) >> 13) & 0x1)
-#define   C_0000F0_SOFT_RESET_GA                       0xFFFFDFFF
-#define   S_0000F0_SOFT_RESET_IDCT(x)                  (((x) & 0x1) << 14)
-#define   G_0000F0_SOFT_RESET_IDCT(x)                  (((x) >> 14) & 0x1)
-#define   C_0000F0_SOFT_RESET_IDCT                     0xFFFFBFFF
-#define R_000134_HDP_FB_LOCATION                     0x000134
-#define   S_000134_HDP_FB_START(x)                     (((x) & 0xFFFF) << 0)
-#define   G_000134_HDP_FB_START(x)                     (((x) >> 0) & 0xFFFF)
-#define   C_000134_HDP_FB_START                        0xFFFF0000
-#define R_0007C0_CP_STAT                             0x0007C0
-#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
-#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
-#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
-#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
-#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
-#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
-#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
-#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
-#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
-#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
-#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
-#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
-#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
-#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
-#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
-#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
-#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
-#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
-#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
-#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
-#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
-#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
-#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
-#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
-#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
-#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
-#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
-#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
-#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
-#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
-#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
-#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
-#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
-#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
-#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
-#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
-#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
-#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
-#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
-#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
-#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
-#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
-#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
-#define R_000E40_RBBM_STATUS                         0x000E40
-#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
-#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
-#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
-#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
-#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
-#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
-#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
-#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
-#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
-#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
-#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
-#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
-#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
-#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
-#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
-#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
-#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
-#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
-#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
-#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
-#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
-#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
-#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
-#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
-#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
-#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
-#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
-#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
-#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
-#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
-#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
-#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
-#define   C_000E40_E2_BUSY                             0xFFFDFFFF
-#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
-#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
-#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
-#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
-#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
-#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
-#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
-#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
-#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
-#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
-#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
-#define   C_000E40_RE_BUSY                             0xFFDFFFFF
-#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
-#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
-#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
-#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
-#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
-#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
-#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
-#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
-#define   C_000E40_PB_BUSY                             0xFEFFFFFF
-#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
-#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
-#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
-#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
-#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
-#define   C_000E40_GA_BUSY                             0xFBFFFFFF
-#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
-#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
-#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
-#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
-#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
-#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
-#define R_0060A4_D1CRTC_STATUS_FRAME_COUNT           0x0060A4
-#define   S_0060A4_D1CRTC_FRAME_COUNT(x)               (((x) & 0xFFFFFF) << 0)
-#define   G_0060A4_D1CRTC_FRAME_COUNT(x)               (((x) >> 0) & 0xFFFFFF)
-#define   C_0060A4_D1CRTC_FRAME_COUNT                  0xFF000000
-#define R_006534_D1MODE_VBLANK_STATUS                0x006534
-#define   S_006534_D1MODE_VBLANK_OCCURRED(x)           (((x) & 0x1) << 0)
-#define   G_006534_D1MODE_VBLANK_OCCURRED(x)           (((x) >> 0) & 0x1)
-#define   C_006534_D1MODE_VBLANK_OCCURRED              0xFFFFFFFE
-#define   S_006534_D1MODE_VBLANK_ACK(x)                (((x) & 0x1) << 4)
-#define   G_006534_D1MODE_VBLANK_ACK(x)                (((x) >> 4) & 0x1)
-#define   C_006534_D1MODE_VBLANK_ACK                   0xFFFFFFEF
-#define   S_006534_D1MODE_VBLANK_STAT(x)               (((x) & 0x1) << 12)
-#define   G_006534_D1MODE_VBLANK_STAT(x)               (((x) >> 12) & 0x1)
-#define   C_006534_D1MODE_VBLANK_STAT                  0xFFFFEFFF
-#define   S_006534_D1MODE_VBLANK_INTERRUPT(x)          (((x) & 0x1) << 16)
-#define   G_006534_D1MODE_VBLANK_INTERRUPT(x)          (((x) >> 16) & 0x1)
-#define   C_006534_D1MODE_VBLANK_INTERRUPT             0xFFFEFFFF
-#define R_006540_DxMODE_INT_MASK                     0x006540
-#define   S_006540_D1MODE_VBLANK_INT_MASK(x)           (((x) & 0x1) << 0)
-#define   G_006540_D1MODE_VBLANK_INT_MASK(x)           (((x) >> 0) & 0x1)
-#define   C_006540_D1MODE_VBLANK_INT_MASK              0xFFFFFFFE
-#define   S_006540_D1MODE_VLINE_INT_MASK(x)            (((x) & 0x1) << 4)
-#define   G_006540_D1MODE_VLINE_INT_MASK(x)            (((x) >> 4) & 0x1)
-#define   C_006540_D1MODE_VLINE_INT_MASK               0xFFFFFFEF
-#define   S_006540_D2MODE_VBLANK_INT_MASK(x)           (((x) & 0x1) << 8)
-#define   G_006540_D2MODE_VBLANK_INT_MASK(x)           (((x) >> 8) & 0x1)
-#define   C_006540_D2MODE_VBLANK_INT_MASK              0xFFFFFEFF
-#define   S_006540_D2MODE_VLINE_INT_MASK(x)            (((x) & 0x1) << 12)
-#define   G_006540_D2MODE_VLINE_INT_MASK(x)            (((x) >> 12) & 0x1)
-#define   C_006540_D2MODE_VLINE_INT_MASK               0xFFFFEFFF
-#define   S_006540_D1MODE_VBLANK_CP_SEL(x)             (((x) & 0x1) << 30)
-#define   G_006540_D1MODE_VBLANK_CP_SEL(x)             (((x) >> 30) & 0x1)
-#define   C_006540_D1MODE_VBLANK_CP_SEL                0xBFFFFFFF
-#define   S_006540_D2MODE_VBLANK_CP_SEL(x)             (((x) & 0x1) << 31)
-#define   G_006540_D2MODE_VBLANK_CP_SEL(x)             (((x) >> 31) & 0x1)
-#define   C_006540_D2MODE_VBLANK_CP_SEL                0x7FFFFFFF
-#define R_0068A4_D2CRTC_STATUS_FRAME_COUNT           0x0068A4
-#define   S_0068A4_D2CRTC_FRAME_COUNT(x)               (((x) & 0xFFFFFF) << 0)
-#define   G_0068A4_D2CRTC_FRAME_COUNT(x)               (((x) >> 0) & 0xFFFFFF)
-#define   C_0068A4_D2CRTC_FRAME_COUNT                  0xFF000000
-#define R_006D34_D2MODE_VBLANK_STATUS                0x006D34
-#define   S_006D34_D2MODE_VBLANK_OCCURRED(x)           (((x) & 0x1) << 0)
-#define   G_006D34_D2MODE_VBLANK_OCCURRED(x)           (((x) >> 0) & 0x1)
-#define   C_006D34_D2MODE_VBLANK_OCCURRED              0xFFFFFFFE
-#define   S_006D34_D2MODE_VBLANK_ACK(x)                (((x) & 0x1) << 4)
-#define   G_006D34_D2MODE_VBLANK_ACK(x)                (((x) >> 4) & 0x1)
-#define   C_006D34_D2MODE_VBLANK_ACK                   0xFFFFFFEF
-#define   S_006D34_D2MODE_VBLANK_STAT(x)               (((x) & 0x1) << 12)
-#define   G_006D34_D2MODE_VBLANK_STAT(x)               (((x) >> 12) & 0x1)
-#define   C_006D34_D2MODE_VBLANK_STAT                  0xFFFFEFFF
-#define   S_006D34_D2MODE_VBLANK_INTERRUPT(x)          (((x) & 0x1) << 16)
-#define   G_006D34_D2MODE_VBLANK_INTERRUPT(x)          (((x) >> 16) & 0x1)
-#define   C_006D34_D2MODE_VBLANK_INTERRUPT             0xFFFEFFFF
-#define R_007EDC_DISP_INTERRUPT_STATUS               0x007EDC
-#define   S_007EDC_LB_D1_VBLANK_INTERRUPT(x)           (((x) & 0x1) << 4)
-#define   G_007EDC_LB_D1_VBLANK_INTERRUPT(x)           (((x) >> 4) & 0x1)
-#define   C_007EDC_LB_D1_VBLANK_INTERRUPT              0xFFFFFFEF
-#define   S_007EDC_LB_D2_VBLANK_INTERRUPT(x)           (((x) & 0x1) << 5)
-#define   G_007EDC_LB_D2_VBLANK_INTERRUPT(x)           (((x) >> 5) & 0x1)
-#define   C_007EDC_LB_D2_VBLANK_INTERRUPT              0xFFFFFFDF
-#define   S_007EDC_DACA_AUTODETECT_INTERRUPT(x)        (((x) & 0x1) << 16)
-#define   G_007EDC_DACA_AUTODETECT_INTERRUPT(x)        (((x) >> 16) & 0x1)
-#define   C_007EDC_DACA_AUTODETECT_INTERRUPT           0xFFFEFFFF
-#define   S_007EDC_DACB_AUTODETECT_INTERRUPT(x)        (((x) & 0x1) << 17)
-#define   G_007EDC_DACB_AUTODETECT_INTERRUPT(x)        (((x) >> 17) & 0x1)
-#define   C_007EDC_DACB_AUTODETECT_INTERRUPT           0xFFFDFFFF
-#define   S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x)    (((x) & 0x1) << 18)
-#define   G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x)    (((x) >> 18) & 0x1)
-#define   C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT       0xFFFBFFFF
-#define   S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x)    (((x) & 0x1) << 19)
-#define   G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x)    (((x) >> 19) & 0x1)
-#define   C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT       0xFFF7FFFF
-#define R_007828_DACA_AUTODETECT_CONTROL               0x007828
-#define   S_007828_DACA_AUTODETECT_MODE(x)             (((x) & 0x3) << 0)
-#define   G_007828_DACA_AUTODETECT_MODE(x)             (((x) >> 0) & 0x3)
-#define   C_007828_DACA_AUTODETECT_MODE                0xFFFFFFFC
-#define   S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)
-#define   G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)
-#define   C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER  0xFFFF00FF
-#define   S_007828_DACA_AUTODETECT_CHECK_MASK(x)       (((x) & 0x3) << 16)
-#define   G_007828_DACA_AUTODETECT_CHECK_MASK(x)       (((x) >> 16) & 0x3)
-#define   C_007828_DACA_AUTODETECT_CHECK_MASK          0xFFFCFFFF
-#define R_007838_DACA_AUTODETECT_INT_CONTROL           0x007838
-#define   S_007838_DACA_AUTODETECT_ACK(x)              (((x) & 0x1) << 0)
-#define   C_007838_DACA_DACA_AUTODETECT_ACK            0xFFFFFFFE
-#define   S_007838_DACA_AUTODETECT_INT_ENABLE(x)       (((x) & 0x1) << 16)
-#define   G_007838_DACA_AUTODETECT_INT_ENABLE(x)       (((x) >> 16) & 0x1)
-#define   C_007838_DACA_AUTODETECT_INT_ENABLE          0xFFFCFFFF
-#define R_007A28_DACB_AUTODETECT_CONTROL               0x007A28
-#define   S_007A28_DACB_AUTODETECT_MODE(x)             (((x) & 0x3) << 0)
-#define   G_007A28_DACB_AUTODETECT_MODE(x)             (((x) >> 0) & 0x3)
-#define   C_007A28_DACB_AUTODETECT_MODE                0xFFFFFFFC
-#define   S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)
-#define   G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)
-#define   C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER  0xFFFF00FF
-#define   S_007A28_DACB_AUTODETECT_CHECK_MASK(x)       (((x) & 0x3) << 16)
-#define   G_007A28_DACB_AUTODETECT_CHECK_MASK(x)       (((x) >> 16) & 0x3)
-#define   C_007A28_DACB_AUTODETECT_CHECK_MASK          0xFFFCFFFF
-#define R_007A38_DACB_AUTODETECT_INT_CONTROL           0x007A38
-#define   S_007A38_DACB_AUTODETECT_ACK(x)              (((x) & 0x1) << 0)
-#define   C_007A38_DACB_DACA_AUTODETECT_ACK            0xFFFFFFFE
-#define   S_007A38_DACB_AUTODETECT_INT_ENABLE(x)       (((x) & 0x1) << 16)
-#define   G_007A38_DACB_AUTODETECT_INT_ENABLE(x)       (((x) >> 16) & 0x1)
-#define   C_007A38_DACB_AUTODETECT_INT_ENABLE          0xFFFCFFFF
-#define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL           0x007D00
-#define   S_007D00_DC_HOT_PLUG_DETECT1_EN(x)           (((x) & 0x1) << 0)
-#define   G_007D00_DC_HOT_PLUG_DETECT1_EN(x)           (((x) >> 0) & 0x1)
-#define   C_007D00_DC_HOT_PLUG_DETECT1_EN              0xFFFFFFFE
-#define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS        0x007D04
-#define   S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x)   (((x) & 0x1) << 0)
-#define   G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x)   (((x) >> 0) & 0x1)
-#define   C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS      0xFFFFFFFE
-#define   S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x)        (((x) & 0x1) << 1)
-#define   G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x)        (((x) >> 1) & 0x1)
-#define   C_007D04_DC_HOT_PLUG_DETECT1_SENSE           0xFFFFFFFD
-#define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL       0x007D08
-#define   S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x)      (((x) & 0x1) << 0)
-#define   C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK         0xFFFFFFFE
-#define   S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8)
-#define   G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1)
-#define   C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY    0xFFFFFEFF
-#define   S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x)       (((x) & 0x1) << 16)
-#define   G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x)       (((x) >> 16) & 0x1)
-#define   C_007D08_DC_HOT_PLUG_DETECT1_INT_EN          0xFFFEFFFF
-#define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL           0x007D10
-#define   S_007D10_DC_HOT_PLUG_DETECT2_EN(x)           (((x) & 0x1) << 0)
-#define   G_007D10_DC_HOT_PLUG_DETECT2_EN(x)           (((x) >> 0) & 0x1)
-#define   C_007D10_DC_HOT_PLUG_DETECT2_EN              0xFFFFFFFE
-#define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS        0x007D14
-#define   S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x)   (((x) & 0x1) << 0)
-#define   G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x)   (((x) >> 0) & 0x1)
-#define   C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS      0xFFFFFFFE
-#define   S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x)        (((x) & 0x1) << 1)
-#define   G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x)        (((x) >> 1) & 0x1)
-#define   C_007D14_DC_HOT_PLUG_DETECT2_SENSE           0xFFFFFFFD
-#define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL       0x007D18
-#define   S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x)      (((x) & 0x1) << 0)
-#define   C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK         0xFFFFFFFE
-#define   S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8)
-#define   G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1)
-#define   C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY    0xFFFFFEFF
-#define   S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x)       (((x) & 0x1) << 16)
-#define   G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x)       (((x) >> 16) & 0x1)
-#define   C_007D18_DC_HOT_PLUG_DETECT2_INT_EN          0xFFFEFFFF
-#define R_007404_HDMI0_STATUS                          0x007404
-#define   S_007404_HDMI0_AZ_FORMAT_WTRIG(x)            (((x) & 0x1) << 28)
-#define   G_007404_HDMI0_AZ_FORMAT_WTRIG(x)            (((x) >> 28) & 0x1)
-#define   C_007404_HDMI0_AZ_FORMAT_WTRIG               0xEFFFFFFF
-#define   S_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x)        (((x) & 0x1) << 29)
-#define   G_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x)        (((x) >> 29) & 0x1)
-#define   C_007404_HDMI0_AZ_FORMAT_WTRIG_INT           0xDFFFFFFF
-#define R_007408_HDMI0_AUDIO_PACKET_CONTROL            0x007408
-#define   S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x)       (((x) & 0x1) << 28)
-#define   G_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x)       (((x) >> 28) & 0x1)
-#define   C_007408_HDMI0_AZ_FORMAT_WTRIG_MASK          0xEFFFFFFF
-#define   S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x)        (((x) & 0x1) << 29)
-#define   G_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x)        (((x) >> 29) & 0x1)
-#define   C_007408_HDMI0_AZ_FORMAT_WTRIG_ACK           0xDFFFFFFF
-
-/* MC registers */
-#define R_000000_MC_STATUS                           0x000000
-#define   S_000000_MC_IDLE(x)                          (((x) & 0x1) << 0)
-#define   G_000000_MC_IDLE(x)                          (((x) >> 0) & 0x1)
-#define   C_000000_MC_IDLE                             0xFFFFFFFE
-#define R_000004_MC_FB_LOCATION                      0x000004
-#define   S_000004_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
-#define   G_000004_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
-#define   C_000004_MC_FB_START                         0xFFFF0000
-#define   S_000004_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
-#define   G_000004_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
-#define   C_000004_MC_FB_TOP                           0x0000FFFF
-#define R_000005_MC_AGP_LOCATION                     0x000005
-#define   S_000005_MC_AGP_START(x)                     (((x) & 0xFFFF) << 0)
-#define   G_000005_MC_AGP_START(x)                     (((x) >> 0) & 0xFFFF)
-#define   C_000005_MC_AGP_START                        0xFFFF0000
-#define   S_000005_MC_AGP_TOP(x)                       (((x) & 0xFFFF) << 16)
-#define   G_000005_MC_AGP_TOP(x)                       (((x) >> 16) & 0xFFFF)
-#define   C_000005_MC_AGP_TOP                          0x0000FFFF
-#define R_000006_AGP_BASE                            0x000006
-#define   S_000006_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
-#define   G_000006_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
-#define   C_000006_AGP_BASE_ADDR                       0x00000000
-#define R_000007_AGP_BASE_2                          0x000007
-#define   S_000007_AGP_BASE_ADDR_2(x)                  (((x) & 0xF) << 0)
-#define   G_000007_AGP_BASE_ADDR_2(x)                  (((x) >> 0) & 0xF)
-#define   C_000007_AGP_BASE_ADDR_2                     0xFFFFFFF0
-#define R_000009_MC_CNTL1                            0x000009
-#define   S_000009_ENABLE_PAGE_TABLES(x)               (((x) & 0x1) << 26)
-#define   G_000009_ENABLE_PAGE_TABLES(x)               (((x) >> 26) & 0x1)
-#define   C_000009_ENABLE_PAGE_TABLES                  0xFBFFFFFF
-/* FIXME don't know the various field size need feedback from AMD */
-#define R_000100_MC_PT0_CNTL                         0x000100
-#define   S_000100_ENABLE_PT(x)                        (((x) & 0x1) << 0)
-#define   G_000100_ENABLE_PT(x)                        (((x) >> 0) & 0x1)
-#define   C_000100_ENABLE_PT                           0xFFFFFFFE
-#define   S_000100_EFFECTIVE_L2_CACHE_SIZE(x)          (((x) & 0x7) << 15)
-#define   G_000100_EFFECTIVE_L2_CACHE_SIZE(x)          (((x) >> 15) & 0x7)
-#define   C_000100_EFFECTIVE_L2_CACHE_SIZE             0xFFFC7FFF
-#define   S_000100_EFFECTIVE_L2_QUEUE_SIZE(x)          (((x) & 0x7) << 21)
-#define   G_000100_EFFECTIVE_L2_QUEUE_SIZE(x)          (((x) >> 21) & 0x7)
-#define   C_000100_EFFECTIVE_L2_QUEUE_SIZE             0xFF1FFFFF
-#define   S_000100_INVALIDATE_ALL_L1_TLBS(x)           (((x) & 0x1) << 28)
-#define   G_000100_INVALIDATE_ALL_L1_TLBS(x)           (((x) >> 28) & 0x1)
-#define   C_000100_INVALIDATE_ALL_L1_TLBS              0xEFFFFFFF
-#define   S_000100_INVALIDATE_L2_CACHE(x)              (((x) & 0x1) << 29)
-#define   G_000100_INVALIDATE_L2_CACHE(x)              (((x) >> 29) & 0x1)
-#define   C_000100_INVALIDATE_L2_CACHE                 0xDFFFFFFF
-#define R_000102_MC_PT0_CONTEXT0_CNTL                0x000102
-#define   S_000102_ENABLE_PAGE_TABLE(x)                (((x) & 0x1) << 0)
-#define   G_000102_ENABLE_PAGE_TABLE(x)                (((x) >> 0) & 0x1)
-#define   C_000102_ENABLE_PAGE_TABLE                   0xFFFFFFFE
-#define   S_000102_PAGE_TABLE_DEPTH(x)                 (((x) & 0x3) << 1)
-#define   G_000102_PAGE_TABLE_DEPTH(x)                 (((x) >> 1) & 0x3)
-#define   C_000102_PAGE_TABLE_DEPTH                    0xFFFFFFF9
-#define   V_000102_PAGE_TABLE_FLAT                     0
-/* R600 documentation suggest that this should be a number of pages */
-#define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR     0x000112
-#define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR    0x000114
-#define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR   0x00011C
-#define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR      0x00012C
-#define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR     0x00013C
-#define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR       0x00014C
-#define R_00016C_MC_PT0_CLIENT0_CNTL                 0x00016C
-#define   S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0)
-#define   G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1)
-#define   C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE    0xFFFFFFFE
-#define   S_00016C_TRANSLATION_MODE_OVERRIDE(x)        (((x) & 0x1) << 1)
-#define   G_00016C_TRANSLATION_MODE_OVERRIDE(x)        (((x) >> 1) & 0x1)
-#define   C_00016C_TRANSLATION_MODE_OVERRIDE           0xFFFFFFFD
-#define   S_00016C_SYSTEM_ACCESS_MODE_MASK(x)          (((x) & 0x3) << 8)
-#define   G_00016C_SYSTEM_ACCESS_MODE_MASK(x)          (((x) >> 8) & 0x3)
-#define   C_00016C_SYSTEM_ACCESS_MODE_MASK             0xFFFFFCFF
-#define   V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY          0
-#define   V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP      1
-#define   V_00016C_SYSTEM_ACCESS_MODE_IN_SYS           2
-#define   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS       3
-#define   S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x)  (((x) & 0x1) << 10)
-#define   G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x)  (((x) >> 10) & 0x1)
-#define   C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS     0xFFFFFBFF
-#define   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH  0
-#define   V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1
-#define   S_00016C_EFFECTIVE_L1_CACHE_SIZE(x)          (((x) & 0x7) << 11)
-#define   G_00016C_EFFECTIVE_L1_CACHE_SIZE(x)          (((x) >> 11) & 0x7)
-#define   C_00016C_EFFECTIVE_L1_CACHE_SIZE             0xFFFFC7FF
-#define   S_00016C_ENABLE_FRAGMENT_PROCESSING(x)       (((x) & 0x1) << 14)
-#define   G_00016C_ENABLE_FRAGMENT_PROCESSING(x)       (((x) >> 14) & 0x1)
-#define   C_00016C_ENABLE_FRAGMENT_PROCESSING          0xFFFFBFFF
-#define   S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x)          (((x) & 0x7) << 15)
-#define   G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x)          (((x) >> 15) & 0x7)
-#define   C_00016C_EFFECTIVE_L1_QUEUE_SIZE             0xFFFC7FFF
-#define   S_00016C_INVALIDATE_L1_TLB(x)                (((x) & 0x1) << 20)
-#define   G_00016C_INVALIDATE_L1_TLB(x)                (((x) >> 20) & 0x1)
-#define   C_00016C_INVALIDATE_L1_TLB                   0xFFEFFFFF
-
-#define R_006548_D1MODE_PRIORITY_A_CNT               0x006548
-#define   S_006548_D1MODE_PRIORITY_MARK_A(x)           (((x) & 0x7FFF) << 0)
-#define   G_006548_D1MODE_PRIORITY_MARK_A(x)           (((x) >> 0) & 0x7FFF)
-#define   C_006548_D1MODE_PRIORITY_MARK_A              0xFFFF8000
-#define   S_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) & 0x1) << 16)
-#define   G_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) >> 16) & 0x1)
-#define   C_006548_D1MODE_PRIORITY_A_OFF               0xFFFEFFFF
-#define   S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) & 0x1) << 20)
-#define   G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
-#define   C_006548_D1MODE_PRIORITY_A_ALWAYS_ON         0xFFEFFFFF
-#define   S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) & 0x1) << 24)
-#define   G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) >> 24) & 0x1)
-#define   C_006548_D1MODE_PRIORITY_A_FORCE_MASK        0xFEFFFFFF
-#define R_00654C_D1MODE_PRIORITY_B_CNT               0x00654C
-#define   S_00654C_D1MODE_PRIORITY_MARK_B(x)           (((x) & 0x7FFF) << 0)
-#define   G_00654C_D1MODE_PRIORITY_MARK_B(x)           (((x) >> 0) & 0x7FFF)
-#define   C_00654C_D1MODE_PRIORITY_MARK_B              0xFFFF8000
-#define   S_00654C_D1MODE_PRIORITY_B_OFF(x)            (((x) & 0x1) << 16)
-#define   G_00654C_D1MODE_PRIORITY_B_OFF(x)            (((x) >> 16) & 0x1)
-#define   C_00654C_D1MODE_PRIORITY_B_OFF               0xFFFEFFFF
-#define   S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) & 0x1) << 20)
-#define   G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
-#define   C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON         0xFFEFFFFF
-#define   S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)     (((x) & 0x1) << 24)
-#define   G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)     (((x) >> 24) & 0x1)
-#define   C_00654C_D1MODE_PRIORITY_B_FORCE_MASK        0xFEFFFFFF
-#define R_006D48_D2MODE_PRIORITY_A_CNT               0x006D48
-#define   S_006D48_D2MODE_PRIORITY_MARK_A(x)           (((x) & 0x7FFF) << 0)
-#define   G_006D48_D2MODE_PRIORITY_MARK_A(x)           (((x) >> 0) & 0x7FFF)
-#define   C_006D48_D2MODE_PRIORITY_MARK_A              0xFFFF8000
-#define   S_006D48_D2MODE_PRIORITY_A_OFF(x)            (((x) & 0x1) << 16)
-#define   G_006D48_D2MODE_PRIORITY_A_OFF(x)            (((x) >> 16) & 0x1)
-#define   C_006D48_D2MODE_PRIORITY_A_OFF               0xFFFEFFFF
-#define   S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) & 0x1) << 20)
-#define   G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
-#define   C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON         0xFFEFFFFF
-#define   S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)     (((x) & 0x1) << 24)
-#define   G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)     (((x) >> 24) & 0x1)
-#define   C_006D48_D2MODE_PRIORITY_A_FORCE_MASK        0xFEFFFFFF
-#define R_006D4C_D2MODE_PRIORITY_B_CNT               0x006D4C
-#define   S_006D4C_D2MODE_PRIORITY_MARK_B(x)           (((x) & 0x7FFF) << 0)
-#define   G_006D4C_D2MODE_PRIORITY_MARK_B(x)           (((x) >> 0) & 0x7FFF)
-#define   C_006D4C_D2MODE_PRIORITY_MARK_B              0xFFFF8000
-#define   S_006D4C_D2MODE_PRIORITY_B_OFF(x)            (((x) & 0x1) << 16)
-#define   G_006D4C_D2MODE_PRIORITY_B_OFF(x)            (((x) >> 16) & 0x1)
-#define   C_006D4C_D2MODE_PRIORITY_B_OFF               0xFFFEFFFF
-#define   S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) & 0x1) << 20)
-#define   G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
-#define   C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON         0xFFEFFFFF
-#define   S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)     (((x) & 0x1) << 24)
-#define   G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)     (((x) >> 24) & 0x1)
-#define   C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK        0xFEFFFFFF
-
-/* PLL regs */
-#define GENERAL_PWRMGT                                 0x8
-#define   GLOBAL_PWRMGT_EN                             (1 << 0)
-#define   MOBILE_SU                                    (1 << 2)
-#define DYN_PWRMGT_SCLK_LENGTH                         0xc
-#define   NORMAL_POWER_SCLK_HILEN(x)                   ((x) << 0)
-#define   NORMAL_POWER_SCLK_LOLEN(x)                   ((x) << 4)
-#define   REDUCED_POWER_SCLK_HILEN(x)                  ((x) << 8)
-#define   REDUCED_POWER_SCLK_LOLEN(x)                  ((x) << 12)
-#define   POWER_D1_SCLK_HILEN(x)                       ((x) << 16)
-#define   POWER_D1_SCLK_LOLEN(x)                       ((x) << 20)
-#define   STATIC_SCREEN_HILEN(x)                       ((x) << 24)
-#define   STATIC_SCREEN_LOLEN(x)                       ((x) << 28)
-#define DYN_SCLK_VOL_CNTL                              0xe
-#define   IO_CG_VOLTAGE_DROP                           (1 << 0)
-#define   VOLTAGE_DROP_SYNC                            (1 << 2)
-#define   VOLTAGE_DELAY_SEL(x)                         ((x) << 3)
-#define HDP_DYN_CNTL                                   0x10
-#define   HDP_FORCEON                                  (1 << 0)
-#define MC_HOST_DYN_CNTL                               0x1e
-#define   MC_HOST_FORCEON                              (1 << 0)
-#define DYN_BACKBIAS_CNTL                              0x29
-#define   IO_CG_BACKBIAS_EN                            (1 << 0)
-
-/* mmreg */
-#define DOUT_POWER_MANAGEMENT_CNTL                     0x7ee0
-#define   PWRDN_WAIT_BUSY_OFF                          (1 << 0)
-#define   PWRDN_WAIT_PWRSEQ_OFF                        (1 << 4)
-#define   PWRDN_WAIT_PPLL_OFF                          (1 << 8)
-#define   PWRUP_WAIT_PPLL_ON                           (1 << 12)
-#define   PWRUP_WAIT_MEM_INIT_DONE                     (1 << 16)
-#define   PM_ASSERT_RESET                              (1 << 20)
-#define   PM_PWRDN_PPLL                                (1 << 24)
-
-#endif
diff --git a/hw/display/rs690d.h b/hw/display/rs690d.h
deleted file mode 100644
index 8af3ccf20c..0000000000
--- a/hw/display/rs690d.h
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RS690D_H__
-#define __RS690D_H__
-
-/* Registers */
-#define R_00001E_K8_FB_LOCATION                      0x00001E
-#define R_00005F_MC_MISC_UMA_CNTL                    0x00005F
-#define   G_00005F_K8_ADDR_EXT(x)                      (((x) >> 0) & 0xFF)
-#define R_000078_MC_INDEX                            0x000078
-#define   S_000078_MC_IND_ADDR(x)                      (((x) & 0x1FF) << 0)
-#define   G_000078_MC_IND_ADDR(x)                      (((x) >> 0) & 0x1FF)
-#define   C_000078_MC_IND_ADDR                         0xFFFFFE00
-#define   S_000078_MC_IND_WR_EN(x)                     (((x) & 0x1) << 9)
-#define   G_000078_MC_IND_WR_EN(x)                     (((x) >> 9) & 0x1)
-#define   C_000078_MC_IND_WR_EN                        0xFFFFFDFF
-#define R_00007C_MC_DATA                             0x00007C
-#define   S_00007C_MC_DATA(x)                          (((x) & 0xFFFFFFFF) << 0)
-#define   G_00007C_MC_DATA(x)                          (((x) >> 0) & 0xFFFFFFFF)
-#define   C_00007C_MC_DATA                             0x00000000
-#define R_0000F8_CONFIG_MEMSIZE                      0x0000F8
-#define   S_0000F8_CONFIG_MEMSIZE(x)                   (((x) & 0xFFFFFFFF) << 0)
-#define   G_0000F8_CONFIG_MEMSIZE(x)                   (((x) >> 0) & 0xFFFFFFFF)
-#define   C_0000F8_CONFIG_MEMSIZE                      0x00000000
-#define R_000134_HDP_FB_LOCATION                     0x000134
-#define   S_000134_HDP_FB_START(x)                     (((x) & 0xFFFF) << 0)
-#define   G_000134_HDP_FB_START(x)                     (((x) >> 0) & 0xFFFF)
-#define   C_000134_HDP_FB_START                        0xFFFF0000
-#define R_0007C0_CP_STAT                             0x0007C0
-#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
-#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
-#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
-#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
-#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
-#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
-#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
-#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
-#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
-#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
-#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
-#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
-#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
-#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
-#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
-#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
-#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
-#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
-#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
-#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
-#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
-#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
-#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
-#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
-#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
-#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
-#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
-#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
-#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
-#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
-#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
-#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
-#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
-#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
-#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
-#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
-#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
-#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
-#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
-#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
-#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
-#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
-#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
-#define R_000E40_RBBM_STATUS                         0x000E40
-#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
-#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
-#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
-#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
-#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
-#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
-#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
-#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
-#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
-#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
-#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
-#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
-#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
-#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
-#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
-#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
-#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
-#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
-#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
-#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
-#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
-#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
-#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
-#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
-#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
-#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
-#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
-#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
-#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
-#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
-#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
-#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
-#define   C_000E40_E2_BUSY                             0xFFFDFFFF
-#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
-#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
-#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
-#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
-#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
-#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
-#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
-#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
-#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
-#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
-#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
-#define   C_000E40_RE_BUSY                             0xFFDFFFFF
-#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
-#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
-#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
-#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
-#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
-#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
-#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
-#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
-#define   C_000E40_PB_BUSY                             0xFEFFFFFF
-#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
-#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
-#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
-#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
-#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
-#define   C_000E40_GA_BUSY                             0xFBFFFFFF
-#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
-#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
-#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
-#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
-#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
-#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
-#define R_006520_DC_LB_MEMORY_SPLIT                  0x006520
-#define   S_006520_DC_LB_MEMORY_SPLIT(x)               (((x) & 0x3) << 0)
-#define   G_006520_DC_LB_MEMORY_SPLIT(x)               (((x) >> 0) & 0x3)
-#define   C_006520_DC_LB_MEMORY_SPLIT                  0xFFFFFFFC
-#define   S_006520_DC_LB_MEMORY_SPLIT_MODE(x)          (((x) & 0x1) << 2)
-#define   G_006520_DC_LB_MEMORY_SPLIT_MODE(x)          (((x) >> 2) & 0x1)
-#define   C_006520_DC_LB_MEMORY_SPLIT_MODE             0xFFFFFFFB
-#define   V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF    0
-#define   V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q      1
-#define   V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY          2
-#define   V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q      3
-#define   S_006520_DC_LB_DISP1_END_ADR(x)              (((x) & 0x7FF) << 4)
-#define   G_006520_DC_LB_DISP1_END_ADR(x)              (((x) >> 4) & 0x7FF)
-#define   C_006520_DC_LB_DISP1_END_ADR                 0xFFFF800F
-#define R_006548_D1MODE_PRIORITY_A_CNT               0x006548
-#define   S_006548_D1MODE_PRIORITY_MARK_A(x)           (((x) & 0x7FFF) << 0)
-#define   G_006548_D1MODE_PRIORITY_MARK_A(x)           (((x) >> 0) & 0x7FFF)
-#define   C_006548_D1MODE_PRIORITY_MARK_A              0xFFFF8000
-#define   S_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) & 0x1) << 16)
-#define   G_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) >> 16) & 0x1)
-#define   C_006548_D1MODE_PRIORITY_A_OFF               0xFFFEFFFF
-#define   S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) & 0x1) << 20)
-#define   G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
-#define   C_006548_D1MODE_PRIORITY_A_ALWAYS_ON         0xFFEFFFFF
-#define   S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) & 0x1) << 24)
-#define   G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) >> 24) & 0x1)
-#define   C_006548_D1MODE_PRIORITY_A_FORCE_MASK        0xFEFFFFFF
-#define R_00654C_D1MODE_PRIORITY_B_CNT               0x00654C
-#define   S_00654C_D1MODE_PRIORITY_MARK_B(x)           (((x) & 0x7FFF) << 0)
-#define   G_00654C_D1MODE_PRIORITY_MARK_B(x)           (((x) >> 0) & 0x7FFF)
-#define   C_00654C_D1MODE_PRIORITY_MARK_B              0xFFFF8000
-#define   S_00654C_D1MODE_PRIORITY_B_OFF(x)            (((x) & 0x1) << 16)
-#define   G_00654C_D1MODE_PRIORITY_B_OFF(x)            (((x) >> 16) & 0x1)
-#define   C_00654C_D1MODE_PRIORITY_B_OFF               0xFFFEFFFF
-#define   S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) & 0x1) << 20)
-#define   G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
-#define   C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON         0xFFEFFFFF
-#define   S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)     (((x) & 0x1) << 24)
-#define   G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)     (((x) >> 24) & 0x1)
-#define   C_00654C_D1MODE_PRIORITY_B_FORCE_MASK        0xFEFFFFFF
-#define R_006C9C_DCP_CONTROL                         0x006C9C
-#define R_006D48_D2MODE_PRIORITY_A_CNT               0x006D48
-#define   S_006D48_D2MODE_PRIORITY_MARK_A(x)           (((x) & 0x7FFF) << 0)
-#define   G_006D48_D2MODE_PRIORITY_MARK_A(x)           (((x) >> 0) & 0x7FFF)
-#define   C_006D48_D2MODE_PRIORITY_MARK_A              0xFFFF8000
-#define   S_006D48_D2MODE_PRIORITY_A_OFF(x)            (((x) & 0x1) << 16)
-#define   G_006D48_D2MODE_PRIORITY_A_OFF(x)            (((x) >> 16) & 0x1)
-#define   C_006D48_D2MODE_PRIORITY_A_OFF               0xFFFEFFFF
-#define   S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) & 0x1) << 20)
-#define   G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
-#define   C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON         0xFFEFFFFF
-#define   S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)     (((x) & 0x1) << 24)
-#define   G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)     (((x) >> 24) & 0x1)
-#define   C_006D48_D2MODE_PRIORITY_A_FORCE_MASK        0xFEFFFFFF
-#define R_006D4C_D2MODE_PRIORITY_B_CNT               0x006D4C
-#define   S_006D4C_D2MODE_PRIORITY_MARK_B(x)           (((x) & 0x7FFF) << 0)
-#define   G_006D4C_D2MODE_PRIORITY_MARK_B(x)           (((x) >> 0) & 0x7FFF)
-#define   C_006D4C_D2MODE_PRIORITY_MARK_B              0xFFFF8000
-#define   S_006D4C_D2MODE_PRIORITY_B_OFF(x)            (((x) & 0x1) << 16)
-#define   G_006D4C_D2MODE_PRIORITY_B_OFF(x)            (((x) >> 16) & 0x1)
-#define   C_006D4C_D2MODE_PRIORITY_B_OFF               0xFFFEFFFF
-#define   S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) & 0x1) << 20)
-#define   G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
-#define   C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON         0xFFEFFFFF
-#define   S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)     (((x) & 0x1) << 24)
-#define   G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)     (((x) >> 24) & 0x1)
-#define   C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK        0xFEFFFFFF
-#define R_006D58_LB_MAX_REQ_OUTSTANDING              0x006D58
-#define   S_006D58_LB_D1_MAX_REQ_OUTSTANDING(x)        (((x) & 0xF) << 0)
-#define   G_006D58_LB_D1_MAX_REQ_OUTSTANDING(x)        (((x) >> 0) & 0xF)
-#define   C_006D58_LB_D1_MAX_REQ_OUTSTANDING           0xFFFFFFF0
-#define   S_006D58_LB_D2_MAX_REQ_OUTSTANDING(x)        (((x) & 0xF) << 16)
-#define   G_006D58_LB_D2_MAX_REQ_OUTSTANDING(x)        (((x) >> 16) & 0xF)
-#define   C_006D58_LB_D2_MAX_REQ_OUTSTANDING           0xFFF0FFFF
-
-
-#define R_000090_MC_SYSTEM_STATUS                    0x000090
-#define   S_000090_MC_SYSTEM_IDLE(x)                   (((x) & 0x1) << 0)
-#define   G_000090_MC_SYSTEM_IDLE(x)                   (((x) >> 0) & 0x1)
-#define   C_000090_MC_SYSTEM_IDLE                      0xFFFFFFFE
-#define   S_000090_MC_SEQUENCER_IDLE(x)                (((x) & 0x1) << 1)
-#define   G_000090_MC_SEQUENCER_IDLE(x)                (((x) >> 1) & 0x1)
-#define   C_000090_MC_SEQUENCER_IDLE                   0xFFFFFFFD
-#define   S_000090_MC_ARBITER_IDLE(x)                  (((x) & 0x1) << 2)
-#define   G_000090_MC_ARBITER_IDLE(x)                  (((x) >> 2) & 0x1)
-#define   C_000090_MC_ARBITER_IDLE                     0xFFFFFFFB
-#define   S_000090_MC_SELECT_PM(x)                     (((x) & 0x1) << 3)
-#define   G_000090_MC_SELECT_PM(x)                     (((x) >> 3) & 0x1)
-#define   C_000090_MC_SELECT_PM                        0xFFFFFFF7
-#define   S_000090_RESERVED4(x)                        (((x) & 0xF) << 4)
-#define   G_000090_RESERVED4(x)                        (((x) >> 4) & 0xF)
-#define   C_000090_RESERVED4                           0xFFFFFF0F
-#define   S_000090_RESERVED8(x)                        (((x) & 0xF) << 8)
-#define   G_000090_RESERVED8(x)                        (((x) >> 8) & 0xF)
-#define   C_000090_RESERVED8                           0xFFFFF0FF
-#define   S_000090_RESERVED12(x)                       (((x) & 0xF) << 12)
-#define   G_000090_RESERVED12(x)                       (((x) >> 12) & 0xF)
-#define   C_000090_RESERVED12                          0xFFFF0FFF
-#define   S_000090_MCA_INIT_EXECUTED(x)                (((x) & 0x1) << 16)
-#define   G_000090_MCA_INIT_EXECUTED(x)                (((x) >> 16) & 0x1)
-#define   C_000090_MCA_INIT_EXECUTED                   0xFFFEFFFF
-#define   S_000090_MCA_IDLE(x)                         (((x) & 0x1) << 17)
-#define   G_000090_MCA_IDLE(x)                         (((x) >> 17) & 0x1)
-#define   C_000090_MCA_IDLE                            0xFFFDFFFF
-#define   S_000090_MCA_SEQ_IDLE(x)                     (((x) & 0x1) << 18)
-#define   G_000090_MCA_SEQ_IDLE(x)                     (((x) >> 18) & 0x1)
-#define   C_000090_MCA_SEQ_IDLE                        0xFFFBFFFF
-#define   S_000090_MCA_ARB_IDLE(x)                     (((x) & 0x1) << 19)
-#define   G_000090_MCA_ARB_IDLE(x)                     (((x) >> 19) & 0x1)
-#define   C_000090_MCA_ARB_IDLE                        0xFFF7FFFF
-#define   S_000090_RESERVED20(x)                       (((x) & 0xFFF) << 20)
-#define   G_000090_RESERVED20(x)                       (((x) >> 20) & 0xFFF)
-#define   C_000090_RESERVED20                          0x000FFFFF
-#define R_000100_MCCFG_FB_LOCATION                   0x000100
-#define   S_000100_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
-#define   G_000100_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
-#define   C_000100_MC_FB_START                         0xFFFF0000
-#define   S_000100_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
-#define   G_000100_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
-#define   C_000100_MC_FB_TOP                           0x0000FFFF
-#define R_000104_MC_INIT_MISC_LAT_TIMER              0x000104
-#define   S_000104_MC_CPR_INIT_LAT(x)                  (((x) & 0xF) << 0)
-#define   G_000104_MC_CPR_INIT_LAT(x)                  (((x) >> 0) & 0xF)
-#define   C_000104_MC_CPR_INIT_LAT                     0xFFFFFFF0
-#define   S_000104_MC_VF_INIT_LAT(x)                   (((x) & 0xF) << 4)
-#define   G_000104_MC_VF_INIT_LAT(x)                   (((x) >> 4) & 0xF)
-#define   C_000104_MC_VF_INIT_LAT                      0xFFFFFF0F
-#define   S_000104_MC_DISP0R_INIT_LAT(x)               (((x) & 0xF) << 8)
-#define   G_000104_MC_DISP0R_INIT_LAT(x)               (((x) >> 8) & 0xF)
-#define   C_000104_MC_DISP0R_INIT_LAT                  0xFFFFF0FF
-#define   S_000104_MC_DISP1R_INIT_LAT(x)               (((x) & 0xF) << 12)
-#define   G_000104_MC_DISP1R_INIT_LAT(x)               (((x) >> 12) & 0xF)
-#define   C_000104_MC_DISP1R_INIT_LAT                  0xFFFF0FFF
-#define   S_000104_MC_FIXED_INIT_LAT(x)                (((x) & 0xF) << 16)
-#define   G_000104_MC_FIXED_INIT_LAT(x)                (((x) >> 16) & 0xF)
-#define   C_000104_MC_FIXED_INIT_LAT                   0xFFF0FFFF
-#define   S_000104_MC_E2R_INIT_LAT(x)                  (((x) & 0xF) << 20)
-#define   G_000104_MC_E2R_INIT_LAT(x)                  (((x) >> 20) & 0xF)
-#define   C_000104_MC_E2R_INIT_LAT                     0xFF0FFFFF
-#define   S_000104_SAME_PAGE_PRIO(x)                   (((x) & 0xF) << 24)
-#define   G_000104_SAME_PAGE_PRIO(x)                   (((x) >> 24) & 0xF)
-#define   C_000104_SAME_PAGE_PRIO                      0xF0FFFFFF
-#define   S_000104_MC_GLOBW_INIT_LAT(x)                (((x) & 0xF) << 28)
-#define   G_000104_MC_GLOBW_INIT_LAT(x)                (((x) >> 28) & 0xF)
-#define   C_000104_MC_GLOBW_INIT_LAT                   0x0FFFFFFF
-
-#endif
diff --git a/hw/display/rs780_dpm.h b/hw/display/rs780_dpm.h
deleted file mode 100644
index 47a40b14fa..0000000000
--- a/hw/display/rs780_dpm.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __RS780_DPM_H__
-#define __RS780_DPM_H__
-
-enum rs780_vddc_level {
-	RS780_VDDC_LEVEL_UNKNOWN = 0,
-	RS780_VDDC_LEVEL_LOW = 1,
-	RS780_VDDC_LEVEL_HIGH = 2,
-};
-
-struct igp_power_info {
-	/* flags */
-	bool invert_pwm_required;
-	bool pwm_voltage_control;
-	bool voltage_control;
-	bool gfx_clock_gating;
-	/* stored values */
-	u32 system_config;
-	u32 bootup_uma_clk;
-	u16 max_voltage;
-	u16 min_voltage;
-	u16 boot_voltage;
-	u16 inter_voltage_low;
-	u16 inter_voltage_high;
-	u16 num_of_cycles_in_period;
-	/* variable */
-	int crtc_id;
-	int refresh_rate;
-};
-
-struct igp_ps {
-	enum rs780_vddc_level min_voltage;
-	enum rs780_vddc_level max_voltage;
-	u32 sclk_low;
-	u32 sclk_high;
-	u32 flags;
-};
-
-#define RS780_CGFTV_DFLT                 0x0303000f
-#define RS780_FBDIVTIMERVAL_DFLT         0x2710
-
-#define RS780_FVTHROTUTC0_DFLT   0x04010040
-#define RS780_FVTHROTUTC1_DFLT   0x04010040
-#define RS780_FVTHROTUTC2_DFLT   0x04010040
-#define RS780_FVTHROTUTC3_DFLT   0x04010040
-#define RS780_FVTHROTUTC4_DFLT   0x04010040
-
-#define RS780_FVTHROTDTC0_DFLT 0x04010040
-#define RS780_FVTHROTDTC1_DFLT 0x04010040
-#define RS780_FVTHROTDTC2_DFLT 0x04010040
-#define RS780_FVTHROTDTC3_DFLT 0x04010040
-#define RS780_FVTHROTDTC4_DFLT 0x04010040
-
-#define RS780_FVTHROTFBUSREG0_DFLT       0x00001001
-#define RS780_FVTHROTFBUSREG1_DFLT       0x00002002
-#define RS780_FVTHROTFBDSREG0_DFLT       0x00004001
-#define RS780_FVTHROTFBDSREG1_DFLT       0x00020010
-
-#define RS780_FVTHROTPWMUSREG0_DFLT      0x00002001
-#define RS780_FVTHROTPWMUSREG1_DFLT      0x00004003
-#define RS780_FVTHROTPWMDSREG0_DFLT      0x00002001
-#define RS780_FVTHROTPWMDSREG1_DFLT      0x00004003
-
-#define RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT  0x37
-#define RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT  0x4b
-#define RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT  0x8b
-
-#define RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT  0x8b
-#define RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT  0x8c
-#define RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT  0xb5
-
-#define RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT  0x8d
-#define RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT  0x8e
-#define RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT  0xBa
-
-#define RS780_FVTHROTPWMRANGE0_GPIO_DFLT  0x1a
-#define RS780_FVTHROTPWMRANGE1_GPIO_DFLT  0x1a
-#define RS780_FVTHROTPWMRANGE2_GPIO_DFLT  0x0
-#define RS780_FVTHROTPWMRANGE3_GPIO_DFLT  0x0
-
-#define RS780_SLOWCLKFEEDBACKDIV_DFLT 110
-
-#define RS780_CGCLKGATING_DFLT           0x0000E204
-
-#define RS780_DEFAULT_VCLK_FREQ  53300 /* 10 khz */
-#define RS780_DEFAULT_DCLK_FREQ  40000 /* 10 khz */
-
-#endif
diff --git a/hw/display/rs780d.h b/hw/display/rs780d.h
deleted file mode 100644
index cfbe9a43d9..0000000000
--- a/hw/display/rs780d.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __RS780D_H__
-#define __RS780D_H__
-
-#define CG_SPLL_FUNC_CNTL                                 0x600
-#       define SPLL_RESET                                (1 << 0)
-#       define SPLL_SLEEP                                (1 << 1)
-#       define SPLL_REF_DIV(x)                           ((x) << 2)
-#       define SPLL_REF_DIV_MASK                         (7 << 2)
-#       define SPLL_REF_DIV_SHIFT                        2
-#       define SPLL_FB_DIV(x)                            ((x) << 5)
-#       define SPLL_FB_DIV_MASK                          (0xff << 2)
-#       define SPLL_FB_DIV_SHIFT                         2
-#       define SPLL_PULSEEN                              (1 << 13)
-#       define SPLL_PULSENUM(x)                          ((x) << 14)
-#       define SPLL_PULSENUM_MASK                        (3 << 14)
-#       define SPLL_SW_HILEN(x)                          ((x) << 16)
-#       define SPLL_SW_HILEN_MASK                        (0xf << 16)
-#       define SPLL_SW_HILEN_SHIFT                       16
-#       define SPLL_SW_LOLEN(x)                          ((x) << 20)
-#       define SPLL_SW_LOLEN_MASK                        (0xf << 20)
-#       define SPLL_SW_LOLEN_SHIFT                       20
-#       define SPLL_DIVEN                                (1 << 24)
-#       define SPLL_BYPASS_EN                            (1 << 25)
-#       define SPLL_CHG_STATUS                           (1 << 29)
-#       define SPLL_CTLREQ                               (1 << 30)
-#       define SPLL_CTLACK                               (1 << 31)
-
-/* RS780/RS880 PM */
-#define	FVTHROT_CNTRL_REG				0x3000
-#define		DONT_WAIT_FOR_FBDIV_WRAP		(1 << 0)
-#define		MINIMUM_CIP(x)				((x) << 1)
-#define		MINIMUM_CIP_SHIFT			1
-#define		MINIMUM_CIP_MASK			0x1fffffe
-#define		REFRESH_RATE_DIVISOR(x)			((x) << 25)
-#define		REFRESH_RATE_DIVISOR_SHIFT		25
-#define		REFRESH_RATE_DIVISOR_MASK		(0x3 << 25)
-#define		ENABLE_FV_THROT				(1 << 27)
-#define		ENABLE_FV_UPDATE			(1 << 28)
-#define		TREND_SEL_MODE				(1 << 29)
-#define		FORCE_TREND_SEL				(1 << 30)
-#define		ENABLE_FV_THROT_IO			(1 << 31)
-#define	FVTHROT_TARGET_REG				0x3004
-#define		TARGET_IDLE_COUNT(x)			((x) << 0)
-#define		TARGET_IDLE_COUNT_MASK			0xffffff
-#define		TARGET_IDLE_COUNT_SHIFT			0
-#define	FVTHROT_CB1					0x3008
-#define	FVTHROT_CB2					0x300c
-#define	FVTHROT_CB3					0x3010
-#define	FVTHROT_CB4					0x3014
-#define	FVTHROT_UTC0					0x3018
-#define	FVTHROT_UTC1					0x301c
-#define	FVTHROT_UTC2					0x3020
-#define	FVTHROT_UTC3					0x3024
-#define	FVTHROT_UTC4					0x3028
-#define	FVTHROT_DTC0					0x302c
-#define	FVTHROT_DTC1					0x3030
-#define	FVTHROT_DTC2					0x3034
-#define	FVTHROT_DTC3					0x3038
-#define	FVTHROT_DTC4					0x303c
-#define	FVTHROT_FBDIV_REG0				0x3040
-#define		MIN_FEEDBACK_DIV(x)			((x) << 0)
-#define		MIN_FEEDBACK_DIV_MASK			0xfff
-#define		MIN_FEEDBACK_DIV_SHIFT			0
-#define		MAX_FEEDBACK_DIV(x)			((x) << 12)
-#define		MAX_FEEDBACK_DIV_MASK			(0xfff << 12)
-#define		MAX_FEEDBACK_DIV_SHIFT			12
-#define	FVTHROT_FBDIV_REG1				0x3044
-#define		MAX_FEEDBACK_STEP(x)			((x) << 0)
-#define		MAX_FEEDBACK_STEP_MASK			0xfff
-#define		MAX_FEEDBACK_STEP_SHIFT			0
-#define		STARTING_FEEDBACK_DIV(x)		((x) << 12)
-#define		STARTING_FEEDBACK_DIV_MASK		(0xfff << 12)
-#define		STARTING_FEEDBACK_DIV_SHIFT		12
-#define		FORCE_FEEDBACK_DIV			(1 << 24)
-#define	FVTHROT_FBDIV_REG2				0x3048
-#define		FORCED_FEEDBACK_DIV(x)			((x) << 0)
-#define		FORCED_FEEDBACK_DIV_MASK		0xfff
-#define		FORCED_FEEDBACK_DIV_SHIFT		0
-#define		FB_DIV_TIMER_VAL(x)			((x) << 12)
-#define		FB_DIV_TIMER_VAL_MASK			(0xffff << 12)
-#define		FB_DIV_TIMER_VAL_SHIFT			12
-#define	FVTHROT_FB_US_REG0				0x304c
-#define	FVTHROT_FB_US_REG1				0x3050
-#define	FVTHROT_FB_DS_REG0				0x3054
-#define	FVTHROT_FB_DS_REG1				0x3058
-#define	FVTHROT_PWM_CTRL_REG0				0x305c
-#define		STARTING_PWM_HIGHTIME(x)		((x) << 0)
-#define		STARTING_PWM_HIGHTIME_MASK		0xfff
-#define		STARTING_PWM_HIGHTIME_SHIFT		0
-#define		NUMBER_OF_CYCLES_IN_PERIOD(x)		((x) << 12)
-#define		NUMBER_OF_CYCLES_IN_PERIOD_MASK		(0xfff << 12)
-#define		NUMBER_OF_CYCLES_IN_PERIOD_SHIFT	12
-#define		FORCE_STARTING_PWM_HIGHTIME		(1 << 24)
-#define		INVERT_PWM_WAVEFORM			(1 << 25)
-#define	FVTHROT_PWM_CTRL_REG1				0x3060
-#define		MIN_PWM_HIGHTIME(x)			((x) << 0)
-#define		MIN_PWM_HIGHTIME_MASK			0xfff
-#define		MIN_PWM_HIGHTIME_SHIFT			0
-#define		MAX_PWM_HIGHTIME(x)			((x) << 12)
-#define		MAX_PWM_HIGHTIME_MASK			(0xfff << 12)
-#define		MAX_PWM_HIGHTIME_SHIFT			12
-#define	FVTHROT_PWM_US_REG0				0x3064
-#define	FVTHROT_PWM_US_REG1				0x3068
-#define	FVTHROT_PWM_DS_REG0				0x306c
-#define	FVTHROT_PWM_DS_REG1				0x3070
-#define	FVTHROT_STATUS_REG0				0x3074
-#define		CURRENT_FEEDBACK_DIV_MASK		0xfff
-#define		CURRENT_FEEDBACK_DIV_SHIFT		0
-#define	FVTHROT_STATUS_REG1				0x3078
-#define	FVTHROT_STATUS_REG2				0x307c
-#define	CG_INTGFX_MISC					0x3080
-#define		FVTHROT_VBLANK_SEL			(1 << 9)
-#define	FVTHROT_PWM_FEEDBACK_DIV_REG1			0x308c
-#define		RANGE0_PWM_FEEDBACK_DIV(x)		((x) << 0)
-#define		RANGE0_PWM_FEEDBACK_DIV_MASK		0xfff
-#define		RANGE0_PWM_FEEDBACK_DIV_SHIFT		0
-#define		RANGE_PWM_FEEDBACK_DIV_EN		(1 << 12)
-#define	FVTHROT_PWM_FEEDBACK_DIV_REG2			0x3090
-#define		RANGE1_PWM_FEEDBACK_DIV(x)		((x) << 0)
-#define		RANGE1_PWM_FEEDBACK_DIV_MASK		0xfff
-#define		RANGE1_PWM_FEEDBACK_DIV_SHIFT		0
-#define		RANGE2_PWM_FEEDBACK_DIV(x)		((x) << 12)
-#define		RANGE2_PWM_FEEDBACK_DIV_MASK		(0xfff << 12)
-#define		RANGE2_PWM_FEEDBACK_DIV_SHIFT		12
-#define	FVTHROT_PWM_FEEDBACK_DIV_REG3			0x3094
-#define		RANGE0_PWM(x)				((x) << 0)
-#define		RANGE0_PWM_MASK				0xfff
-#define		RANGE0_PWM_SHIFT			0
-#define		RANGE1_PWM(x)				((x) << 12)
-#define		RANGE1_PWM_MASK				(0xfff << 12)
-#define		RANGE1_PWM_SHIFT			12
-#define	FVTHROT_PWM_FEEDBACK_DIV_REG4			0x3098
-#define		RANGE2_PWM(x)				((x) << 0)
-#define		RANGE2_PWM_MASK				0xfff
-#define		RANGE2_PWM_SHIFT			0
-#define		RANGE3_PWM(x)				((x) << 12)
-#define		RANGE3_PWM_MASK				(0xfff << 12)
-#define		RANGE3_PWM_SHIFT			12
-#define	FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1		0x30ac
-#define		RANGE0_SLOW_CLK_FEEDBACK_DIV(x)		((x) << 0)
-#define		RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK	0xfff
-#define		RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT	0
-#define		RANGE_SLOW_CLK_FEEDBACK_DIV_EN		(1 << 12)
-
-#define	GFX_MACRO_BYPASS_CNTL				0x30c0
-#define		SPLL_BYPASS_CNTL			(1 << 0)
-#define		UPLL_BYPASS_CNTL			(1 << 1)
-
-#endif
diff --git a/hw/display/rv200d.h b/hw/display/rv200d.h
deleted file mode 100644
index c5b398330c..0000000000
--- a/hw/display/rv200d.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RV200D_H__
-#define __RV200D_H__
-
-#define R_00015C_AGP_BASE_2                          0x00015C
-#define   S_00015C_AGP_BASE_ADDR_2(x)                  (((x) & 0xF) << 0)
-#define   G_00015C_AGP_BASE_ADDR_2(x)                  (((x) >> 0) & 0xF)
-#define   C_00015C_AGP_BASE_ADDR_2                     0xFFFFFFF0
-
-#endif
diff --git a/hw/display/rv250d.h b/hw/display/rv250d.h
deleted file mode 100644
index e5a70b06fe..0000000000
--- a/hw/display/rv250d.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RV250D_H__
-#define __RV250D_H__
-
-#define R_00000D_SCLK_CNTL_M6                        0x00000D
-#define   S_00000D_SCLK_SRC_SEL(x)                     (((x) & 0x7) << 0)
-#define   G_00000D_SCLK_SRC_SEL(x)                     (((x) >> 0) & 0x7)
-#define   C_00000D_SCLK_SRC_SEL                        0xFFFFFFF8
-#define   S_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 3)
-#define   G_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) >> 3) & 0x1)
-#define   C_00000D_CP_MAX_DYN_STOP_LAT                 0xFFFFFFF7
-#define   S_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 4)
-#define   G_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) >> 4) & 0x1)
-#define   C_00000D_HDP_MAX_DYN_STOP_LAT                0xFFFFFFEF
-#define   S_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 5)
-#define   G_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) >> 5) & 0x1)
-#define   C_00000D_TV_MAX_DYN_STOP_LAT                 0xFFFFFFDF
-#define   S_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 6)
-#define   G_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) >> 6) & 0x1)
-#define   C_00000D_E2_MAX_DYN_STOP_LAT                 0xFFFFFFBF
-#define   S_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 7)
-#define   G_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) >> 7) & 0x1)
-#define   C_00000D_SE_MAX_DYN_STOP_LAT                 0xFFFFFF7F
-#define   S_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) & 0x1) << 8)
-#define   G_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) >> 8) & 0x1)
-#define   C_00000D_IDCT_MAX_DYN_STOP_LAT               0xFFFFFEFF
-#define   S_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 9)
-#define   G_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) >> 9) & 0x1)
-#define   C_00000D_VIP_MAX_DYN_STOP_LAT                0xFFFFFDFF
-#define   S_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 10)
-#define   G_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) >> 10) & 0x1)
-#define   C_00000D_RE_MAX_DYN_STOP_LAT                 0xFFFFFBFF
-#define   S_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 11)
-#define   G_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) >> 11) & 0x1)
-#define   C_00000D_PB_MAX_DYN_STOP_LAT                 0xFFFFF7FF
-#define   S_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 12)
-#define   G_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) >> 12) & 0x1)
-#define   C_00000D_TAM_MAX_DYN_STOP_LAT                0xFFFFEFFF
-#define   S_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 13)
-#define   G_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) >> 13) & 0x1)
-#define   C_00000D_TDM_MAX_DYN_STOP_LAT                0xFFFFDFFF
-#define   S_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 14)
-#define   G_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) >> 14) & 0x1)
-#define   C_00000D_RB_MAX_DYN_STOP_LAT                 0xFFFFBFFF
-#define   S_00000D_FORCE_DISP2(x)                      (((x) & 0x1) << 15)
-#define   G_00000D_FORCE_DISP2(x)                      (((x) >> 15) & 0x1)
-#define   C_00000D_FORCE_DISP2                         0xFFFF7FFF
-#define   S_00000D_FORCE_CP(x)                         (((x) & 0x1) << 16)
-#define   G_00000D_FORCE_CP(x)                         (((x) >> 16) & 0x1)
-#define   C_00000D_FORCE_CP                            0xFFFEFFFF
-#define   S_00000D_FORCE_HDP(x)                        (((x) & 0x1) << 17)
-#define   G_00000D_FORCE_HDP(x)                        (((x) >> 17) & 0x1)
-#define   C_00000D_FORCE_HDP                           0xFFFDFFFF
-#define   S_00000D_FORCE_DISP1(x)                      (((x) & 0x1) << 18)
-#define   G_00000D_FORCE_DISP1(x)                      (((x) >> 18) & 0x1)
-#define   C_00000D_FORCE_DISP1                         0xFFFBFFFF
-#define   S_00000D_FORCE_TOP(x)                        (((x) & 0x1) << 19)
-#define   G_00000D_FORCE_TOP(x)                        (((x) >> 19) & 0x1)
-#define   C_00000D_FORCE_TOP                           0xFFF7FFFF
-#define   S_00000D_FORCE_E2(x)                         (((x) & 0x1) << 20)
-#define   G_00000D_FORCE_E2(x)                         (((x) >> 20) & 0x1)
-#define   C_00000D_FORCE_E2                            0xFFEFFFFF
-#define   S_00000D_FORCE_SE(x)                         (((x) & 0x1) << 21)
-#define   G_00000D_FORCE_SE(x)                         (((x) >> 21) & 0x1)
-#define   C_00000D_FORCE_SE                            0xFFDFFFFF
-#define   S_00000D_FORCE_IDCT(x)                       (((x) & 0x1) << 22)
-#define   G_00000D_FORCE_IDCT(x)                       (((x) >> 22) & 0x1)
-#define   C_00000D_FORCE_IDCT                          0xFFBFFFFF
-#define   S_00000D_FORCE_VIP(x)                        (((x) & 0x1) << 23)
-#define   G_00000D_FORCE_VIP(x)                        (((x) >> 23) & 0x1)
-#define   C_00000D_FORCE_VIP                           0xFF7FFFFF
-#define   S_00000D_FORCE_RE(x)                         (((x) & 0x1) << 24)
-#define   G_00000D_FORCE_RE(x)                         (((x) >> 24) & 0x1)
-#define   C_00000D_FORCE_RE                            0xFEFFFFFF
-#define   S_00000D_FORCE_PB(x)                         (((x) & 0x1) << 25)
-#define   G_00000D_FORCE_PB(x)                         (((x) >> 25) & 0x1)
-#define   C_00000D_FORCE_PB                            0xFDFFFFFF
-#define   S_00000D_FORCE_TAM(x)                        (((x) & 0x1) << 26)
-#define   G_00000D_FORCE_TAM(x)                        (((x) >> 26) & 0x1)
-#define   C_00000D_FORCE_TAM                           0xFBFFFFFF
-#define   S_00000D_FORCE_TDM(x)                        (((x) & 0x1) << 27)
-#define   G_00000D_FORCE_TDM(x)                        (((x) >> 27) & 0x1)
-#define   C_00000D_FORCE_TDM                           0xF7FFFFFF
-#define   S_00000D_FORCE_RB(x)                         (((x) & 0x1) << 28)
-#define   G_00000D_FORCE_RB(x)                         (((x) >> 28) & 0x1)
-#define   C_00000D_FORCE_RB                            0xEFFFFFFF
-#define   S_00000D_FORCE_TV_SCLK(x)                    (((x) & 0x1) << 29)
-#define   G_00000D_FORCE_TV_SCLK(x)                    (((x) >> 29) & 0x1)
-#define   C_00000D_FORCE_TV_SCLK                       0xDFFFFFFF
-#define   S_00000D_FORCE_SUBPIC(x)                     (((x) & 0x1) << 30)
-#define   G_00000D_FORCE_SUBPIC(x)                     (((x) >> 30) & 0x1)
-#define   C_00000D_FORCE_SUBPIC                        0xBFFFFFFF
-#define   S_00000D_FORCE_OV0(x)                        (((x) & 0x1) << 31)
-#define   G_00000D_FORCE_OV0(x)                        (((x) >> 31) & 0x1)
-#define   C_00000D_FORCE_OV0                           0x7FFFFFFF
-
-#endif
diff --git a/hw/display/rv350d.h b/hw/display/rv350d.h
deleted file mode 100644
index c75c5ed9e6..0000000000
--- a/hw/display/rv350d.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RV350D_H__
-#define __RV350D_H__
-
-/* RV350, RV380 registers */
-/* #define R_00000D_SCLK_CNTL                           0x00000D */
-#define   S_00000D_FORCE_VAP(x)                        (((x) & 0x1) << 21)
-#define   G_00000D_FORCE_VAP(x)                        (((x) >> 21) & 0x1)
-#define   C_00000D_FORCE_VAP                           0xFFDFFFFF
-#define   S_00000D_FORCE_SR(x)                         (((x) & 0x1) << 25)
-#define   G_00000D_FORCE_SR(x)                         (((x) >> 25) & 0x1)
-#define   C_00000D_FORCE_SR                            0xFDFFFFFF
-#define   S_00000D_FORCE_PX(x)                         (((x) & 0x1) << 26)
-#define   G_00000D_FORCE_PX(x)                         (((x) >> 26) & 0x1)
-#define   C_00000D_FORCE_PX                            0xFBFFFFFF
-#define   S_00000D_FORCE_TX(x)                         (((x) & 0x1) << 27)
-#define   G_00000D_FORCE_TX(x)                         (((x) >> 27) & 0x1)
-#define   C_00000D_FORCE_TX                            0xF7FFFFFF
-#define   S_00000D_FORCE_US(x)                         (((x) & 0x1) << 28)
-#define   G_00000D_FORCE_US(x)                         (((x) >> 28) & 0x1)
-#define   C_00000D_FORCE_US                            0xEFFFFFFF
-#define   S_00000D_FORCE_SU(x)                         (((x) & 0x1) << 30)
-#define   G_00000D_FORCE_SU(x)                         (((x) >> 30) & 0x1)
-#define   C_00000D_FORCE_SU                            0xBFFFFFFF
-
-#endif
diff --git a/hw/display/rv515d.h b/hw/display/rv515d.h
deleted file mode 100644
index 6927a200da..0000000000
--- a/hw/display/rv515d.h
+++ /dev/null
@@ -1,638 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RV515D_H__
-#define __RV515D_H__
-
-/*
- * RV515 registers
- */
-#define PCIE_INDEX			0x0030
-#define PCIE_DATA			0x0034
-#define	MC_IND_INDEX			0x0070
-#define		MC_IND_WR_EN				(1 << 24)
-#define	MC_IND_DATA			0x0074
-#define	RBBM_SOFT_RESET			0x00F0
-#define	CONFIG_MEMSIZE			0x00F8
-#define HDP_FB_LOCATION			0x0134
-#define	CP_CSQ_CNTL			0x0740
-#define	CP_CSQ_MODE			0x0744
-#define	CP_CSQ_ADDR			0x07F0
-#define	CP_CSQ_DATA			0x07F4
-#define	CP_CSQ_STAT			0x07F8
-#define	CP_CSQ2_STAT			0x07FC
-#define	RBBM_STATUS			0x0E40
-#define	DST_PIPE_CONFIG			0x170C
-#define	WAIT_UNTIL			0x1720
-#define		WAIT_2D_IDLE				(1 << 14)
-#define		WAIT_3D_IDLE				(1 << 15)
-#define		WAIT_2D_IDLECLEAN			(1 << 16)
-#define		WAIT_3D_IDLECLEAN			(1 << 17)
-#define	ISYNC_CNTL			0x1724
-#define		ISYNC_ANY2D_IDLE3D			(1 << 0)
-#define		ISYNC_ANY3D_IDLE2D			(1 << 1)
-#define		ISYNC_TRIG2D_IDLE3D			(1 << 2)
-#define		ISYNC_TRIG3D_IDLE2D			(1 << 3)
-#define		ISYNC_WAIT_IDLEGUI			(1 << 4)
-#define		ISYNC_CPSCRATCH_IDLEGUI			(1 << 5)
-#define	VAP_INDEX_OFFSET		0x208C
-#define	VAP_PVS_STATE_FLUSH_REG		0x2284
-#define	GB_ENABLE			0x4008
-#define	GB_MSPOS0			0x4010
-#define		MS_X0_SHIFT				0
-#define		MS_Y0_SHIFT				4
-#define		MS_X1_SHIFT				8
-#define		MS_Y1_SHIFT				12
-#define		MS_X2_SHIFT				16
-#define		MS_Y2_SHIFT				20
-#define		MSBD0_Y_SHIFT				24
-#define		MSBD0_X_SHIFT				28
-#define	GB_MSPOS1			0x4014
-#define		MS_X3_SHIFT				0
-#define		MS_Y3_SHIFT				4
-#define		MS_X4_SHIFT				8
-#define		MS_Y4_SHIFT				12
-#define		MS_X5_SHIFT				16
-#define		MS_Y5_SHIFT				20
-#define		MSBD1_SHIFT				24
-#define GB_TILE_CONFIG			0x4018
-#define		ENABLE_TILING				(1 << 0)
-#define		PIPE_COUNT_MASK				0x0000000E
-#define		PIPE_COUNT_SHIFT			1
-#define		TILE_SIZE_8				(0 << 4)
-#define		TILE_SIZE_16				(1 << 4)
-#define		TILE_SIZE_32				(2 << 4)
-#define		SUBPIXEL_1_12				(0 << 16)
-#define		SUBPIXEL_1_16				(1 << 16)
-#define	GB_SELECT			0x401C
-#define	GB_AA_CONFIG			0x4020
-#define	GB_PIPE_SELECT			0x402C
-#define	GA_ENHANCE			0x4274
-#define		GA_DEADLOCK_CNTL			(1 << 0)
-#define		GA_FASTSYNC_CNTL			(1 << 1)
-#define	GA_POLY_MODE			0x4288
-#define		FRONT_PTYPE_POINT			(0 << 4)
-#define		FRONT_PTYPE_LINE			(1 << 4)
-#define		FRONT_PTYPE_TRIANGE			(2 << 4)
-#define		BACK_PTYPE_POINT			(0 << 7)
-#define		BACK_PTYPE_LINE				(1 << 7)
-#define		BACK_PTYPE_TRIANGE			(2 << 7)
-#define	GA_ROUND_MODE			0x428C
-#define		GEOMETRY_ROUND_TRUNC			(0 << 0)
-#define		GEOMETRY_ROUND_NEAREST			(1 << 0)
-#define		COLOR_ROUND_TRUNC			(0 << 2)
-#define		COLOR_ROUND_NEAREST			(1 << 2)
-#define	SU_REG_DEST			0x42C8
-#define	RB3D_DSTCACHE_CTLSTAT		0x4E4C
-#define		RB3D_DC_FLUSH				(2 << 0)
-#define		RB3D_DC_FREE				(2 << 2)
-#define		RB3D_DC_FINISH				(1 << 4)
-#define ZB_ZCACHE_CTLSTAT		0x4F18
-#define		ZC_FLUSH				(1 << 0)
-#define		ZC_FREE					(1 << 1)
-#define DC_LB_MEMORY_SPLIT		0x6520
-#define		DC_LB_MEMORY_SPLIT_MASK			0x00000003
-#define		DC_LB_MEMORY_SPLIT_SHIFT		0
-#define		DC_LB_MEMORY_SPLIT_D1HALF_D2HALF	0
-#define		DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q		1
-#define		DC_LB_MEMORY_SPLIT_D1_ONLY		2
-#define		DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q		3
-#define		DC_LB_MEMORY_SPLIT_SHIFT_MODE		(1 << 2)
-#define		DC_LB_DISP1_END_ADR_SHIFT		4
-#define		DC_LB_DISP1_END_ADR_MASK		0x00007FF0
-#define D1MODE_PRIORITY_A_CNT		0x6548
-#define		MODE_PRIORITY_MARK_MASK			0x00007FFF
-#define		MODE_PRIORITY_OFF			(1 << 16)
-#define		MODE_PRIORITY_ALWAYS_ON			(1 << 20)
-#define		MODE_PRIORITY_FORCE_MASK		(1 << 24)
-#define D1MODE_PRIORITY_B_CNT		0x654C
-#define LB_MAX_REQ_OUTSTANDING		0x6D58
-#define		LB_D1_MAX_REQ_OUTSTANDING_MASK		0x0000000F
-#define		LB_D1_MAX_REQ_OUTSTANDING_SHIFT		0
-#define		LB_D2_MAX_REQ_OUTSTANDING_MASK		0x000F0000
-#define		LB_D2_MAX_REQ_OUTSTANDING_SHIFT		16
-#define D2MODE_PRIORITY_A_CNT		0x6D48
-#define D2MODE_PRIORITY_B_CNT		0x6D4C
-
-/* ix[MC] registers */
-#define MC_FB_LOCATION			0x01
-#define		MC_FB_START_MASK			0x0000FFFF
-#define		MC_FB_START_SHIFT			0
-#define		MC_FB_TOP_MASK				0xFFFF0000
-#define		MC_FB_TOP_SHIFT				16
-#define MC_AGP_LOCATION			0x02
-#define		MC_AGP_START_MASK			0x0000FFFF
-#define		MC_AGP_START_SHIFT			0
-#define		MC_AGP_TOP_MASK				0xFFFF0000
-#define		MC_AGP_TOP_SHIFT			16
-#define MC_AGP_BASE			0x03
-#define MC_AGP_BASE_2			0x04
-#define	MC_CNTL				0x5
-#define		MEM_NUM_CHANNELS_MASK			0x00000003
-#define	MC_STATUS			0x08
-#define		MC_STATUS_IDLE				(1 << 4)
-#define	MC_MISC_LAT_TIMER		0x09
-#define		MC_CPR_INIT_LAT_MASK			0x0000000F
-#define		MC_VF_INIT_LAT_MASK			0x000000F0
-#define		MC_DISP0R_INIT_LAT_MASK			0x00000F00
-#define		MC_DISP0R_INIT_LAT_SHIFT		8
-#define		MC_DISP1R_INIT_LAT_MASK			0x0000F000
-#define		MC_DISP1R_INIT_LAT_SHIFT		12
-#define		MC_FIXED_INIT_LAT_MASK			0x000F0000
-#define		MC_E2R_INIT_LAT_MASK			0x00F00000
-#define		SAME_PAGE_PRIO_MASK			0x0F000000
-#define		MC_GLOBW_INIT_LAT_MASK			0xF0000000
-
-
-/*
- * PM4 packet
- */
-#define CP_PACKET0			0x00000000
-#define		PACKET0_BASE_INDEX_SHIFT	0
-#define		PACKET0_BASE_INDEX_MASK		(0x1ffff << 0)
-#define		PACKET0_COUNT_SHIFT		16
-#define		PACKET0_COUNT_MASK		(0x3fff << 16)
-#define CP_PACKET1			0x40000000
-#define CP_PACKET2			0x80000000
-#define		PACKET2_PAD_SHIFT		0
-#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
-#define CP_PACKET3			0xC0000000
-#define		PACKET3_IT_OPCODE_SHIFT		8
-#define		PACKET3_IT_OPCODE_MASK		(0xff << 8)
-#define		PACKET3_COUNT_SHIFT		16
-#define		PACKET3_COUNT_MASK		(0x3fff << 16)
-/* PACKET3 op code */
-#define		PACKET3_NOP			0x10
-#define		PACKET3_3D_DRAW_VBUF		0x28
-#define		PACKET3_3D_DRAW_IMMD		0x29
-#define		PACKET3_3D_DRAW_INDX		0x2A
-#define		PACKET3_3D_LOAD_VBPNTR		0x2F
-#define		PACKET3_INDX_BUFFER		0x33
-#define		PACKET3_3D_DRAW_VBUF_2		0x34
-#define		PACKET3_3D_DRAW_IMMD_2		0x35
-#define		PACKET3_3D_DRAW_INDX_2		0x36
-#define		PACKET3_BITBLT_MULTI		0x9B
-
-#define PACKET0(reg, n)	(CP_PACKET0 |					\
-			 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |	\
-			 REG_SET(PACKET0_COUNT, (n)))
-#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
-#define PACKET3(op, n)	(CP_PACKET3 |					\
-			 REG_SET(PACKET3_IT_OPCODE, (op)) |		\
-			 REG_SET(PACKET3_COUNT, (n)))
-
-/* Registers */
-#define R_0000F0_RBBM_SOFT_RESET                     0x0000F0
-#define   S_0000F0_SOFT_RESET_CP(x)                    (((x) & 0x1) << 0)
-#define   G_0000F0_SOFT_RESET_CP(x)                    (((x) >> 0) & 0x1)
-#define   C_0000F0_SOFT_RESET_CP                       0xFFFFFFFE
-#define   S_0000F0_SOFT_RESET_HI(x)                    (((x) & 0x1) << 1)
-#define   G_0000F0_SOFT_RESET_HI(x)                    (((x) >> 1) & 0x1)
-#define   C_0000F0_SOFT_RESET_HI                       0xFFFFFFFD
-#define   S_0000F0_SOFT_RESET_VAP(x)                   (((x) & 0x1) << 2)
-#define   G_0000F0_SOFT_RESET_VAP(x)                   (((x) >> 2) & 0x1)
-#define   C_0000F0_SOFT_RESET_VAP                      0xFFFFFFFB
-#define   S_0000F0_SOFT_RESET_RE(x)                    (((x) & 0x1) << 3)
-#define   G_0000F0_SOFT_RESET_RE(x)                    (((x) >> 3) & 0x1)
-#define   C_0000F0_SOFT_RESET_RE                       0xFFFFFFF7
-#define   S_0000F0_SOFT_RESET_PP(x)                    (((x) & 0x1) << 4)
-#define   G_0000F0_SOFT_RESET_PP(x)                    (((x) >> 4) & 0x1)
-#define   C_0000F0_SOFT_RESET_PP                       0xFFFFFFEF
-#define   S_0000F0_SOFT_RESET_E2(x)                    (((x) & 0x1) << 5)
-#define   G_0000F0_SOFT_RESET_E2(x)                    (((x) >> 5) & 0x1)
-#define   C_0000F0_SOFT_RESET_E2                       0xFFFFFFDF
-#define   S_0000F0_SOFT_RESET_RB(x)                    (((x) & 0x1) << 6)
-#define   G_0000F0_SOFT_RESET_RB(x)                    (((x) >> 6) & 0x1)
-#define   C_0000F0_SOFT_RESET_RB                       0xFFFFFFBF
-#define   S_0000F0_SOFT_RESET_HDP(x)                   (((x) & 0x1) << 7)
-#define   G_0000F0_SOFT_RESET_HDP(x)                   (((x) >> 7) & 0x1)
-#define   C_0000F0_SOFT_RESET_HDP                      0xFFFFFF7F
-#define   S_0000F0_SOFT_RESET_MC(x)                    (((x) & 0x1) << 8)
-#define   G_0000F0_SOFT_RESET_MC(x)                    (((x) >> 8) & 0x1)
-#define   C_0000F0_SOFT_RESET_MC                       0xFFFFFEFF
-#define   S_0000F0_SOFT_RESET_AIC(x)                   (((x) & 0x1) << 9)
-#define   G_0000F0_SOFT_RESET_AIC(x)                   (((x) >> 9) & 0x1)
-#define   C_0000F0_SOFT_RESET_AIC                      0xFFFFFDFF
-#define   S_0000F0_SOFT_RESET_VIP(x)                   (((x) & 0x1) << 10)
-#define   G_0000F0_SOFT_RESET_VIP(x)                   (((x) >> 10) & 0x1)
-#define   C_0000F0_SOFT_RESET_VIP                      0xFFFFFBFF
-#define   S_0000F0_SOFT_RESET_DISP(x)                  (((x) & 0x1) << 11)
-#define   G_0000F0_SOFT_RESET_DISP(x)                  (((x) >> 11) & 0x1)
-#define   C_0000F0_SOFT_RESET_DISP                     0xFFFFF7FF
-#define   S_0000F0_SOFT_RESET_CG(x)                    (((x) & 0x1) << 12)
-#define   G_0000F0_SOFT_RESET_CG(x)                    (((x) >> 12) & 0x1)
-#define   C_0000F0_SOFT_RESET_CG                       0xFFFFEFFF
-#define   S_0000F0_SOFT_RESET_GA(x)                    (((x) & 0x1) << 13)
-#define   G_0000F0_SOFT_RESET_GA(x)                    (((x) >> 13) & 0x1)
-#define   C_0000F0_SOFT_RESET_GA                       0xFFFFDFFF
-#define   S_0000F0_SOFT_RESET_IDCT(x)                  (((x) & 0x1) << 14)
-#define   G_0000F0_SOFT_RESET_IDCT(x)                  (((x) >> 14) & 0x1)
-#define   C_0000F0_SOFT_RESET_IDCT                     0xFFFFBFFF
-#define R_0000F8_CONFIG_MEMSIZE                      0x0000F8
-#define   S_0000F8_CONFIG_MEMSIZE(x)                   (((x) & 0xFFFFFFFF) << 0)
-#define   G_0000F8_CONFIG_MEMSIZE(x)                   (((x) >> 0) & 0xFFFFFFFF)
-#define   C_0000F8_CONFIG_MEMSIZE                      0x00000000
-#define R_000134_HDP_FB_LOCATION                     0x000134
-#define   S_000134_HDP_FB_START(x)                     (((x) & 0xFFFF) << 0)
-#define   G_000134_HDP_FB_START(x)                     (((x) >> 0) & 0xFFFF)
-#define   C_000134_HDP_FB_START                        0xFFFF0000
-#define R_000300_VGA_RENDER_CONTROL                  0x000300
-#define   S_000300_VGA_BLINK_RATE(x)                   (((x) & 0x1F) << 0)
-#define   G_000300_VGA_BLINK_RATE(x)                   (((x) >> 0) & 0x1F)
-#define   C_000300_VGA_BLINK_RATE                      0xFFFFFFE0
-#define   S_000300_VGA_BLINK_MODE(x)                   (((x) & 0x3) << 5)
-#define   G_000300_VGA_BLINK_MODE(x)                   (((x) >> 5) & 0x3)
-#define   C_000300_VGA_BLINK_MODE                      0xFFFFFF9F
-#define   S_000300_VGA_CURSOR_BLINK_INVERT(x)          (((x) & 0x1) << 7)
-#define   G_000300_VGA_CURSOR_BLINK_INVERT(x)          (((x) >> 7) & 0x1)
-#define   C_000300_VGA_CURSOR_BLINK_INVERT             0xFFFFFF7F
-#define   S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x)       (((x) & 0x1) << 8)
-#define   G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x)       (((x) >> 8) & 0x1)
-#define   C_000300_VGA_EXTD_ADDR_COUNT_ENABLE          0xFFFFFEFF
-#define   S_000300_VGA_VSTATUS_CNTL(x)                 (((x) & 0x3) << 16)
-#define   G_000300_VGA_VSTATUS_CNTL(x)                 (((x) >> 16) & 0x3)
-#define   C_000300_VGA_VSTATUS_CNTL                    0xFFFCFFFF
-#define   S_000300_VGA_LOCK_8DOT(x)                    (((x) & 0x1) << 24)
-#define   G_000300_VGA_LOCK_8DOT(x)                    (((x) >> 24) & 0x1)
-#define   C_000300_VGA_LOCK_8DOT                       0xFEFFFFFF
-#define   S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25)
-#define   G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1)
-#define   C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL    0xFDFFFFFF
-#define R_000310_VGA_MEMORY_BASE_ADDRESS             0x000310
-#define   S_000310_VGA_MEMORY_BASE_ADDRESS(x)          (((x) & 0xFFFFFFFF) << 0)
-#define   G_000310_VGA_MEMORY_BASE_ADDRESS(x)          (((x) >> 0) & 0xFFFFFFFF)
-#define   C_000310_VGA_MEMORY_BASE_ADDRESS             0x00000000
-#define R_000328_VGA_HDP_CONTROL                     0x000328
-#define   S_000328_VGA_MEM_PAGE_SELECT_EN(x)           (((x) & 0x1) << 0)
-#define   G_000328_VGA_MEM_PAGE_SELECT_EN(x)           (((x) >> 0) & 0x1)
-#define   C_000328_VGA_MEM_PAGE_SELECT_EN              0xFFFFFFFE
-#define   S_000328_VGA_RBBM_LOCK_DISABLE(x)            (((x) & 0x1) << 8)
-#define   G_000328_VGA_RBBM_LOCK_DISABLE(x)            (((x) >> 8) & 0x1)
-#define   C_000328_VGA_RBBM_LOCK_DISABLE               0xFFFFFEFF
-#define   S_000328_VGA_SOFT_RESET(x)                   (((x) & 0x1) << 16)
-#define   G_000328_VGA_SOFT_RESET(x)                   (((x) >> 16) & 0x1)
-#define   C_000328_VGA_SOFT_RESET                      0xFFFEFFFF
-#define   S_000328_VGA_TEST_RESET_CONTROL(x)           (((x) & 0x1) << 24)
-#define   G_000328_VGA_TEST_RESET_CONTROL(x)           (((x) >> 24) & 0x1)
-#define   C_000328_VGA_TEST_RESET_CONTROL              0xFEFFFFFF
-#define R_000330_D1VGA_CONTROL                       0x000330
-#define   S_000330_D1VGA_MODE_ENABLE(x)                (((x) & 0x1) << 0)
-#define   G_000330_D1VGA_MODE_ENABLE(x)                (((x) >> 0) & 0x1)
-#define   C_000330_D1VGA_MODE_ENABLE                   0xFFFFFFFE
-#define   S_000330_D1VGA_TIMING_SELECT(x)              (((x) & 0x1) << 8)
-#define   G_000330_D1VGA_TIMING_SELECT(x)              (((x) >> 8) & 0x1)
-#define   C_000330_D1VGA_TIMING_SELECT                 0xFFFFFEFF
-#define   S_000330_D1VGA_SYNC_POLARITY_SELECT(x)       (((x) & 0x1) << 9)
-#define   G_000330_D1VGA_SYNC_POLARITY_SELECT(x)       (((x) >> 9) & 0x1)
-#define   C_000330_D1VGA_SYNC_POLARITY_SELECT          0xFFFFFDFF
-#define   S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x)     (((x) & 0x1) << 10)
-#define   G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x)     (((x) >> 10) & 0x1)
-#define   C_000330_D1VGA_OVERSCAN_TIMING_SELECT        0xFFFFFBFF
-#define   S_000330_D1VGA_OVERSCAN_COLOR_EN(x)          (((x) & 0x1) << 16)
-#define   G_000330_D1VGA_OVERSCAN_COLOR_EN(x)          (((x) >> 16) & 0x1)
-#define   C_000330_D1VGA_OVERSCAN_COLOR_EN             0xFFFEFFFF
-#define   S_000330_D1VGA_ROTATE(x)                     (((x) & 0x3) << 24)
-#define   G_000330_D1VGA_ROTATE(x)                     (((x) >> 24) & 0x3)
-#define   C_000330_D1VGA_ROTATE                        0xFCFFFFFF
-#define R_000338_D2VGA_CONTROL                       0x000338
-#define   S_000338_D2VGA_MODE_ENABLE(x)                (((x) & 0x1) << 0)
-#define   G_000338_D2VGA_MODE_ENABLE(x)                (((x) >> 0) & 0x1)
-#define   C_000338_D2VGA_MODE_ENABLE                   0xFFFFFFFE
-#define   S_000338_D2VGA_TIMING_SELECT(x)              (((x) & 0x1) << 8)
-#define   G_000338_D2VGA_TIMING_SELECT(x)              (((x) >> 8) & 0x1)
-#define   C_000338_D2VGA_TIMING_SELECT                 0xFFFFFEFF
-#define   S_000338_D2VGA_SYNC_POLARITY_SELECT(x)       (((x) & 0x1) << 9)
-#define   G_000338_D2VGA_SYNC_POLARITY_SELECT(x)       (((x) >> 9) & 0x1)
-#define   C_000338_D2VGA_SYNC_POLARITY_SELECT          0xFFFFFDFF
-#define   S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x)     (((x) & 0x1) << 10)
-#define   G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x)     (((x) >> 10) & 0x1)
-#define   C_000338_D2VGA_OVERSCAN_TIMING_SELECT        0xFFFFFBFF
-#define   S_000338_D2VGA_OVERSCAN_COLOR_EN(x)          (((x) & 0x1) << 16)
-#define   G_000338_D2VGA_OVERSCAN_COLOR_EN(x)          (((x) >> 16) & 0x1)
-#define   C_000338_D2VGA_OVERSCAN_COLOR_EN             0xFFFEFFFF
-#define   S_000338_D2VGA_ROTATE(x)                     (((x) & 0x3) << 24)
-#define   G_000338_D2VGA_ROTATE(x)                     (((x) >> 24) & 0x3)
-#define   C_000338_D2VGA_ROTATE                        0xFCFFFFFF
-#define R_0007C0_CP_STAT                             0x0007C0
-#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
-#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
-#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
-#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
-#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
-#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
-#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
-#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
-#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
-#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
-#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
-#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
-#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
-#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
-#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
-#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
-#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
-#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
-#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
-#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
-#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
-#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
-#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
-#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
-#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
-#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
-#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
-#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
-#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
-#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
-#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
-#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
-#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
-#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
-#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
-#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
-#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
-#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
-#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
-#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
-#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
-#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
-#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
-#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
-#define R_000E40_RBBM_STATUS                         0x000E40
-#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
-#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
-#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
-#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
-#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
-#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
-#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
-#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
-#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
-#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
-#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
-#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
-#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
-#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
-#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
-#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
-#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
-#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
-#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
-#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
-#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
-#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
-#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
-#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
-#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
-#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
-#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
-#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
-#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
-#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
-#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
-#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
-#define   C_000E40_E2_BUSY                             0xFFFDFFFF
-#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
-#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
-#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
-#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
-#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
-#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
-#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
-#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
-#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
-#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
-#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
-#define   C_000E40_RE_BUSY                             0xFFDFFFFF
-#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
-#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
-#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
-#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
-#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
-#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
-#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
-#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
-#define   C_000E40_PB_BUSY                             0xFEFFFFFF
-#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
-#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
-#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
-#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
-#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
-#define   C_000E40_GA_BUSY                             0xFBFFFFFF
-#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
-#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
-#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
-#define   S_000E40_RBBM_HIBUSY(x)                      (((x) & 0x1) << 28)
-#define   G_000E40_RBBM_HIBUSY(x)                      (((x) >> 28) & 0x1)
-#define   C_000E40_RBBM_HIBUSY                         0xEFFFFFFF
-#define   S_000E40_SKID_CFBUSY(x)                      (((x) & 0x1) << 29)
-#define   G_000E40_SKID_CFBUSY(x)                      (((x) >> 29) & 0x1)
-#define   C_000E40_SKID_CFBUSY                         0xDFFFFFFF
-#define   S_000E40_VAP_VF_BUSY(x)                      (((x) & 0x1) << 30)
-#define   G_000E40_VAP_VF_BUSY(x)                      (((x) >> 30) & 0x1)
-#define   C_000E40_VAP_VF_BUSY                         0xBFFFFFFF
-#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
-#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
-#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
-#define R_006080_D1CRTC_CONTROL                      0x006080
-#define   S_006080_D1CRTC_MASTER_EN(x)                 (((x) & 0x1) << 0)
-#define   G_006080_D1CRTC_MASTER_EN(x)                 (((x) >> 0) & 0x1)
-#define   C_006080_D1CRTC_MASTER_EN                    0xFFFFFFFE
-#define   S_006080_D1CRTC_SYNC_RESET_SEL(x)            (((x) & 0x1) << 4)
-#define   G_006080_D1CRTC_SYNC_RESET_SEL(x)            (((x) >> 4) & 0x1)
-#define   C_006080_D1CRTC_SYNC_RESET_SEL               0xFFFFFFEF
-#define   S_006080_D1CRTC_DISABLE_POINT_CNTL(x)        (((x) & 0x3) << 8)
-#define   G_006080_D1CRTC_DISABLE_POINT_CNTL(x)        (((x) >> 8) & 0x3)
-#define   C_006080_D1CRTC_DISABLE_POINT_CNTL           0xFFFFFCFF
-#define   S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x)   (((x) & 0x1) << 16)
-#define   G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x)   (((x) >> 16) & 0x1)
-#define   C_006080_D1CRTC_CURRENT_MASTER_EN_STATE      0xFFFEFFFF
-#define   S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24)
-#define   G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1)
-#define   C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE    0xFEFFFFFF
-#define R_0060E8_D1CRTC_UPDATE_LOCK                  0x0060E8
-#define   S_0060E8_D1CRTC_UPDATE_LOCK(x)               (((x) & 0x1) << 0)
-#define   G_0060E8_D1CRTC_UPDATE_LOCK(x)               (((x) >> 0) & 0x1)
-#define   C_0060E8_D1CRTC_UPDATE_LOCK                  0xFFFFFFFE
-#define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS      0x006110
-#define   S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x)   (((x) & 0xFFFFFFFF) << 0)
-#define   G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x)   (((x) >> 0) & 0xFFFFFFFF)
-#define   C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS      0x00000000
-#define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS    0x006118
-#define   S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
-#define   G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
-#define   C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS    0x00000000
-#define R_006880_D2CRTC_CONTROL                      0x006880
-#define   S_006880_D2CRTC_MASTER_EN(x)                 (((x) & 0x1) << 0)
-#define   G_006880_D2CRTC_MASTER_EN(x)                 (((x) >> 0) & 0x1)
-#define   C_006880_D2CRTC_MASTER_EN                    0xFFFFFFFE
-#define   S_006880_D2CRTC_SYNC_RESET_SEL(x)            (((x) & 0x1) << 4)
-#define   G_006880_D2CRTC_SYNC_RESET_SEL(x)            (((x) >> 4) & 0x1)
-#define   C_006880_D2CRTC_SYNC_RESET_SEL               0xFFFFFFEF
-#define   S_006880_D2CRTC_DISABLE_POINT_CNTL(x)        (((x) & 0x3) << 8)
-#define   G_006880_D2CRTC_DISABLE_POINT_CNTL(x)        (((x) >> 8) & 0x3)
-#define   C_006880_D2CRTC_DISABLE_POINT_CNTL           0xFFFFFCFF
-#define   S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x)   (((x) & 0x1) << 16)
-#define   G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x)   (((x) >> 16) & 0x1)
-#define   C_006880_D2CRTC_CURRENT_MASTER_EN_STATE      0xFFFEFFFF
-#define   S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24)
-#define   G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1)
-#define   C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE    0xFEFFFFFF
-#define R_0068E8_D2CRTC_UPDATE_LOCK                  0x0068E8
-#define   S_0068E8_D2CRTC_UPDATE_LOCK(x)               (((x) & 0x1) << 0)
-#define   G_0068E8_D2CRTC_UPDATE_LOCK(x)               (((x) >> 0) & 0x1)
-#define   C_0068E8_D2CRTC_UPDATE_LOCK                  0xFFFFFFFE
-#define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS      0x006910
-#define   S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x)   (((x) & 0xFFFFFFFF) << 0)
-#define   G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x)   (((x) >> 0) & 0xFFFFFFFF)
-#define   C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS      0x00000000
-#define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS    0x006918
-#define   S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
-#define   G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
-#define   C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS    0x00000000
-
-
-#define R_000001_MC_FB_LOCATION                      0x000001
-#define   S_000001_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
-#define   G_000001_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
-#define   C_000001_MC_FB_START                         0xFFFF0000
-#define   S_000001_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
-#define   G_000001_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
-#define   C_000001_MC_FB_TOP                           0x0000FFFF
-#define R_000002_MC_AGP_LOCATION                     0x000002
-#define   S_000002_MC_AGP_START(x)                     (((x) & 0xFFFF) << 0)
-#define   G_000002_MC_AGP_START(x)                     (((x) >> 0) & 0xFFFF)
-#define   C_000002_MC_AGP_START                        0xFFFF0000
-#define   S_000002_MC_AGP_TOP(x)                       (((x) & 0xFFFF) << 16)
-#define   G_000002_MC_AGP_TOP(x)                       (((x) >> 16) & 0xFFFF)
-#define   C_000002_MC_AGP_TOP                          0x0000FFFF
-#define R_000003_MC_AGP_BASE                         0x000003
-#define   S_000003_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
-#define   G_000003_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
-#define   C_000003_AGP_BASE_ADDR                       0x00000000
-#define R_000004_MC_AGP_BASE_2                       0x000004
-#define   S_000004_AGP_BASE_ADDR_2(x)                  (((x) & 0xF) << 0)
-#define   G_000004_AGP_BASE_ADDR_2(x)                  (((x) >> 0) & 0xF)
-#define   C_000004_AGP_BASE_ADDR_2                     0xFFFFFFF0
-
-
-#define R_00000F_CP_DYN_CNTL                         0x00000F
-#define   S_00000F_CP_FORCEON(x)                       (((x) & 0x1) << 0)
-#define   G_00000F_CP_FORCEON(x)                       (((x) >> 0) & 0x1)
-#define   C_00000F_CP_FORCEON                          0xFFFFFFFE
-#define   S_00000F_CP_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 1)
-#define   G_00000F_CP_MAX_DYN_STOP_LAT(x)              (((x) >> 1) & 0x1)
-#define   C_00000F_CP_MAX_DYN_STOP_LAT                 0xFFFFFFFD
-#define   S_00000F_CP_CLOCK_STATUS(x)                  (((x) & 0x1) << 2)
-#define   G_00000F_CP_CLOCK_STATUS(x)                  (((x) >> 2) & 0x1)
-#define   C_00000F_CP_CLOCK_STATUS                     0xFFFFFFFB
-#define   S_00000F_CP_PROG_SHUTOFF(x)                  (((x) & 0x1) << 3)
-#define   G_00000F_CP_PROG_SHUTOFF(x)                  (((x) >> 3) & 0x1)
-#define   C_00000F_CP_PROG_SHUTOFF                     0xFFFFFFF7
-#define   S_00000F_CP_PROG_DELAY_VALUE(x)              (((x) & 0xFF) << 4)
-#define   G_00000F_CP_PROG_DELAY_VALUE(x)              (((x) >> 4) & 0xFF)
-#define   C_00000F_CP_PROG_DELAY_VALUE                 0xFFFFF00F
-#define   S_00000F_CP_LOWER_POWER_IDLE(x)              (((x) & 0xFF) << 12)
-#define   G_00000F_CP_LOWER_POWER_IDLE(x)              (((x) >> 12) & 0xFF)
-#define   C_00000F_CP_LOWER_POWER_IDLE                 0xFFF00FFF
-#define   S_00000F_CP_LOWER_POWER_IGNORE(x)            (((x) & 0x1) << 20)
-#define   G_00000F_CP_LOWER_POWER_IGNORE(x)            (((x) >> 20) & 0x1)
-#define   C_00000F_CP_LOWER_POWER_IGNORE               0xFFEFFFFF
-#define   S_00000F_CP_NORMAL_POWER_IGNORE(x)           (((x) & 0x1) << 21)
-#define   G_00000F_CP_NORMAL_POWER_IGNORE(x)           (((x) >> 21) & 0x1)
-#define   C_00000F_CP_NORMAL_POWER_IGNORE              0xFFDFFFFF
-#define   S_00000F_SPARE(x)                            (((x) & 0x3) << 22)
-#define   G_00000F_SPARE(x)                            (((x) >> 22) & 0x3)
-#define   C_00000F_SPARE                               0xFF3FFFFF
-#define   S_00000F_CP_NORMAL_POWER_BUSY(x)             (((x) & 0xFF) << 24)
-#define   G_00000F_CP_NORMAL_POWER_BUSY(x)             (((x) >> 24) & 0xFF)
-#define   C_00000F_CP_NORMAL_POWER_BUSY                0x00FFFFFF
-#define R_000011_E2_DYN_CNTL                         0x000011
-#define   S_000011_E2_FORCEON(x)                       (((x) & 0x1) << 0)
-#define   G_000011_E2_FORCEON(x)                       (((x) >> 0) & 0x1)
-#define   C_000011_E2_FORCEON                          0xFFFFFFFE
-#define   S_000011_E2_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 1)
-#define   G_000011_E2_MAX_DYN_STOP_LAT(x)              (((x) >> 1) & 0x1)
-#define   C_000011_E2_MAX_DYN_STOP_LAT                 0xFFFFFFFD
-#define   S_000011_E2_CLOCK_STATUS(x)                  (((x) & 0x1) << 2)
-#define   G_000011_E2_CLOCK_STATUS(x)                  (((x) >> 2) & 0x1)
-#define   C_000011_E2_CLOCK_STATUS                     0xFFFFFFFB
-#define   S_000011_E2_PROG_SHUTOFF(x)                  (((x) & 0x1) << 3)
-#define   G_000011_E2_PROG_SHUTOFF(x)                  (((x) >> 3) & 0x1)
-#define   C_000011_E2_PROG_SHUTOFF                     0xFFFFFFF7
-#define   S_000011_E2_PROG_DELAY_VALUE(x)              (((x) & 0xFF) << 4)
-#define   G_000011_E2_PROG_DELAY_VALUE(x)              (((x) >> 4) & 0xFF)
-#define   C_000011_E2_PROG_DELAY_VALUE                 0xFFFFF00F
-#define   S_000011_E2_LOWER_POWER_IDLE(x)              (((x) & 0xFF) << 12)
-#define   G_000011_E2_LOWER_POWER_IDLE(x)              (((x) >> 12) & 0xFF)
-#define   C_000011_E2_LOWER_POWER_IDLE                 0xFFF00FFF
-#define   S_000011_E2_LOWER_POWER_IGNORE(x)            (((x) & 0x1) << 20)
-#define   G_000011_E2_LOWER_POWER_IGNORE(x)            (((x) >> 20) & 0x1)
-#define   C_000011_E2_LOWER_POWER_IGNORE               0xFFEFFFFF
-#define   S_000011_E2_NORMAL_POWER_IGNORE(x)           (((x) & 0x1) << 21)
-#define   G_000011_E2_NORMAL_POWER_IGNORE(x)           (((x) >> 21) & 0x1)
-#define   C_000011_E2_NORMAL_POWER_IGNORE              0xFFDFFFFF
-#define   S_000011_SPARE(x)                            (((x) & 0x3) << 22)
-#define   G_000011_SPARE(x)                            (((x) >> 22) & 0x3)
-#define   C_000011_SPARE                               0xFF3FFFFF
-#define   S_000011_E2_NORMAL_POWER_BUSY(x)             (((x) & 0xFF) << 24)
-#define   G_000011_E2_NORMAL_POWER_BUSY(x)             (((x) >> 24) & 0xFF)
-#define   C_000011_E2_NORMAL_POWER_BUSY                0x00FFFFFF
-#define R_000013_IDCT_DYN_CNTL                       0x000013
-#define   S_000013_IDCT_FORCEON(x)                     (((x) & 0x1) << 0)
-#define   G_000013_IDCT_FORCEON(x)                     (((x) >> 0) & 0x1)
-#define   C_000013_IDCT_FORCEON                        0xFFFFFFFE
-#define   S_000013_IDCT_MAX_DYN_STOP_LAT(x)            (((x) & 0x1) << 1)
-#define   G_000013_IDCT_MAX_DYN_STOP_LAT(x)            (((x) >> 1) & 0x1)
-#define   C_000013_IDCT_MAX_DYN_STOP_LAT               0xFFFFFFFD
-#define   S_000013_IDCT_CLOCK_STATUS(x)                (((x) & 0x1) << 2)
-#define   G_000013_IDCT_CLOCK_STATUS(x)                (((x) >> 2) & 0x1)
-#define   C_000013_IDCT_CLOCK_STATUS                   0xFFFFFFFB
-#define   S_000013_IDCT_PROG_SHUTOFF(x)                (((x) & 0x1) << 3)
-#define   G_000013_IDCT_PROG_SHUTOFF(x)                (((x) >> 3) & 0x1)
-#define   C_000013_IDCT_PROG_SHUTOFF                   0xFFFFFFF7
-#define   S_000013_IDCT_PROG_DELAY_VALUE(x)            (((x) & 0xFF) << 4)
-#define   G_000013_IDCT_PROG_DELAY_VALUE(x)            (((x) >> 4) & 0xFF)
-#define   C_000013_IDCT_PROG_DELAY_VALUE               0xFFFFF00F
-#define   S_000013_IDCT_LOWER_POWER_IDLE(x)            (((x) & 0xFF) << 12)
-#define   G_000013_IDCT_LOWER_POWER_IDLE(x)            (((x) >> 12) & 0xFF)
-#define   C_000013_IDCT_LOWER_POWER_IDLE               0xFFF00FFF
-#define   S_000013_IDCT_LOWER_POWER_IGNORE(x)          (((x) & 0x1) << 20)
-#define   G_000013_IDCT_LOWER_POWER_IGNORE(x)          (((x) >> 20) & 0x1)
-#define   C_000013_IDCT_LOWER_POWER_IGNORE             0xFFEFFFFF
-#define   S_000013_IDCT_NORMAL_POWER_IGNORE(x)         (((x) & 0x1) << 21)
-#define   G_000013_IDCT_NORMAL_POWER_IGNORE(x)         (((x) >> 21) & 0x1)
-#define   C_000013_IDCT_NORMAL_POWER_IGNORE            0xFFDFFFFF
-#define   S_000013_SPARE(x)                            (((x) & 0x3) << 22)
-#define   G_000013_SPARE(x)                            (((x) >> 22) & 0x3)
-#define   C_000013_SPARE                               0xFF3FFFFF
-#define   S_000013_IDCT_NORMAL_POWER_BUSY(x)           (((x) & 0xFF) << 24)
-#define   G_000013_IDCT_NORMAL_POWER_BUSY(x)           (((x) >> 24) & 0xFF)
-#define   C_000013_IDCT_NORMAL_POWER_BUSY              0x00FFFFFF
-
-#endif
diff --git a/hw/display/rv6xx_dpm.h b/hw/display/rv6xx_dpm.h
deleted file mode 100644
index 8035d53ebe..0000000000
--- a/hw/display/rv6xx_dpm.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Alex Deucher
- */
-
-#ifndef __RV6XX_DPM_H__
-#define __RV6XX_DPM_H__
-
-#include "r600_dpm.h"
-
-/* Represents a single SCLK step. */
-struct rv6xx_sclk_stepping
-{
-    u32 vco_frequency;
-    u32 post_divider;
-};
-
-struct rv6xx_pm_hw_state {
-	u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
-	u32 mclks[R600_PM_NUMBER_OF_MCLKS];
-	u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
-	bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
-	bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
-	u8 high_sclk_index;
-	u8 medium_sclk_index;
-	u8 low_sclk_index;
-	u8 high_mclk_index;
-	u8 medium_mclk_index;
-	u8 low_mclk_index;
-	u8 high_vddc_index;
-	u8 medium_vddc_index;
-	u8 low_vddc_index;
-	u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
-	u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
-};
-
-struct rv6xx_power_info {
-	/* flags */
-	bool voltage_control;
-	bool sclk_ss;
-	bool mclk_ss;
-	bool dynamic_ss;
-	bool dynamic_pcie_gen2;
-	bool thermal_protection;
-	bool display_gap;
-	bool gfx_clock_gating;
-	/* clk values */
-	u32 fb_div_scale;
-	u32 spll_ref_div;
-	u32 mpll_ref_div;
-	u32 bsu;
-	u32 bsp;
-	/* */
-	u32 active_auto_throttle_sources;
-	/* current power state */
-	u32 restricted_levels;
-	struct rv6xx_pm_hw_state hw;
-};
-
-struct rv6xx_pl {
-	u32 sclk;
-	u32 mclk;
-	u16 vddc;
-	u32 flags;
-};
-
-struct rv6xx_ps {
-	struct rv6xx_pl high;
-	struct rv6xx_pl medium;
-	struct rv6xx_pl low;
-};
-
-#define RV6XX_DEFAULT_VCLK_FREQ  40000 /* 10 khz */
-#define RV6XX_DEFAULT_DCLK_FREQ  30000 /* 10 khz */
-
-#endif
diff --git a/hw/display/rv6xxd.h b/hw/display/rv6xxd.h
deleted file mode 100644
index 34e86f90b4..0000000000
--- a/hw/display/rv6xxd.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef RV6XXD_H
-#define RV6XXD_H
-
-/* RV6xx power management */
-#define SPLL_CNTL_MODE                                    0x60c
-#       define SPLL_DIV_SYNC                              (1 << 5)
-
-#define GENERAL_PWRMGT                                    0x618
-#       define GLOBAL_PWRMGT_EN                           (1 << 0)
-#       define STATIC_PM_EN                               (1 << 1)
-#       define MOBILE_SU                                  (1 << 2)
-#       define THERMAL_PROTECTION_DIS                     (1 << 3)
-#       define THERMAL_PROTECTION_TYPE                    (1 << 4)
-#       define ENABLE_GEN2PCIE                            (1 << 5)
-#       define SW_GPIO_INDEX(x)                           ((x) << 6)
-#       define SW_GPIO_INDEX_MASK                         (3 << 6)
-#       define LOW_VOLT_D2_ACPI                           (1 << 8)
-#       define LOW_VOLT_D3_ACPI                           (1 << 9)
-#       define VOLT_PWRMGT_EN                             (1 << 10)
-#       define BACKBIAS_PAD_EN                            (1 << 16)
-#       define BACKBIAS_VALUE                             (1 << 17)
-#       define BACKBIAS_DPM_CNTL                          (1 << 18)
-#       define DYN_SPREAD_SPECTRUM_EN                     (1 << 21)
-
-#define MCLK_PWRMGT_CNTL                                  0x624
-#       define MPLL_PWRMGT_OFF                            (1 << 0)
-#       define YCLK_TURNOFF                               (1 << 1)
-#       define MPLL_TURNOFF                               (1 << 2)
-#       define SU_MCLK_USE_BCLK                           (1 << 3)
-#       define DLL_READY                                  (1 << 4)
-#       define MC_BUSY                                    (1 << 5)
-#       define MC_INT_CNTL                                (1 << 7)
-#       define MRDCKA_SLEEP                               (1 << 8)
-#       define MRDCKB_SLEEP                               (1 << 9)
-#       define MRDCKC_SLEEP                               (1 << 10)
-#       define MRDCKD_SLEEP                               (1 << 11)
-#       define MRDCKE_SLEEP                               (1 << 12)
-#       define MRDCKF_SLEEP                               (1 << 13)
-#       define MRDCKG_SLEEP                               (1 << 14)
-#       define MRDCKH_SLEEP                               (1 << 15)
-#       define MRDCKA_RESET                               (1 << 16)
-#       define MRDCKB_RESET                               (1 << 17)
-#       define MRDCKC_RESET                               (1 << 18)
-#       define MRDCKD_RESET                               (1 << 19)
-#       define MRDCKE_RESET                               (1 << 20)
-#       define MRDCKF_RESET                               (1 << 21)
-#       define MRDCKG_RESET                               (1 << 22)
-#       define MRDCKH_RESET                               (1 << 23)
-#       define DLL_READY_READ                             (1 << 24)
-#       define USE_DISPLAY_GAP                            (1 << 25)
-#       define USE_DISPLAY_URGENT_NORMAL                  (1 << 26)
-#       define USE_DISPLAY_GAP_CTXSW                      (1 << 27)
-#       define MPLL_TURNOFF_D2                            (1 << 28)
-#       define USE_DISPLAY_URGENT_CTXSW                   (1 << 29)
-
-#define MPLL_FREQ_LEVEL_0                                 0x6e8
-#       define LEVEL0_MPLL_POST_DIV(x)                    ((x) << 0)
-#       define LEVEL0_MPLL_POST_DIV_MASK                  (0xff << 0)
-#       define LEVEL0_MPLL_FB_DIV(x)                      ((x) << 8)
-#       define LEVEL0_MPLL_FB_DIV_MASK                    (0xfff << 8)
-#       define LEVEL0_MPLL_REF_DIV(x)                     ((x) << 20)
-#       define LEVEL0_MPLL_REF_DIV_MASK                   (0x3f << 20)
-#       define LEVEL0_MPLL_DIV_EN                         (1 << 28)
-#       define LEVEL0_DLL_BYPASS                          (1 << 29)
-#       define LEVEL0_DLL_RESET                           (1 << 30)
-
-#define VID_RT                                            0x6f8
-#       define VID_CRT(x)                                 ((x) << 0)
-#       define VID_CRT_MASK                               (0x1fff << 0)
-#       define VID_CRTU(x)                                ((x) << 13)
-#       define VID_CRTU_MASK                              (7 << 13)
-#       define SSTU(x)                                    ((x) << 16)
-#       define SSTU_MASK                                  (7 << 16)
-#       define VID_SWT(x)                                 ((x) << 19)
-#       define VID_SWT_MASK                               (0x1f << 19)
-#       define BRT(x)                                     ((x) << 24)
-#       define BRT_MASK                                   (0xff << 24)
-
-#define TARGET_AND_CURRENT_PROFILE_INDEX                  0x70c
-#       define TARGET_PROFILE_INDEX_MASK                  (3 << 0)
-#       define TARGET_PROFILE_INDEX_SHIFT                 0
-#       define CURRENT_PROFILE_INDEX_MASK                 (3 << 2)
-#       define CURRENT_PROFILE_INDEX_SHIFT                2
-#       define DYN_PWR_ENTER_INDEX(x)                     ((x) << 4)
-#       define DYN_PWR_ENTER_INDEX_MASK                   (3 << 4)
-#       define DYN_PWR_ENTER_INDEX_SHIFT                  4
-#       define CURR_MCLK_INDEX_MASK                       (3 << 6)
-#       define CURR_MCLK_INDEX_SHIFT                      6
-#       define CURR_SCLK_INDEX_MASK                       (0x1f << 8)
-#       define CURR_SCLK_INDEX_SHIFT                      8
-#       define CURR_VID_INDEX_MASK                        (3 << 13)
-#       define CURR_VID_INDEX_SHIFT                       13
-
-#define VID_UPPER_GPIO_CNTL                               0x740
-#       define CTXSW_UPPER_GPIO_VALUES(x)                 ((x) << 0)
-#       define CTXSW_UPPER_GPIO_VALUES_MASK               (7 << 0)
-#       define HIGH_UPPER_GPIO_VALUES(x)                  ((x) << 3)
-#       define HIGH_UPPER_GPIO_VALUES_MASK                (7 << 3)
-#       define MEDIUM_UPPER_GPIO_VALUES(x)                ((x) << 6)
-#       define MEDIUM_UPPER_GPIO_VALUES_MASK              (7 << 6)
-#       define LOW_UPPER_GPIO_VALUES(x)                   ((x) << 9)
-#       define LOW_UPPER_GPIO_VALUES_MASK                 (7 << 9)
-#       define CTXSW_BACKBIAS_VALUE                       (1 << 12)
-#       define HIGH_BACKBIAS_VALUE                        (1 << 13)
-#       define MEDIUM_BACKBIAS_VALUE                      (1 << 14)
-#       define LOW_BACKBIAS_VALUE                         (1 << 15)
-
-#define CG_DISPLAY_GAP_CNTL                               0x7dc
-#       define DISP1_GAP(x)                               ((x) << 0)
-#       define DISP1_GAP_MASK                             (3 << 0)
-#       define DISP2_GAP(x)                               ((x) << 2)
-#       define DISP2_GAP_MASK                             (3 << 2)
-#       define VBI_TIMER_COUNT(x)                         ((x) << 4)
-#       define VBI_TIMER_COUNT_MASK                       (0x3fff << 4)
-#       define VBI_TIMER_UNIT(x)                          ((x) << 20)
-#       define VBI_TIMER_UNIT_MASK                        (7 << 20)
-#       define DISP1_GAP_MCHG(x)                          ((x) << 24)
-#       define DISP1_GAP_MCHG_MASK                        (3 << 24)
-#       define DISP2_GAP_MCHG(x)                          ((x) << 26)
-#       define DISP2_GAP_MCHG_MASK                        (3 << 26)
-
-#define CG_THERMAL_CTRL                                   0x7f0
-#       define DPM_EVENT_SRC(x)                           ((x) << 0)
-#       define DPM_EVENT_SRC_MASK                         (7 << 0)
-#       define THERM_INC_CLK                              (1 << 3)
-#       define TOFFSET(x)                                 ((x) << 4)
-#       define TOFFSET_MASK                               (0xff << 4)
-#       define DIG_THERM_DPM(x)                           ((x) << 12)
-#       define DIG_THERM_DPM_MASK                         (0xff << 12)
-#       define CTF_SEL(x)                                 ((x) << 20)
-#       define CTF_SEL_MASK                               (7 << 20)
-#       define CTF_PAD_POLARITY                           (1 << 23)
-#       define CTF_PAD_EN                                 (1 << 24)
-
-#define CG_SPLL_SPREAD_SPECTRUM_LOW                       0x820
-#       define SSEN                                       (1 << 0)
-#       define CLKS(x)                                    ((x) << 3)
-#       define CLKS_MASK                                  (0xff << 3)
-#       define CLKS_SHIFT                                 3
-#       define CLKV(x)                                    ((x) << 11)
-#       define CLKV_MASK                                  (0x7ff << 11)
-#       define CLKV_SHIFT                                 11
-#define CG_MPLL_SPREAD_SPECTRUM                           0x830
-
-#define CITF_CNTL					0x200c
-#       define BLACKOUT_RD                              (1 << 0)
-#       define BLACKOUT_WR                              (1 << 1)
-
-#define RAMCFG						0x2408
-#define		NOOFBANK_SHIFT					0
-#define		NOOFBANK_MASK					0x00000001
-#define		NOOFRANK_SHIFT					1
-#define		NOOFRANK_MASK					0x00000002
-#define		NOOFROWS_SHIFT					2
-#define		NOOFROWS_MASK					0x0000001C
-#define		NOOFCOLS_SHIFT					5
-#define		NOOFCOLS_MASK					0x00000060
-#define		CHANSIZE_SHIFT					7
-#define		CHANSIZE_MASK					0x00000080
-#define		BURSTLENGTH_SHIFT				8
-#define		BURSTLENGTH_MASK				0x00000100
-#define		CHANSIZE_OVERRIDE				(1 << 10)
-
-#define SQM_RATIO					0x2424
-#       define STATE0(x)                                ((x) << 0)
-#       define STATE0_MASK                              (0xff << 0)
-#       define STATE1(x)                                ((x) << 8)
-#       define STATE1_MASK                              (0xff << 8)
-#       define STATE2(x)                                ((x) << 16)
-#       define STATE2_MASK                              (0xff << 16)
-#       define STATE3(x)                                ((x) << 24)
-#       define STATE3_MASK                              (0xff << 24)
-
-#define ARB_RFSH_CNTL					0x2460
-#       define ENABLE                                   (1 << 0)
-#define ARB_RFSH_RATE					0x2464
-#       define POWERMODE0(x)                            ((x) << 0)
-#       define POWERMODE0_MASK                          (0xff << 0)
-#       define POWERMODE1(x)                            ((x) << 8)
-#       define POWERMODE1_MASK                          (0xff << 8)
-#       define POWERMODE2(x)                            ((x) << 16)
-#       define POWERMODE2_MASK                          (0xff << 16)
-#       define POWERMODE3(x)                            ((x) << 24)
-#       define POWERMODE3_MASK                          (0xff << 24)
-
-#define MC_SEQ_DRAM					0x2608
-#       define CKE_DYN                                  (1 << 12)
-
-#define MC_SEQ_CMD					0x26c4
-
-#define MC_SEQ_RESERVE_S				0x2890
-#define MC_SEQ_RESERVE_M				0x2894
-
-#define LVTMA_DATA_SYNCHRONIZATION                      0x7adc
-#       define LVTMA_PFREQCHG                           (1 << 8)
-#define DCE3_LVTMA_DATA_SYNCHRONIZATION                 0x7f98
-
-/* PCIE indirect regs */
-#define PCIE_P_CNTL                                       0x40
-#       define P_PLL_PWRDN_IN_L1L23                       (1 << 3)
-#       define P_PLL_BUF_PDNB                             (1 << 4)
-#       define P_PLL_PDNB                                 (1 << 9)
-#       define P_ALLOW_PRX_FRONTEND_SHUTOFF               (1 << 12)
-/* PCIE PORT indirect regs */
-#define PCIE_LC_CNTL                                      0xa0
-#       define LC_L0S_INACTIVITY(x)                       ((x) << 8)
-#       define LC_L0S_INACTIVITY_MASK                     (0xf << 8)
-#       define LC_L0S_INACTIVITY_SHIFT                    8
-#       define LC_L1_INACTIVITY(x)                        ((x) << 12)
-#       define LC_L1_INACTIVITY_MASK                      (0xf << 12)
-#       define LC_L1_INACTIVITY_SHIFT                     12
-#       define LC_PMI_TO_L1_DIS                           (1 << 16)
-#       define LC_ASPM_TO_L1_DIS                          (1 << 24)
-#define PCIE_LC_SPEED_CNTL                                0xa4
-#       define LC_GEN2_EN                                 (1 << 0)
-#       define LC_INITIATE_LINK_SPEED_CHANGE              (1 << 7)
-#       define LC_CURRENT_DATA_RATE                       (1 << 11)
-#       define LC_HW_VOLTAGE_IF_CONTROL(x)                ((x) << 12)
-#       define LC_HW_VOLTAGE_IF_CONTROL_MASK              (3 << 12)
-#       define LC_HW_VOLTAGE_IF_CONTROL_SHIFT             12
-#       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 23)
-#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 24)
-
-#endif
diff --git a/hw/display/rv730d.h b/hw/display/rv730d.h
deleted file mode 100644
index f0a7954fb1..0000000000
--- a/hw/display/rv730d.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef RV730_H
-#define RV730_H
-
-#define	CG_SPLL_FUNC_CNTL				0x600
-#define		SPLL_RESET				(1 << 0)
-#define		SPLL_SLEEP				(1 << 1)
-#define		SPLL_DIVEN				(1 << 2)
-#define		SPLL_BYPASS_EN				(1 << 3)
-#define		SPLL_REF_DIV(x)				((x) << 4)
-#define		SPLL_REF_DIV_MASK			(0x3f << 4)
-#define		SPLL_HILEN(x)				((x) << 12)
-#define		SPLL_HILEN_MASK				(0xf << 12)
-#define		SPLL_LOLEN(x)				((x) << 16)
-#define		SPLL_LOLEN_MASK				(0xf << 16)
-#define	CG_SPLL_FUNC_CNTL_2				0x604
-#define		SCLK_MUX_SEL(x)				((x) << 0)
-#define		SCLK_MUX_SEL_MASK			(0x1ff << 0)
-#define	CG_SPLL_FUNC_CNTL_3				0x608
-#define		SPLL_FB_DIV(x)				((x) << 0)
-#define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)
-#define		SPLL_DITHEN				(1 << 28)
-
-#define	CG_MPLL_FUNC_CNTL				0x624
-#define		MPLL_RESET				(1 << 0)
-#define		MPLL_SLEEP				(1 << 1)
-#define		MPLL_DIVEN				(1 << 2)
-#define		MPLL_BYPASS_EN				(1 << 3)
-#define		MPLL_REF_DIV(x)				((x) << 4)
-#define		MPLL_REF_DIV_MASK			(0x3f << 4)
-#define		MPLL_HILEN(x)				((x) << 12)
-#define		MPLL_HILEN_MASK				(0xf << 12)
-#define		MPLL_LOLEN(x)				((x) << 16)
-#define		MPLL_LOLEN_MASK				(0xf << 16)
-#define	CG_MPLL_FUNC_CNTL_2				0x628
-#define		MCLK_MUX_SEL(x)				((x) << 0)
-#define		MCLK_MUX_SEL_MASK			(0x1ff << 0)
-#define	CG_MPLL_FUNC_CNTL_3				0x62c
-#define		MPLL_FB_DIV(x)				((x) << 0)
-#define		MPLL_FB_DIV_MASK			(0x3ffffff << 0)
-#define		MPLL_DITHEN				(1 << 28)
-
-#define	CG_TCI_MPLL_SPREAD_SPECTRUM			0x634
-#define	CG_TCI_MPLL_SPREAD_SPECTRUM_2			0x638
-#define GENERAL_PWRMGT                                  0x63c
-#       define GLOBAL_PWRMGT_EN                         (1 << 0)
-#       define STATIC_PM_EN                             (1 << 1)
-#       define THERMAL_PROTECTION_DIS                   (1 << 2)
-#       define THERMAL_PROTECTION_TYPE                  (1 << 3)
-#       define ENABLE_GEN2PCIE                          (1 << 4)
-#       define ENABLE_GEN2XSP                           (1 << 5)
-#       define SW_SMIO_INDEX(x)                         ((x) << 6)
-#       define SW_SMIO_INDEX_MASK                       (3 << 6)
-#       define LOW_VOLT_D2_ACPI                         (1 << 8)
-#       define LOW_VOLT_D3_ACPI                         (1 << 9)
-#       define VOLT_PWRMGT_EN                           (1 << 10)
-#       define BACKBIAS_PAD_EN                          (1 << 18)
-#       define BACKBIAS_VALUE                           (1 << 19)
-#       define DYN_SPREAD_SPECTRUM_EN                   (1 << 23)
-#       define AC_DC_SW                                 (1 << 24)
-
-#define SCLK_PWRMGT_CNTL                                  0x644
-#       define SCLK_PWRMGT_OFF                            (1 << 0)
-#       define SCLK_LOW_D1                                (1 << 1)
-#       define FIR_RESET                                  (1 << 4)
-#       define FIR_FORCE_TREND_SEL                        (1 << 5)
-#       define FIR_TREND_MODE                             (1 << 6)
-#       define DYN_GFX_CLK_OFF_EN                         (1 << 7)
-#       define GFX_CLK_FORCE_ON                           (1 << 8)
-#       define GFX_CLK_REQUEST_OFF                        (1 << 9)
-#       define GFX_CLK_FORCE_OFF                          (1 << 10)
-#       define GFX_CLK_OFF_ACPI_D1                        (1 << 11)
-#       define GFX_CLK_OFF_ACPI_D2                        (1 << 12)
-#       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)
-
-#define	TCI_MCLK_PWRMGT_CNTL				0x648
-#       define MPLL_PWRMGT_OFF                          (1 << 5)
-#       define DLL_READY                                (1 << 6)
-#       define MC_INT_CNTL                              (1 << 7)
-#       define MRDCKA_SLEEP                             (1 << 8)
-#       define MRDCKB_SLEEP                             (1 << 9)
-#       define MRDCKC_SLEEP                             (1 << 10)
-#       define MRDCKD_SLEEP                             (1 << 11)
-#       define MRDCKE_SLEEP                             (1 << 12)
-#       define MRDCKF_SLEEP                             (1 << 13)
-#       define MRDCKG_SLEEP                             (1 << 14)
-#       define MRDCKH_SLEEP                             (1 << 15)
-#       define MRDCKA_RESET                             (1 << 16)
-#       define MRDCKB_RESET                             (1 << 17)
-#       define MRDCKC_RESET                             (1 << 18)
-#       define MRDCKD_RESET                             (1 << 19)
-#       define MRDCKE_RESET                             (1 << 20)
-#       define MRDCKF_RESET                             (1 << 21)
-#       define MRDCKG_RESET                             (1 << 22)
-#       define MRDCKH_RESET                             (1 << 23)
-#       define DLL_READY_READ                           (1 << 24)
-#       define USE_DISPLAY_GAP                          (1 << 25)
-#       define USE_DISPLAY_URGENT_NORMAL                (1 << 26)
-#       define MPLL_TURNOFF_D2                          (1 << 28)
-#define	TCI_DLL_CNTL					0x64c
-
-#define	CG_PG_CNTL					0x858
-#       define PWRGATE_ENABLE                           (1 << 0)
-
-#define	CG_AT				                0x6d4
-#define		CG_R(x)					((x) << 0)
-#define		CG_R_MASK				(0xffff << 0)
-#define		CG_L(x)					((x) << 16)
-#define		CG_L_MASK				(0xffff << 16)
-
-#define	CG_SPLL_SPREAD_SPECTRUM				0x790
-#define		SSEN					(1 << 0)
-#define		CLK_S(x)				((x) << 4)
-#define		CLK_S_MASK				(0xfff << 4)
-#define	CG_SPLL_SPREAD_SPECTRUM_2			0x794
-#define		CLK_V(x)				((x) << 0)
-#define		CLK_V_MASK				(0x3ffffff << 0)
-
-#define	MC_ARB_DRAM_TIMING				0x2774
-#define	MC_ARB_DRAM_TIMING2				0x2778
-
-#define	MC_ARB_RFSH_RATE				0x27b0
-#define		POWERMODE0(x)				((x) << 0)
-#define		POWERMODE0_MASK				(0xff << 0)
-#define		POWERMODE1(x)				((x) << 8)
-#define		POWERMODE1_MASK				(0xff << 8)
-#define		POWERMODE2(x)				((x) << 16)
-#define		POWERMODE2_MASK				(0xff << 16)
-#define		POWERMODE3(x)				((x) << 24)
-#define		POWERMODE3_MASK				(0xff << 24)
-
-#define	MC_ARB_DRAM_TIMING_1				0x27f0
-#define	MC_ARB_DRAM_TIMING_2				0x27f4
-#define	MC_ARB_DRAM_TIMING_3				0x27f8
-#define	MC_ARB_DRAM_TIMING2_1				0x27fc
-#define	MC_ARB_DRAM_TIMING2_2				0x2800
-#define	MC_ARB_DRAM_TIMING2_3				0x2804
-
-#define	MC4_IO_DQ_PAD_CNTL_D0_I0			0x2978
-#define	MC4_IO_DQ_PAD_CNTL_D0_I1			0x297c
-#define	MC4_IO_QS_PAD_CNTL_D0_I0			0x2980
-#define	MC4_IO_QS_PAD_CNTL_D0_I1			0x2984
-
-#endif
diff --git a/hw/display/rv740d.h b/hw/display/rv740d.h
deleted file mode 100644
index fe5ab075dc..0000000000
--- a/hw/display/rv740d.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef RV740_H
-#define RV740_H
-
-#define	CG_SPLL_FUNC_CNTL				0x600
-#define		SPLL_RESET				(1 << 0)
-#define		SPLL_SLEEP				(1 << 1)
-#define		SPLL_BYPASS_EN				(1 << 3)
-#define		SPLL_REF_DIV(x)				((x) << 4)
-#define		SPLL_REF_DIV_MASK			(0x3f << 4)
-#define		SPLL_PDIV_A(x)				((x) << 20)
-#define		SPLL_PDIV_A_MASK			(0x7f << 20)
-#define	CG_SPLL_FUNC_CNTL_2				0x604
-#define		SCLK_MUX_SEL(x)				((x) << 0)
-#define		SCLK_MUX_SEL_MASK			(0x1ff << 0)
-#define	CG_SPLL_FUNC_CNTL_3				0x608
-#define		SPLL_FB_DIV(x)				((x) << 0)
-#define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)
-#define		SPLL_DITHEN				(1 << 28)
-
-#define	MPLL_CNTL_MODE					0x61c
-#define		SS_SSEN					(1 << 24)
-
-#define	MPLL_AD_FUNC_CNTL				0x624
-#define		CLKF(x)					((x) << 0)
-#define		CLKF_MASK				(0x7f << 0)
-#define		CLKR(x)					((x) << 7)
-#define		CLKR_MASK				(0x1f << 7)
-#define		CLKFRAC(x)				((x) << 12)
-#define		CLKFRAC_MASK				(0x1f << 12)
-#define		YCLK_POST_DIV(x)			((x) << 17)
-#define		YCLK_POST_DIV_MASK			(3 << 17)
-#define		IBIAS(x)				((x) << 20)
-#define		IBIAS_MASK				(0x3ff << 20)
-#define		RESET					(1 << 30)
-#define		PDNB					(1 << 31)
-#define	MPLL_AD_FUNC_CNTL_2				0x628
-#define		BYPASS					(1 << 19)
-#define		BIAS_GEN_PDNB				(1 << 24)
-#define		RESET_EN				(1 << 25)
-#define		VCO_MODE				(1 << 29)
-#define	MPLL_DQ_FUNC_CNTL				0x62c
-#define	MPLL_DQ_FUNC_CNTL_2				0x630
-
-#define	MCLK_PWRMGT_CNTL				0x648
-#define		DLL_SPEED(x)				((x) << 0)
-#define		DLL_SPEED_MASK				(0x1f << 0)
-#       define MPLL_PWRMGT_OFF                          (1 << 5)
-#       define DLL_READY                                (1 << 6)
-#       define MC_INT_CNTL                              (1 << 7)
-#       define MRDCKA0_SLEEP                            (1 << 8)
-#       define MRDCKA1_SLEEP                            (1 << 9)
-#       define MRDCKB0_SLEEP                            (1 << 10)
-#       define MRDCKB1_SLEEP                            (1 << 11)
-#       define MRDCKC0_SLEEP                            (1 << 12)
-#       define MRDCKC1_SLEEP                            (1 << 13)
-#       define MRDCKD0_SLEEP                            (1 << 14)
-#       define MRDCKD1_SLEEP                            (1 << 15)
-#       define MRDCKA0_RESET                            (1 << 16)
-#       define MRDCKA1_RESET                            (1 << 17)
-#       define MRDCKB0_RESET                            (1 << 18)
-#       define MRDCKB1_RESET                            (1 << 19)
-#       define MRDCKC0_RESET                            (1 << 20)
-#       define MRDCKC1_RESET                            (1 << 21)
-#       define MRDCKD0_RESET                            (1 << 22)
-#       define MRDCKD1_RESET                            (1 << 23)
-#       define DLL_READY_READ                           (1 << 24)
-#       define USE_DISPLAY_GAP                          (1 << 25)
-#       define USE_DISPLAY_URGENT_NORMAL                (1 << 26)
-#       define MPLL_TURNOFF_D2                          (1 << 28)
-#define	DLL_CNTL					0x64c
-#       define MRDCKA0_BYPASS                           (1 << 24)
-#       define MRDCKA1_BYPASS                           (1 << 25)
-#       define MRDCKB0_BYPASS                           (1 << 26)
-#       define MRDCKB1_BYPASS                           (1 << 27)
-#       define MRDCKC0_BYPASS                           (1 << 28)
-#       define MRDCKC1_BYPASS                           (1 << 29)
-#       define MRDCKD0_BYPASS                           (1 << 30)
-#       define MRDCKD1_BYPASS                           (1 << 31)
-
-#define	CG_SPLL_SPREAD_SPECTRUM				0x790
-#define		SSEN					(1 << 0)
-#define		CLK_S(x)				((x) << 4)
-#define		CLK_S_MASK				(0xfff << 4)
-#define	CG_SPLL_SPREAD_SPECTRUM_2			0x794
-#define		CLK_V(x)				((x) << 0)
-#define		CLK_V_MASK				(0x3ffffff << 0)
-
-#define	MPLL_SS1					0x85c
-#define		CLKV(x)					((x) << 0)
-#define		CLKV_MASK				(0x3ffffff << 0)
-#define	MPLL_SS2					0x860
-#define		CLKS(x)					((x) << 0)
-#define		CLKS_MASK				(0xfff << 0)
-
-#endif
diff --git a/hw/display/rv770_dpm.h b/hw/display/rv770_dpm.h
deleted file mode 100644
index d81ccf153c..0000000000
--- a/hw/display/rv770_dpm.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __RV770_DPM_H__
-#define __RV770_DPM_H__
-
-#include "radeon.h"
-#include "rv770_smc.h"
-
-struct rv770_clock_registers {
-	u32 cg_spll_func_cntl;
-	u32 cg_spll_func_cntl_2;
-	u32 cg_spll_func_cntl_3;
-	u32 cg_spll_spread_spectrum;
-	u32 cg_spll_spread_spectrum_2;
-	u32 mpll_ad_func_cntl;
-	u32 mpll_ad_func_cntl_2;
-	u32 mpll_dq_func_cntl;
-	u32 mpll_dq_func_cntl_2;
-	u32 mclk_pwrmgt_cntl;
-	u32 dll_cntl;
-	u32 mpll_ss1;
-	u32 mpll_ss2;
-};
-
-struct rv730_clock_registers {
-	u32 cg_spll_func_cntl;
-	u32 cg_spll_func_cntl_2;
-	u32 cg_spll_func_cntl_3;
-	u32 cg_spll_spread_spectrum;
-	u32 cg_spll_spread_spectrum_2;
-	u32 mclk_pwrmgt_cntl;
-	u32 dll_cntl;
-	u32 mpll_func_cntl;
-	u32 mpll_func_cntl2;
-	u32 mpll_func_cntl3;
-	u32 mpll_ss;
-	u32 mpll_ss2;
-};
-
-union r7xx_clock_registers {
-	struct rv770_clock_registers rv770;
-	struct rv730_clock_registers rv730;
-};
-
-struct vddc_table_entry {
-	u16 vddc;
-	u8 vddc_index;
-	u8 high_smio;
-	u32 low_smio;
-};
-
-#define MAX_NO_OF_MVDD_VALUES 2
-#define MAX_NO_VREG_STEPS 32
-
-struct rv7xx_power_info {
-	/* flags */
-	bool mem_gddr5;
-	bool pcie_gen2;
-	bool dynamic_pcie_gen2;
-	bool acpi_pcie_gen2;
-	bool boot_in_gen2;
-	bool voltage_control; /* vddc */
-	bool mvdd_control;
-	bool sclk_ss;
-	bool mclk_ss;
-	bool dynamic_ss;
-	bool gfx_clock_gating;
-	bool mg_clock_gating;
-	bool mgcgtssm;
-	bool power_gating;
-	bool thermal_protection;
-	bool display_gap;
-	bool dcodt;
-	bool ulps;
-	/* registers */
-	union r7xx_clock_registers clk_regs;
-	u32 s0_vid_lower_smio_cntl;
-	/* voltage */
-	u32 vddc_mask_low;
-	u32 mvdd_mask_low;
-	u32 mvdd_split_frequency;
-	u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
-	u16 max_vddc;
-	u16 max_vddc_in_table;
-	u16 min_vddc_in_table;
-	struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
-	u8 valid_vddc_entries;
-	/* dc odt */
-	u32 mclk_odt_threshold;
-	u8 odt_value_0[2];
-	u8 odt_value_1[2];
-	/* stored values */
-	u32 boot_sclk;
-	u16 acpi_vddc;
-	u32 ref_div;
-	u32 active_auto_throttle_sources;
-	u32 mclk_stutter_mode_threshold;
-	u32 mclk_strobe_mode_threshold;
-	u32 mclk_edc_enable_threshold;
-	u32 bsp;
-	u32 bsu;
-	u32 pbsp;
-	u32 pbsu;
-	u32 dsp;
-	u32 psp;
-	u32 asi;
-	u32 pasi;
-	u32 vrc;
-	u32 restricted_levels;
-	u32 rlp;
-	u32 rmp;
-	u32 lhp;
-	u32 lmp;
-	/* smc offsets */
-	u16 state_table_start;
-	u16 soft_regs_start;
-	u16 sram_end;
-	/* scratch structs */
-	RV770_SMC_STATETABLE smc_statetable;
-};
-
-struct rv7xx_pl {
-	u32 sclk;
-	u32 mclk;
-	u16 vddc;
-	u16 vddci; /* eg+ only */
-	u32 flags;
-	enum radeon_pcie_gen pcie_gen; /* si+ only */
-};
-
-struct rv7xx_ps {
-	struct rv7xx_pl high;
-	struct rv7xx_pl medium;
-	struct rv7xx_pl low;
-	bool dc_compatible;
-};
-
-#define RV770_RLP_DFLT                                10
-#define RV770_RMP_DFLT                                25
-#define RV770_LHP_DFLT                                25
-#define RV770_LMP_DFLT                                10
-#define RV770_VRC_DFLT                                0x003f
-#define RV770_ASI_DFLT                                1000
-#define RV770_HASI_DFLT                               200000
-#define RV770_MGCGTTLOCAL0_DFLT                       0x00100000
-#define RV7XX_MGCGTTLOCAL0_DFLT                       0
-#define RV770_MGCGTTLOCAL1_DFLT                       0xFFFF0000
-#define RV770_MGCGCGTSSMCTRL_DFLT                     0x55940000
-
-#define MVDD_LOW_INDEX  0
-#define MVDD_HIGH_INDEX 1
-
-#define MVDD_LOW_VALUE  0
-#define MVDD_HIGH_VALUE 0xffff
-
-#define RV770_DEFAULT_VCLK_FREQ  53300 /* 10 khz */
-#define RV770_DEFAULT_DCLK_FREQ  40000 /* 10 khz */
-
-/* rv730/rv710 */
-int rv730_populate_sclk_value(struct radeon_device *rdev,
-			      u32 engine_clock,
-			      RV770_SMC_SCLK_VALUE *sclk);
-int rv730_populate_mclk_value(struct radeon_device *rdev,
-			      u32 engine_clock, u32 memory_clock,
-			      LPRV7XX_SMC_MCLK_VALUE mclk);
-void rv730_read_clock_registers(struct radeon_device *rdev);
-int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
-				  RV770_SMC_STATETABLE *table);
-int rv730_populate_smc_initial_state(struct radeon_device *rdev,
-				     struct radeon_ps *radeon_initial_state,
-				     RV770_SMC_STATETABLE *table);
-void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
-					    struct radeon_ps *radeon_state);
-void rv730_power_gating_enable(struct radeon_device *rdev,
-			       bool enable);
-void rv730_start_dpm(struct radeon_device *rdev);
-void rv730_stop_dpm(struct radeon_device *rdev);
-void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt);
-void rv730_get_odt_values(struct radeon_device *rdev);
-
-/* rv740 */
-int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
-			      RV770_SMC_SCLK_VALUE *sclk);
-int rv740_populate_mclk_value(struct radeon_device *rdev,
-			      u32 engine_clock, u32 memory_clock,
-			      RV7XX_SMC_MCLK_VALUE *mclk);
-void rv740_read_clock_registers(struct radeon_device *rdev);
-int rv740_populate_smc_acpi_state(struct radeon_device *rdev,
-				  RV770_SMC_STATETABLE *table);
-void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev,
-				       bool enable);
-u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
-u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
-u32 rv740_get_decoded_reference_divider(u32 encoded_ref);
-
-/* rv770 */
-u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);
-int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
-			      RV770_SMC_VOLTAGE_VALUE *voltage);
-int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
-			      RV770_SMC_VOLTAGE_VALUE *voltage);
-u8 rv770_get_seq_value(struct radeon_device *rdev,
-		       struct rv7xx_pl *pl);
-int rv770_populate_initial_mvdd_value(struct radeon_device *rdev,
-				      RV770_SMC_VOLTAGE_VALUE *voltage);
-u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
-					u32 engine_clock);
-void rv770_program_response_times(struct radeon_device *rdev);
-int rv770_populate_smc_sp(struct radeon_device *rdev,
-			  struct radeon_ps *radeon_state,
-			  RV770_SMC_SWSTATE *smc_state);
-int rv770_populate_smc_t(struct radeon_device *rdev,
-			 struct radeon_ps *radeon_state,
-			 RV770_SMC_SWSTATE *smc_state);
-void rv770_read_voltage_smio_registers(struct radeon_device *rdev);
-void rv770_get_memory_type(struct radeon_device *rdev);
-void r7xx_start_smc(struct radeon_device *rdev);
-u8 rv770_get_memory_module_index(struct radeon_device *rdev);
-void rv770_get_max_vddc(struct radeon_device *rdev);
-void rv770_get_pcie_gen2_status(struct radeon_device *rdev);
-void rv770_enable_acpi_pm(struct radeon_device *rdev);
-void rv770_restore_cgcg(struct radeon_device *rdev);
-bool rv770_dpm_enabled(struct radeon_device *rdev);
-void rv770_enable_voltage_control(struct radeon_device *rdev,
-				  bool enable);
-void rv770_enable_backbias(struct radeon_device *rdev,
-			   bool enable);
-void rv770_enable_thermal_protection(struct radeon_device *rdev,
-				     bool enable);
-void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
-				       enum radeon_dpm_auto_throttle_src source,
-				       bool enable);
-void rv770_setup_bsp(struct radeon_device *rdev);
-void rv770_program_git(struct radeon_device *rdev);
-void rv770_program_tp(struct radeon_device *rdev);
-void rv770_program_tpp(struct radeon_device *rdev);
-void rv770_program_sstp(struct radeon_device *rdev);
-void rv770_program_engine_speed_parameters(struct radeon_device *rdev);
-void rv770_program_vc(struct radeon_device *rdev);
-void rv770_clear_vc(struct radeon_device *rdev);
-int rv770_upload_firmware(struct radeon_device *rdev);
-void rv770_stop_dpm(struct radeon_device *rdev);
-void r7xx_stop_smc(struct radeon_device *rdev);
-void rv770_reset_smio_status(struct radeon_device *rdev);
-int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev);
-int rv770_dpm_force_performance_level(struct radeon_device *rdev,
-				      enum radeon_dpm_forced_level level);
-int rv770_halt_smc(struct radeon_device *rdev);
-int rv770_resume_smc(struct radeon_device *rdev);
-int rv770_set_sw_state(struct radeon_device *rdev);
-int rv770_set_boot_state(struct radeon_device *rdev);
-int rv7xx_parse_power_table(struct radeon_device *rdev);
-void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
-					      struct radeon_ps *new_ps,
-					      struct radeon_ps *old_ps);
-void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
-					     struct radeon_ps *new_ps,
-					     struct radeon_ps *old_ps);
-void rv770_get_engine_memory_ss(struct radeon_device *rdev);
-
-/* smc */
-int rv770_write_smc_soft_register(struct radeon_device *rdev,
-				  u16 reg_offset, u32 value);
-
-#endif
diff --git a/hw/display/rv770_smc.h b/hw/display/rv770_smc.h
deleted file mode 100644
index 3b2c963c48..0000000000
--- a/hw/display/rv770_smc.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __RV770_SMC_H__
-#define __RV770_SMC_H__
-
-#include "ppsmc.h"
-
-#pragma pack(push, 1)
-
-#define RV770_SMC_TABLE_ADDRESS 0xB000
-
-#define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE    3
-
-struct RV770_SMC_SCLK_VALUE
-{
-    uint32_t        vCG_SPLL_FUNC_CNTL;
-    uint32_t        vCG_SPLL_FUNC_CNTL_2;
-    uint32_t        vCG_SPLL_FUNC_CNTL_3;
-    uint32_t        vCG_SPLL_SPREAD_SPECTRUM;
-    uint32_t        vCG_SPLL_SPREAD_SPECTRUM_2;
-    uint32_t        sclk_value;
-};
-
-typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE;
-
-struct RV770_SMC_MCLK_VALUE
-{
-    uint32_t        vMPLL_AD_FUNC_CNTL;
-    uint32_t        vMPLL_AD_FUNC_CNTL_2;
-    uint32_t        vMPLL_DQ_FUNC_CNTL;
-    uint32_t        vMPLL_DQ_FUNC_CNTL_2;
-    uint32_t        vMCLK_PWRMGT_CNTL;
-    uint32_t        vDLL_CNTL;
-    uint32_t        vMPLL_SS;
-    uint32_t        vMPLL_SS2;
-    uint32_t        mclk_value;
-};
-
-typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE;
-
-
-struct RV730_SMC_MCLK_VALUE
-{
-    uint32_t        vMCLK_PWRMGT_CNTL;
-    uint32_t        vDLL_CNTL;
-    uint32_t        vMPLL_FUNC_CNTL;
-    uint32_t        vMPLL_FUNC_CNTL2;
-    uint32_t        vMPLL_FUNC_CNTL3;
-    uint32_t        vMPLL_SS;
-    uint32_t        vMPLL_SS2;
-    uint32_t        mclk_value;
-};
-
-typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE;
-
-struct RV770_SMC_VOLTAGE_VALUE
-{
-    uint16_t             value;
-    uint8_t              index;
-    uint8_t              padding;
-};
-
-typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE;
-
-union RV7XX_SMC_MCLK_VALUE
-{
-    RV770_SMC_MCLK_VALUE    mclk770;
-    RV730_SMC_MCLK_VALUE    mclk730;
-};
-
-typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE;
-
-struct RV770_SMC_HW_PERFORMANCE_LEVEL
-{
-    uint8_t                 arbValue;
-    union{
-        uint8_t             seqValue;
-        uint8_t             ACIndex;
-    };
-    uint8_t                 displayWatermark;
-    uint8_t                 gen2PCIE;
-    uint8_t                 gen2XSP;
-    uint8_t                 backbias;
-    uint8_t                 strobeMode;
-    uint8_t                 mcFlags;
-    uint32_t                aT;
-    uint32_t                bSP;
-    RV770_SMC_SCLK_VALUE    sclk;
-    RV7XX_SMC_MCLK_VALUE    mclk;
-    RV770_SMC_VOLTAGE_VALUE vddc;
-    RV770_SMC_VOLTAGE_VALUE mvdd;
-    RV770_SMC_VOLTAGE_VALUE vddci;
-    uint8_t                 reserved1;
-    uint8_t                 reserved2;
-    uint8_t                 stateFlags;
-    uint8_t                 padding;
-};
-
-#define SMC_STROBE_RATIO    0x0F
-#define SMC_STROBE_ENABLE   0x10
-
-#define SMC_MC_EDC_RD_FLAG  0x01
-#define SMC_MC_EDC_WR_FLAG  0x02
-#define SMC_MC_RTT_ENABLE   0x04
-#define SMC_MC_STUTTER_EN   0x08
-
-typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL;
-
-struct RV770_SMC_SWSTATE
-{
-    uint8_t           flags;
-    uint8_t           padding1;
-    uint8_t           padding2;
-    uint8_t           padding3;
-    RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
-};
-
-typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE;
-
-#define RV770_SMC_VOLTAGEMASK_VDDC 0
-#define RV770_SMC_VOLTAGEMASK_MVDD 1
-#define RV770_SMC_VOLTAGEMASK_VDDCI 2
-#define RV770_SMC_VOLTAGEMASK_MAX  4
-
-struct RV770_SMC_VOLTAGEMASKTABLE
-{
-    uint8_t  highMask[RV770_SMC_VOLTAGEMASK_MAX];
-    uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX];
-};
-
-typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE;
-
-#define MAX_NO_VREG_STEPS 32
-
-struct RV770_SMC_STATETABLE
-{
-    uint8_t             thermalProtectType;
-    uint8_t             systemFlags;
-    uint8_t             maxVDDCIndexInPPTable;
-    uint8_t             extraFlags;
-    uint8_t             highSMIO[MAX_NO_VREG_STEPS];
-    uint32_t            lowSMIO[MAX_NO_VREG_STEPS];
-    RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable;
-    RV770_SMC_SWSTATE   initialState;
-    RV770_SMC_SWSTATE   ACPIState;
-    RV770_SMC_SWSTATE   driverState;
-    RV770_SMC_SWSTATE   ULVState;
-};
-
-typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE;
-
-#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
-
-#pragma pack(pop)
-
-#define RV770_SMC_SOFT_REGISTERS_START        0x104
-
-#define RV770_SMC_SOFT_REGISTER_mclk_chg_timeout        0x0
-#define RV770_SMC_SOFT_REGISTER_baby_step_timer         0x8
-#define RV770_SMC_SOFT_REGISTER_delay_bbias             0xC
-#define RV770_SMC_SOFT_REGISTER_delay_vreg              0x10
-#define RV770_SMC_SOFT_REGISTER_delay_acpi              0x2C
-#define RV770_SMC_SOFT_REGISTER_seq_index               0x64
-#define RV770_SMC_SOFT_REGISTER_mvdd_chg_time           0x68
-#define RV770_SMC_SOFT_REGISTER_mclk_switch_lim         0x78
-#define RV770_SMC_SOFT_REGISTER_mc_block_delay          0x90
-#define RV770_SMC_SOFT_REGISTER_uvd_enabled             0x9C
-#define RV770_SMC_SOFT_REGISTER_is_asic_lombok          0xA0
-
-int rv770_copy_bytes_to_smc(struct radeon_device *rdev,
-			    u16 smc_start_address, const u8 *src,
-			    u16 byte_count, u16 limit);
-void rv770_start_smc(struct radeon_device *rdev);
-void rv770_reset_smc(struct radeon_device *rdev);
-void rv770_stop_smc_clock(struct radeon_device *rdev);
-void rv770_start_smc_clock(struct radeon_device *rdev);
-bool rv770_is_smc_running(struct radeon_device *rdev);
-PPSMC_Result rv770_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
-PPSMC_Result rv770_wait_for_smc_inactive(struct radeon_device *rdev);
-int rv770_read_smc_sram_dword(struct radeon_device *rdev,
-			      u16 smc_address, u32 *value, u16 limit);
-int rv770_write_smc_sram_dword(struct radeon_device *rdev,
-			       u16 smc_address, u32 value, u16 limit);
-int rv770_load_smc_ucode(struct radeon_device *rdev,
-			 u16 limit);
-
-#endif
diff --git a/hw/display/rv770d.h b/hw/display/rv770d.h
deleted file mode 100644
index 0271f4c559..0000000000
--- a/hw/display/rv770d.h
+++ /dev/null
@@ -1,1015 +0,0 @@
-/*
- * Copyright 2009 Advanced Micro Devices, Inc.
- * Copyright 2009 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef RV770_H
-#define RV770_H
-
-#define R7XX_MAX_SH_GPRS           256
-#define R7XX_MAX_TEMP_GPRS         16
-#define R7XX_MAX_SH_THREADS        256
-#define R7XX_MAX_SH_STACK_ENTRIES  4096
-#define R7XX_MAX_BACKENDS          8
-#define R7XX_MAX_BACKENDS_MASK     0xff
-#define R7XX_MAX_SIMDS             16
-#define R7XX_MAX_SIMDS_MASK        0xffff
-#define R7XX_MAX_PIPES             8
-#define R7XX_MAX_PIPES_MASK        0xff
-
-/* discrete uvd clocks */
-#define CG_UPLL_FUNC_CNTL				0x718
-#	define UPLL_RESET_MASK				0x00000001
-#	define UPLL_SLEEP_MASK				0x00000002
-#	define UPLL_BYPASS_EN_MASK			0x00000004
-#	define UPLL_CTLREQ_MASK				0x00000008
-#	define UPLL_REF_DIV(x)				((x) << 16)
-#	define UPLL_REF_DIV_MASK			0x003F0000
-#	define UPLL_CTLACK_MASK				0x40000000
-#	define UPLL_CTLACK2_MASK			0x80000000
-#define CG_UPLL_FUNC_CNTL_2				0x71c
-#	define UPLL_SW_HILEN(x)				((x) << 0)
-#	define UPLL_SW_LOLEN(x)				((x) << 4)
-#	define UPLL_SW_HILEN2(x)			((x) << 8)
-#	define UPLL_SW_LOLEN2(x)			((x) << 12)
-#	define UPLL_SW_MASK				0x0000FFFF
-#	define VCLK_SRC_SEL(x)				((x) << 20)
-#	define VCLK_SRC_SEL_MASK			0x01F00000
-#	define DCLK_SRC_SEL(x)				((x) << 25)
-#	define DCLK_SRC_SEL_MASK			0x3E000000
-#define CG_UPLL_FUNC_CNTL_3				0x720
-#	define UPLL_FB_DIV(x)				((x) << 0)
-#	define UPLL_FB_DIV_MASK				0x01FFFFFF
-
-/* pm registers */
-#define	SMC_SRAM_ADDR					0x200
-#define		SMC_SRAM_AUTO_INC_DIS				(1 << 16)
-#define	SMC_SRAM_DATA					0x204
-#define	SMC_IO						0x208
-#define		SMC_RST_N					(1 << 0)
-#define		SMC_STOP_MODE					(1 << 2)
-#define		SMC_CLK_EN					(1 << 11)
-#define	SMC_MSG						0x20c
-#define		HOST_SMC_MSG(x)					((x) << 0)
-#define		HOST_SMC_MSG_MASK				(0xff << 0)
-#define		HOST_SMC_MSG_SHIFT				0
-#define		HOST_SMC_RESP(x)				((x) << 8)
-#define		HOST_SMC_RESP_MASK				(0xff << 8)
-#define		HOST_SMC_RESP_SHIFT				8
-#define		SMC_HOST_MSG(x)					((x) << 16)
-#define		SMC_HOST_MSG_MASK				(0xff << 16)
-#define		SMC_HOST_MSG_SHIFT				16
-#define		SMC_HOST_RESP(x)				((x) << 24)
-#define		SMC_HOST_RESP_MASK				(0xff << 24)
-#define		SMC_HOST_RESP_SHIFT				24
-
-#define	SMC_ISR_FFD8_FFDB				0x218
-
-#define	CG_SPLL_FUNC_CNTL				0x600
-#define		SPLL_RESET				(1 << 0)
-#define		SPLL_SLEEP				(1 << 1)
-#define		SPLL_DIVEN				(1 << 2)
-#define		SPLL_BYPASS_EN				(1 << 3)
-#define		SPLL_REF_DIV(x)				((x) << 4)
-#define		SPLL_REF_DIV_MASK			(0x3f << 4)
-#define		SPLL_HILEN(x)				((x) << 12)
-#define		SPLL_HILEN_MASK				(0xf << 12)
-#define		SPLL_LOLEN(x)				((x) << 16)
-#define		SPLL_LOLEN_MASK				(0xf << 16)
-#define	CG_SPLL_FUNC_CNTL_2				0x604
-#define		SCLK_MUX_SEL(x)				((x) << 0)
-#define		SCLK_MUX_SEL_MASK			(0x1ff << 0)
-#define		SCLK_MUX_UPDATE				(1 << 26)
-#define	CG_SPLL_FUNC_CNTL_3				0x608
-#define		SPLL_FB_DIV(x)				((x) << 0)
-#define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)
-#define		SPLL_DITHEN				(1 << 28)
-#define	CG_SPLL_STATUS					0x60c
-#define		SPLL_CHG_STATUS				(1 << 1)
-
-#define	SPLL_CNTL_MODE					0x610
-#define		SPLL_DIV_SYNC				(1 << 5)
-
-#define MPLL_CNTL_MODE                                  0x61c
-#       define MPLL_MCLK_SEL                            (1 << 11)
-#       define RV730_MPLL_MCLK_SEL                      (1 << 25)
-
-#define	MPLL_AD_FUNC_CNTL				0x624
-#define		CLKF(x)					((x) << 0)
-#define		CLKF_MASK				(0x7f << 0)
-#define		CLKR(x)					((x) << 7)
-#define		CLKR_MASK				(0x1f << 7)
-#define		CLKFRAC(x)				((x) << 12)
-#define		CLKFRAC_MASK				(0x1f << 12)
-#define		YCLK_POST_DIV(x)			((x) << 17)
-#define		YCLK_POST_DIV_MASK			(3 << 17)
-#define		IBIAS(x)				((x) << 20)
-#define		IBIAS_MASK				(0x3ff << 20)
-#define		RESET					(1 << 30)
-#define		PDNB					(1 << 31)
-#define	MPLL_AD_FUNC_CNTL_2				0x628
-#define		BYPASS					(1 << 19)
-#define		BIAS_GEN_PDNB				(1 << 24)
-#define		RESET_EN				(1 << 25)
-#define		VCO_MODE				(1 << 29)
-#define	MPLL_DQ_FUNC_CNTL				0x62c
-#define	MPLL_DQ_FUNC_CNTL_2				0x630
-
-#define GENERAL_PWRMGT                                  0x63c
-#       define GLOBAL_PWRMGT_EN                         (1 << 0)
-#       define STATIC_PM_EN                             (1 << 1)
-#       define THERMAL_PROTECTION_DIS                   (1 << 2)
-#       define THERMAL_PROTECTION_TYPE                  (1 << 3)
-#       define ENABLE_GEN2PCIE                          (1 << 4)
-#       define ENABLE_GEN2XSP                           (1 << 5)
-#       define SW_SMIO_INDEX(x)                         ((x) << 6)
-#       define SW_SMIO_INDEX_MASK                       (3 << 6)
-#       define SW_SMIO_INDEX_SHIFT                      6
-#       define LOW_VOLT_D2_ACPI                         (1 << 8)
-#       define LOW_VOLT_D3_ACPI                         (1 << 9)
-#       define VOLT_PWRMGT_EN                           (1 << 10)
-#       define BACKBIAS_PAD_EN                          (1 << 18)
-#       define BACKBIAS_VALUE                           (1 << 19)
-#       define DYN_SPREAD_SPECTRUM_EN                   (1 << 23)
-#       define AC_DC_SW                                 (1 << 24)
-
-#define CG_TPC                                            0x640
-#define SCLK_PWRMGT_CNTL                                  0x644
-#       define SCLK_PWRMGT_OFF                            (1 << 0)
-#       define SCLK_LOW_D1                                (1 << 1)
-#       define FIR_RESET                                  (1 << 4)
-#       define FIR_FORCE_TREND_SEL                        (1 << 5)
-#       define FIR_TREND_MODE                             (1 << 6)
-#       define DYN_GFX_CLK_OFF_EN                         (1 << 7)
-#       define GFX_CLK_FORCE_ON                           (1 << 8)
-#       define GFX_CLK_REQUEST_OFF                        (1 << 9)
-#       define GFX_CLK_FORCE_OFF                          (1 << 10)
-#       define GFX_CLK_OFF_ACPI_D1                        (1 << 11)
-#       define GFX_CLK_OFF_ACPI_D2                        (1 << 12)
-#       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)
-#define	MCLK_PWRMGT_CNTL				0x648
-#       define DLL_SPEED(x)				((x) << 0)
-#       define DLL_SPEED_MASK				(0x1f << 0)
-#       define MPLL_PWRMGT_OFF                          (1 << 5)
-#       define DLL_READY                                (1 << 6)
-#       define MC_INT_CNTL                              (1 << 7)
-#       define MRDCKA0_SLEEP                            (1 << 8)
-#       define MRDCKA1_SLEEP                            (1 << 9)
-#       define MRDCKB0_SLEEP                            (1 << 10)
-#       define MRDCKB1_SLEEP                            (1 << 11)
-#       define MRDCKC0_SLEEP                            (1 << 12)
-#       define MRDCKC1_SLEEP                            (1 << 13)
-#       define MRDCKD0_SLEEP                            (1 << 14)
-#       define MRDCKD1_SLEEP                            (1 << 15)
-#       define MRDCKA0_RESET                            (1 << 16)
-#       define MRDCKA1_RESET                            (1 << 17)
-#       define MRDCKB0_RESET                            (1 << 18)
-#       define MRDCKB1_RESET                            (1 << 19)
-#       define MRDCKC0_RESET                            (1 << 20)
-#       define MRDCKC1_RESET                            (1 << 21)
-#       define MRDCKD0_RESET                            (1 << 22)
-#       define MRDCKD1_RESET                            (1 << 23)
-#       define DLL_READY_READ                           (1 << 24)
-#       define USE_DISPLAY_GAP                          (1 << 25)
-#       define USE_DISPLAY_URGENT_NORMAL                (1 << 26)
-#       define MPLL_TURNOFF_D2                          (1 << 28)
-#define	DLL_CNTL					0x64c
-#       define MRDCKA0_BYPASS                           (1 << 24)
-#       define MRDCKA1_BYPASS                           (1 << 25)
-#       define MRDCKB0_BYPASS                           (1 << 26)
-#       define MRDCKB1_BYPASS                           (1 << 27)
-#       define MRDCKC0_BYPASS                           (1 << 28)
-#       define MRDCKC1_BYPASS                           (1 << 29)
-#       define MRDCKD0_BYPASS                           (1 << 30)
-#       define MRDCKD1_BYPASS                           (1 << 31)
-
-#define MPLL_TIME                                         0x654
-#       define MPLL_LOCK_TIME(x)			((x) << 0)
-#       define MPLL_LOCK_TIME_MASK			(0xffff << 0)
-#       define MPLL_RESET_TIME(x)			((x) << 16)
-#       define MPLL_RESET_TIME_MASK			(0xffff << 16)
-
-#define CG_CLKPIN_CNTL                                    0x660
-#       define MUX_TCLK_TO_XCLK                           (1 << 8)
-#       define XTALIN_DIVIDE                              (1 << 9)
-
-#define TARGET_AND_CURRENT_PROFILE_INDEX                  0x66c
-#       define CURRENT_PROFILE_INDEX_MASK                 (0xf << 4)
-#       define CURRENT_PROFILE_INDEX_SHIFT                4
-
-#define S0_VID_LOWER_SMIO_CNTL                            0x678
-#define S1_VID_LOWER_SMIO_CNTL                            0x67c
-#define S2_VID_LOWER_SMIO_CNTL                            0x680
-#define S3_VID_LOWER_SMIO_CNTL                            0x684
-
-#define CG_FTV                                            0x690
-#define CG_FFCT_0                                         0x694
-#       define UTC_0(x)                                   ((x) << 0)
-#       define UTC_0_MASK                                 (0x3ff << 0)
-#       define DTC_0(x)                                   ((x) << 10)
-#       define DTC_0_MASK                                 (0x3ff << 10)
-
-#define CG_BSP                                          0x6d0
-#       define BSP(x)					((x) << 0)
-#       define BSP_MASK					(0xffff << 0)
-#       define BSU(x)					((x) << 16)
-#       define BSU_MASK					(0xf << 16)
-#define CG_AT                                           0x6d4
-#       define CG_R(x)					((x) << 0)
-#       define CG_R_MASK				(0xffff << 0)
-#       define CG_L(x)					((x) << 16)
-#       define CG_L_MASK				(0xffff << 16)
-#define CG_GIT                                          0x6d8
-#       define CG_GICST(x)                              ((x) << 0)
-#       define CG_GICST_MASK                            (0xffff << 0)
-#       define CG_GIPOT(x)                              ((x) << 16)
-#       define CG_GIPOT_MASK                            (0xffff << 16)
-
-#define CG_SSP                                            0x6e8
-#       define SST(x)                                     ((x) << 0)
-#       define SST_MASK                                   (0xffff << 0)
-#       define SSTU(x)                                    ((x) << 16)
-#       define SSTU_MASK                                  (0xf << 16)
-
-#define CG_DISPLAY_GAP_CNTL                               0x714
-#       define DISP1_GAP(x)                               ((x) << 0)
-#       define DISP1_GAP_MASK                             (3 << 0)
-#       define DISP2_GAP(x)                               ((x) << 2)
-#       define DISP2_GAP_MASK                             (3 << 2)
-#       define VBI_TIMER_COUNT(x)                         ((x) << 4)
-#       define VBI_TIMER_COUNT_MASK                       (0x3fff << 4)
-#       define VBI_TIMER_UNIT(x)                          ((x) << 20)
-#       define VBI_TIMER_UNIT_MASK                        (7 << 20)
-#       define DISP1_GAP_MCHG(x)                          ((x) << 24)
-#       define DISP1_GAP_MCHG_MASK                        (3 << 24)
-#       define DISP2_GAP_MCHG(x)                          ((x) << 26)
-#       define DISP2_GAP_MCHG_MASK                        (3 << 26)
-
-#define	CG_SPLL_SPREAD_SPECTRUM				0x790
-#define		SSEN					(1 << 0)
-#define		CLKS(x)					((x) << 4)
-#define		CLKS_MASK				(0xfff << 4)
-#define	CG_SPLL_SPREAD_SPECTRUM_2			0x794
-#define		CLKV(x)					((x) << 0)
-#define		CLKV_MASK				(0x3ffffff << 0)
-#define	CG_MPLL_SPREAD_SPECTRUM				0x798
-#define CG_UPLL_SPREAD_SPECTRUM				0x79c
-#	define SSEN_MASK				0x00000001
-
-#define CG_CGTT_LOCAL_0                                   0x7d0
-#define CG_CGTT_LOCAL_1                                   0x7d4
-
-#define BIOS_SCRATCH_4                                    0x1734
-
-#define MC_SEQ_MISC0                                      0x2a00
-#define         MC_SEQ_MISC0_GDDR5_SHIFT                  28
-#define         MC_SEQ_MISC0_GDDR5_MASK                   0xf0000000
-#define         MC_SEQ_MISC0_GDDR5_VALUE                  5
-
-#define MC_ARB_SQM_RATIO                                  0x2770
-#define		STATE0(x)				((x) << 0)
-#define		STATE0_MASK				(0xff << 0)
-#define		STATE1(x)				((x) << 8)
-#define		STATE1_MASK				(0xff << 8)
-#define		STATE2(x)				((x) << 16)
-#define		STATE2_MASK				(0xff << 16)
-#define		STATE3(x)				((x) << 24)
-#define		STATE3_MASK				(0xff << 24)
-
-#define	MC_ARB_RFSH_RATE				0x27b0
-#define		POWERMODE0(x)				((x) << 0)
-#define		POWERMODE0_MASK				(0xff << 0)
-#define		POWERMODE1(x)				((x) << 8)
-#define		POWERMODE1_MASK				(0xff << 8)
-#define		POWERMODE2(x)				((x) << 16)
-#define		POWERMODE2_MASK				(0xff << 16)
-#define		POWERMODE3(x)				((x) << 24)
-#define		POWERMODE3_MASK				(0xff << 24)
-
-#define CGTS_SM_CTRL_REG                                  0x9150
-
-/* Registers */
-#define	CB_COLOR0_BASE					0x28040
-#define	CB_COLOR1_BASE					0x28044
-#define	CB_COLOR2_BASE					0x28048
-#define	CB_COLOR3_BASE					0x2804C
-#define	CB_COLOR4_BASE					0x28050
-#define	CB_COLOR5_BASE					0x28054
-#define	CB_COLOR6_BASE					0x28058
-#define	CB_COLOR7_BASE					0x2805C
-#define	CB_COLOR7_FRAG					0x280FC
-
-#define	CC_GC_SHADER_PIPE_CONFIG			0x8950
-#define	CC_RB_BACKEND_DISABLE				0x98F4
-#define		BACKEND_DISABLE(x)				((x) << 16)
-#define	CC_SYS_RB_BACKEND_DISABLE			0x3F88
-
-#define	CGTS_SYS_TCC_DISABLE				0x3F90
-#define	CGTS_TCC_DISABLE				0x9148
-#define	CGTS_USER_SYS_TCC_DISABLE			0x3F94
-#define	CGTS_USER_TCC_DISABLE				0x914C
-
-#define	CONFIG_MEMSIZE					0x5428
-
-#define	CP_ME_CNTL					0x86D8
-#define		CP_ME_HALT					(1 << 28)
-#define		CP_PFP_HALT					(1 << 26)
-#define	CP_ME_RAM_DATA					0xC160
-#define	CP_ME_RAM_RADDR					0xC158
-#define	CP_ME_RAM_WADDR					0xC15C
-#define CP_MEQ_THRESHOLDS				0x8764
-#define		STQ_SPLIT(x)					((x) << 0)
-#define	CP_PERFMON_CNTL					0x87FC
-#define	CP_PFP_UCODE_ADDR				0xC150
-#define	CP_PFP_UCODE_DATA				0xC154
-#define	CP_QUEUE_THRESHOLDS				0x8760
-#define		ROQ_IB1_START(x)				((x) << 0)
-#define		ROQ_IB2_START(x)				((x) << 8)
-#define	CP_RB_CNTL					0xC104
-#define		RB_BUFSZ(x)					((x) << 0)
-#define		RB_BLKSZ(x)					((x) << 8)
-#define		RB_NO_UPDATE					(1 << 27)
-#define		RB_RPTR_WR_ENA					(1 << 31)
-#define		BUF_SWAP_32BIT					(2 << 16)
-#define	CP_RB_RPTR					0x8700
-#define	CP_RB_RPTR_ADDR					0xC10C
-#define	CP_RB_RPTR_ADDR_HI				0xC110
-#define	CP_RB_RPTR_WR					0xC108
-#define	CP_RB_WPTR					0xC114
-#define	CP_RB_WPTR_ADDR					0xC118
-#define	CP_RB_WPTR_ADDR_HI				0xC11C
-#define	CP_RB_WPTR_DELAY				0x8704
-#define	CP_SEM_WAIT_TIMER				0x85BC
-
-#define	DB_DEBUG3					0x98B0
-#define		DB_CLK_OFF_DELAY(x)				((x) << 11)
-#define DB_DEBUG4					0x9B8C
-#define		DISABLE_TILE_COVERED_FOR_PS_ITER		(1 << 6)
-
-#define	DCP_TILING_CONFIG				0x6CA0
-#define		PIPE_TILING(x)					((x) << 1)
-#define 	BANK_TILING(x)					((x) << 4)
-#define		GROUP_SIZE(x)					((x) << 6)
-#define		ROW_TILING(x)					((x) << 8)
-#define		BANK_SWAPS(x)					((x) << 11)
-#define		SAMPLE_SPLIT(x)					((x) << 14)
-#define		BACKEND_MAP(x)					((x) << 16)
-
-#define GB_TILING_CONFIG				0x98F0
-#define     PIPE_TILING__SHIFT              1
-#define     PIPE_TILING__MASK               0x0000000e
-
-#define DMA_TILING_CONFIG                               0x3ec8
-#define DMA_TILING_CONFIG2                              0xd0b8
-
-/* RV730 only */
-#define UVD_UDEC_TILING_CONFIG                          0xef40
-#define UVD_UDEC_DB_TILING_CONFIG                       0xef44
-#define UVD_UDEC_DBW_TILING_CONFIG                      0xef48
-#define UVD_NO_OP					0xeffc
-
-#define	GC_USER_SHADER_PIPE_CONFIG			0x8954
-#define		INACTIVE_QD_PIPES(x)				((x) << 8)
-#define		INACTIVE_QD_PIPES_MASK				0x0000FF00
-#define		INACTIVE_QD_PIPES_SHIFT			    8
-#define		INACTIVE_SIMDS(x)				((x) << 16)
-#define		INACTIVE_SIMDS_MASK				0x00FF0000
-
-#define	GRBM_CNTL					0x8000
-#define		GRBM_READ_TIMEOUT(x)				((x) << 0)
-#define	GRBM_SOFT_RESET					0x8020
-#define		SOFT_RESET_CP					(1<<0)
-#define	GRBM_STATUS					0x8010
-#define		CMDFIFO_AVAIL_MASK				0x0000000F
-#define		GUI_ACTIVE					(1<<31)
-#define	GRBM_STATUS2					0x8014
-
-#define	CG_THERMAL_CTRL					0x72C
-#define 	DPM_EVENT_SRC(x)			((x) << 0)
-#define 	DPM_EVENT_SRC_MASK			(7 << 0)
-#define		DIG_THERM_DPM(x)			((x) << 14)
-#define		DIG_THERM_DPM_MASK			0x003FC000
-#define		DIG_THERM_DPM_SHIFT			14
-
-#define	CG_THERMAL_INT					0x734
-#define		DIG_THERM_INTH(x)			((x) << 8)
-#define		DIG_THERM_INTH_MASK			0x0000FF00
-#define		DIG_THERM_INTH_SHIFT			8
-#define		DIG_THERM_INTL(x)			((x) << 16)
-#define		DIG_THERM_INTL_MASK			0x00FF0000
-#define		DIG_THERM_INTL_SHIFT			16
-#define 	THERM_INT_MASK_HIGH			(1 << 24)
-#define 	THERM_INT_MASK_LOW			(1 << 25)
-
-#define	CG_MULT_THERMAL_STATUS				0x740
-#define		ASIC_T(x)			        ((x) << 16)
-#define		ASIC_T_MASK			        0x3FF0000
-#define		ASIC_T_SHIFT			        16
-
-#define	HDP_HOST_PATH_CNTL				0x2C00
-#define	HDP_NONSURFACE_BASE				0x2C04
-#define	HDP_NONSURFACE_INFO				0x2C08
-#define	HDP_NONSURFACE_SIZE				0x2C0C
-#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0
-#define	HDP_TILING_CONFIG				0x2F3C
-#define HDP_DEBUG1                                      0x2F34
-
-#define MC_SHARED_CHMAP						0x2004
-#define		NOOFCHAN_SHIFT					12
-#define		NOOFCHAN_MASK					0x00003000
-#define MC_SHARED_CHREMAP					0x2008
-
-#define	MC_ARB_RAMCFG					0x2760
-#define		NOOFBANK_SHIFT					0
-#define		NOOFBANK_MASK					0x00000003
-#define		NOOFRANK_SHIFT					2
-#define		NOOFRANK_MASK					0x00000004
-#define		NOOFROWS_SHIFT					3
-#define		NOOFROWS_MASK					0x00000038
-#define		NOOFCOLS_SHIFT					6
-#define		NOOFCOLS_MASK					0x000000C0
-#define		CHANSIZE_SHIFT					8
-#define		CHANSIZE_MASK					0x00000100
-#define		BURSTLENGTH_SHIFT				9
-#define		BURSTLENGTH_MASK				0x00000200
-#define		CHANSIZE_OVERRIDE				(1 << 11)
-#define	MC_VM_AGP_TOP					0x2028
-#define	MC_VM_AGP_BOT					0x202C
-#define	MC_VM_AGP_BASE					0x2030
-#define	MC_VM_FB_LOCATION				0x2024
-#define	MC_VM_MB_L1_TLB0_CNTL				0x2234
-#define	MC_VM_MB_L1_TLB1_CNTL				0x2238
-#define	MC_VM_MB_L1_TLB2_CNTL				0x223C
-#define	MC_VM_MB_L1_TLB3_CNTL				0x2240
-#define		ENABLE_L1_TLB					(1 << 0)
-#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)
-#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)
-#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)
-#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)
-#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)
-#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)
-#define		EFFECTIVE_L1_TLB_SIZE(x)			((x)<<15)
-#define		EFFECTIVE_L1_QUEUE_SIZE(x)			((x)<<18)
-#define	MC_VM_MD_L1_TLB0_CNTL				0x2654
-#define	MC_VM_MD_L1_TLB1_CNTL				0x2658
-#define	MC_VM_MD_L1_TLB2_CNTL				0x265C
-#define	MC_VM_MD_L1_TLB3_CNTL				0x2698
-#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x203C
-#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2038
-#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2034
-
-#define	PA_CL_ENHANCE					0x8A14
-#define		CLIP_VTX_REORDER_ENA				(1 << 0)
-#define		NUM_CLIP_SEQ(x)					((x) << 1)
-#define PA_SC_AA_CONFIG					0x28C04
-#define PA_SC_CLIPRECT_RULE				0x2820C
-#define	PA_SC_EDGERULE					0x28230
-#define	PA_SC_FIFO_SIZE					0x8BCC
-#define		SC_PRIM_FIFO_SIZE(x)				((x) << 0)
-#define		SC_HIZ_TILE_FIFO_SIZE(x)			((x) << 12)
-#define	PA_SC_FORCE_EOV_MAX_CNTS			0x8B24
-#define		FORCE_EOV_MAX_CLK_CNT(x)			((x)<<0)
-#define		FORCE_EOV_MAX_REZ_CNT(x)			((x)<<16)
-#define PA_SC_LINE_STIPPLE				0x28A0C
-#define	PA_SC_LINE_STIPPLE_STATE			0x8B10
-#define PA_SC_MODE_CNTL					0x28A4C
-#define	PA_SC_MULTI_CHIP_CNTL				0x8B20
-#define		SC_EARLYZ_TILE_FIFO_SIZE(x)			((x) << 20)
-
-#define	SCRATCH_REG0					0x8500
-#define	SCRATCH_REG1					0x8504
-#define	SCRATCH_REG2					0x8508
-#define	SCRATCH_REG3					0x850C
-#define	SCRATCH_REG4					0x8510
-#define	SCRATCH_REG5					0x8514
-#define	SCRATCH_REG6					0x8518
-#define	SCRATCH_REG7					0x851C
-#define	SCRATCH_UMSK					0x8540
-#define	SCRATCH_ADDR					0x8544
-
-#define	SMX_SAR_CTL0					0xA008
-#define	SMX_DC_CTL0					0xA020
-#define		USE_HASH_FUNCTION				(1 << 0)
-#define		CACHE_DEPTH(x)					((x) << 1)
-#define		FLUSH_ALL_ON_EVENT				(1 << 10)
-#define		STALL_ON_EVENT					(1 << 11)
-#define	SMX_EVENT_CTL					0xA02C
-#define		ES_FLUSH_CTL(x)					((x) << 0)
-#define		GS_FLUSH_CTL(x)					((x) << 3)
-#define		ACK_FLUSH_CTL(x)				((x) << 6)
-#define		SYNC_FLUSH_CTL					(1 << 8)
-
-#define	SPI_CONFIG_CNTL					0x9100
-#define		GPR_WRITE_PRIORITY(x)				((x) << 0)
-#define		DISABLE_INTERP_1				(1 << 5)
-#define	SPI_CONFIG_CNTL_1				0x913C
-#define		VTX_DONE_DELAY(x)				((x) << 0)
-#define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)
-#define	SPI_INPUT_Z					0x286D8
-#define	SPI_PS_IN_CONTROL_0				0x286CC
-#define		NUM_INTERP(x)					((x)<<0)
-#define		POSITION_ENA					(1<<8)
-#define		POSITION_CENTROID				(1<<9)
-#define		POSITION_ADDR(x)				((x)<<10)
-#define		PARAM_GEN(x)					((x)<<15)
-#define		PARAM_GEN_ADDR(x)				((x)<<19)
-#define		BARYC_SAMPLE_CNTL(x)				((x)<<26)
-#define		PERSP_GRADIENT_ENA				(1<<28)
-#define		LINEAR_GRADIENT_ENA				(1<<29)
-#define		POSITION_SAMPLE					(1<<30)
-#define		BARYC_AT_SAMPLE_ENA				(1<<31)
-
-#define	SQ_CONFIG					0x8C00
-#define		VC_ENABLE					(1 << 0)
-#define		EXPORT_SRC_C					(1 << 1)
-#define		DX9_CONSTS					(1 << 2)
-#define		ALU_INST_PREFER_VECTOR				(1 << 3)
-#define		DX10_CLAMP					(1 << 4)
-#define		CLAUSE_SEQ_PRIO(x)				((x) << 8)
-#define		PS_PRIO(x)					((x) << 24)
-#define		VS_PRIO(x)					((x) << 26)
-#define		GS_PRIO(x)					((x) << 28)
-#define	SQ_DYN_GPR_SIZE_SIMD_AB_0			0x8DB0
-#define		SIMDA_RING0(x)					((x)<<0)
-#define		SIMDA_RING1(x)					((x)<<8)
-#define		SIMDB_RING0(x)					((x)<<16)
-#define		SIMDB_RING1(x)					((x)<<24)
-#define	SQ_DYN_GPR_SIZE_SIMD_AB_1			0x8DB4
-#define	SQ_DYN_GPR_SIZE_SIMD_AB_2			0x8DB8
-#define	SQ_DYN_GPR_SIZE_SIMD_AB_3			0x8DBC
-#define	SQ_DYN_GPR_SIZE_SIMD_AB_4			0x8DC0
-#define	SQ_DYN_GPR_SIZE_SIMD_AB_5			0x8DC4
-#define	SQ_DYN_GPR_SIZE_SIMD_AB_6			0x8DC8
-#define	SQ_DYN_GPR_SIZE_SIMD_AB_7			0x8DCC
-#define		ES_PRIO(x)					((x) << 30)
-#define	SQ_GPR_RESOURCE_MGMT_1				0x8C04
-#define		NUM_PS_GPRS(x)					((x) << 0)
-#define		NUM_VS_GPRS(x)					((x) << 16)
-#define		DYN_GPR_ENABLE					(1 << 27)
-#define		NUM_CLAUSE_TEMP_GPRS(x)				((x) << 28)
-#define	SQ_GPR_RESOURCE_MGMT_2				0x8C08
-#define		NUM_GS_GPRS(x)					((x) << 0)
-#define		NUM_ES_GPRS(x)					((x) << 16)
-#define	SQ_MS_FIFO_SIZES				0x8CF0
-#define		CACHE_FIFO_SIZE(x)				((x) << 0)
-#define		FETCH_FIFO_HIWATER(x)				((x) << 8)
-#define		DONE_FIFO_HIWATER(x)				((x) << 16)
-#define		ALU_UPDATE_FIFO_HIWATER(x)			((x) << 24)
-#define	SQ_STACK_RESOURCE_MGMT_1			0x8C10
-#define		NUM_PS_STACK_ENTRIES(x)				((x) << 0)
-#define		NUM_VS_STACK_ENTRIES(x)				((x) << 16)
-#define	SQ_STACK_RESOURCE_MGMT_2			0x8C14
-#define		NUM_GS_STACK_ENTRIES(x)				((x) << 0)
-#define		NUM_ES_STACK_ENTRIES(x)				((x) << 16)
-#define	SQ_THREAD_RESOURCE_MGMT				0x8C0C
-#define		NUM_PS_THREADS(x)				((x) << 0)
-#define		NUM_VS_THREADS(x)				((x) << 8)
-#define		NUM_GS_THREADS(x)				((x) << 16)
-#define		NUM_ES_THREADS(x)				((x) << 24)
-
-#define	SX_DEBUG_1					0x9058
-#define		ENABLE_NEW_SMX_ADDRESS				(1 << 16)
-#define	SX_EXPORT_BUFFER_SIZES				0x900C
-#define		COLOR_BUFFER_SIZE(x)				((x) << 0)
-#define		POSITION_BUFFER_SIZE(x)				((x) << 8)
-#define		SMX_BUFFER_SIZE(x)				((x) << 16)
-#define	SX_MISC						0x28350
-
-#define	TA_CNTL_AUX					0x9508
-#define		DISABLE_CUBE_WRAP				(1 << 0)
-#define		DISABLE_CUBE_ANISO				(1 << 1)
-#define		SYNC_GRADIENT					(1 << 24)
-#define		SYNC_WALKER					(1 << 25)
-#define		SYNC_ALIGNER					(1 << 26)
-#define		BILINEAR_PRECISION_6_BIT			(0 << 31)
-#define		BILINEAR_PRECISION_8_BIT			(1 << 31)
-
-#define	TCP_CNTL					0x9610
-#define	TCP_CHAN_STEER					0x9614
-
-#define	VC_ENHANCE					0x9714
-
-#define	VGT_CACHE_INVALIDATION				0x88C4
-#define		CACHE_INVALIDATION(x)				((x)<<0)
-#define			VC_ONLY						0
-#define			TC_ONLY						1
-#define			VC_AND_TC					2
-#define		AUTO_INVLD_EN(x)				((x) << 6)
-#define			NO_AUTO						0
-#define			ES_AUTO						1
-#define			GS_AUTO						2
-#define			ES_AND_GS_AUTO					3
-#define	VGT_ES_PER_GS					0x88CC
-#define	VGT_GS_PER_ES					0x88C8
-#define	VGT_GS_PER_VS					0x88E8
-#define	VGT_GS_VERTEX_REUSE				0x88D4
-#define	VGT_NUM_INSTANCES				0x8974
-#define	VGT_OUT_DEALLOC_CNTL				0x28C5C
-#define		DEALLOC_DIST_MASK				0x0000007F
-#define	VGT_STRMOUT_EN					0x28AB0
-#define	VGT_VERTEX_REUSE_BLOCK_CNTL			0x28C58
-#define		VTX_REUSE_DEPTH_MASK				0x000000FF
-
-#define VM_CONTEXT0_CNTL				0x1410
-#define		ENABLE_CONTEXT					(1 << 0)
-#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
-#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
-#define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x153C
-#define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x157C
-#define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x155C
-#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x1518
-#define VM_L2_CNTL					0x1400
-#define		ENABLE_L2_CACHE					(1 << 0)
-#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
-#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)
-#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 14)
-#define VM_L2_CNTL2					0x1404
-#define		INVALIDATE_ALL_L1_TLBS				(1 << 0)
-#define		INVALIDATE_L2_CACHE				(1 << 1)
-#define VM_L2_CNTL3					0x1408
-#define		BANK_SELECT(x)					((x) << 0)
-#define		CACHE_UPDATE_MODE(x)				((x) << 6)
-#define	VM_L2_STATUS					0x140C
-#define		L2_BUSY						(1 << 0)
-
-#define	WAIT_UNTIL					0x8040
-
-/* async DMA */
-#define DMA_RB_RPTR                                       0xd008
-#define DMA_RB_WPTR                                       0xd00c
-
-/* async DMA packets */
-#define DMA_PACKET(cmd, t, s, n)	((((cmd) & 0xF) << 28) |	\
-					 (((t) & 0x1) << 23) |		\
-					 (((s) & 0x1) << 22) |		\
-					 (((n) & 0xFFFF) << 0))
-/* async DMA Packet types */
-#define	DMA_PACKET_WRITE				  0x2
-#define	DMA_PACKET_COPY					  0x3
-#define	DMA_PACKET_INDIRECT_BUFFER			  0x4
-#define	DMA_PACKET_SEMAPHORE				  0x5
-#define	DMA_PACKET_FENCE				  0x6
-#define	DMA_PACKET_TRAP					  0x7
-#define	DMA_PACKET_CONSTANT_FILL			  0xd
-#define	DMA_PACKET_NOP					  0xf
-
-
-#define	SRBM_STATUS				        0x0E50
-
-/* DCE 3.2 HDMI */
-#define HDMI_CONTROL                         0x7400
-#       define HDMI_KEEPOUT_MODE             (1 << 0)
-#       define HDMI_PACKET_GEN_VERSION       (1 << 4) /* 0 = r6xx compat */
-#       define HDMI_ERROR_ACK                (1 << 8)
-#       define HDMI_ERROR_MASK               (1 << 9)
-#define HDMI_STATUS                          0x7404
-#       define HDMI_ACTIVE_AVMUTE            (1 << 0)
-#       define HDMI_AUDIO_PACKET_ERROR       (1 << 16)
-#       define HDMI_VBI_PACKET_ERROR         (1 << 20)
-#define HDMI_AUDIO_PACKET_CONTROL            0x7408
-#       define HDMI_AUDIO_DELAY_EN(x)        (((x) & 3) << 4)
-#       define HDMI_AUDIO_PACKETS_PER_LINE(x)  (((x) & 0x1f) << 16)
-#define HDMI_ACR_PACKET_CONTROL              0x740c
-#       define HDMI_ACR_SEND                 (1 << 0)
-#       define HDMI_ACR_CONT                 (1 << 1)
-#       define HDMI_ACR_SELECT(x)            (((x) & 3) << 4)
-#       define HDMI_ACR_HW                   0
-#       define HDMI_ACR_32                   1
-#       define HDMI_ACR_44                   2
-#       define HDMI_ACR_48                   3
-#       define HDMI_ACR_SOURCE               (1 << 8) /* 0 - hw; 1 - cts value */
-#       define HDMI_ACR_AUTO_SEND            (1 << 12)
-#define HDMI_VBI_PACKET_CONTROL              0x7410
-#       define HDMI_NULL_SEND                (1 << 0)
-#       define HDMI_GC_SEND                  (1 << 4)
-#       define HDMI_GC_CONT                  (1 << 5) /* 0 - once; 1 - every frame */
-#define HDMI_INFOFRAME_CONTROL0              0x7414
-#       define HDMI_AVI_INFO_SEND            (1 << 0)
-#       define HDMI_AVI_INFO_CONT            (1 << 1)
-#       define HDMI_AUDIO_INFO_SEND          (1 << 4)
-#       define HDMI_AUDIO_INFO_CONT          (1 << 5)
-#       define HDMI_MPEG_INFO_SEND           (1 << 8)
-#       define HDMI_MPEG_INFO_CONT           (1 << 9)
-#define HDMI_INFOFRAME_CONTROL1              0x7418
-#       define HDMI_AVI_INFO_LINE(x)         (((x) & 0x3f) << 0)
-#       define HDMI_AUDIO_INFO_LINE(x)       (((x) & 0x3f) << 8)
-#       define HDMI_MPEG_INFO_LINE(x)        (((x) & 0x3f) << 16)
-#define HDMI_GENERIC_PACKET_CONTROL          0x741c
-#       define HDMI_GENERIC0_SEND            (1 << 0)
-#       define HDMI_GENERIC0_CONT            (1 << 1)
-#       define HDMI_GENERIC1_SEND            (1 << 4)
-#       define HDMI_GENERIC1_CONT            (1 << 5)
-#       define HDMI_GENERIC0_LINE(x)         (((x) & 0x3f) << 16)
-#       define HDMI_GENERIC1_LINE(x)         (((x) & 0x3f) << 24)
-#define HDMI_GC                              0x7428
-#       define HDMI_GC_AVMUTE                (1 << 0)
-#define AFMT_AUDIO_PACKET_CONTROL2           0x742c
-#       define AFMT_AUDIO_LAYOUT_OVRD        (1 << 0)
-#       define AFMT_AUDIO_LAYOUT_SELECT      (1 << 1)
-#       define AFMT_60958_CS_SOURCE          (1 << 4)
-#       define AFMT_AUDIO_CHANNEL_ENABLE(x)  (((x) & 0xff) << 8)
-#       define AFMT_DP_AUDIO_STREAM_ID(x)    (((x) & 0xff) << 16)
-#define AFMT_AVI_INFO0                       0x7454
-#       define AFMT_AVI_INFO_CHECKSUM(x)     (((x) & 0xff) << 0)
-#       define AFMT_AVI_INFO_S(x)            (((x) & 3) << 8)
-#       define AFMT_AVI_INFO_B(x)            (((x) & 3) << 10)
-#       define AFMT_AVI_INFO_A(x)            (((x) & 1) << 12)
-#       define AFMT_AVI_INFO_Y(x)            (((x) & 3) << 13)
-#       define AFMT_AVI_INFO_Y_RGB           0
-#       define AFMT_AVI_INFO_Y_YCBCR422      1
-#       define AFMT_AVI_INFO_Y_YCBCR444      2
-#       define AFMT_AVI_INFO_Y_A_B_S(x)      (((x) & 0xff) << 8)
-#       define AFMT_AVI_INFO_R(x)            (((x) & 0xf) << 16)
-#       define AFMT_AVI_INFO_M(x)            (((x) & 0x3) << 20)
-#       define AFMT_AVI_INFO_C(x)            (((x) & 0x3) << 22)
-#       define AFMT_AVI_INFO_C_M_R(x)        (((x) & 0xff) << 16)
-#       define AFMT_AVI_INFO_SC(x)           (((x) & 0x3) << 24)
-#       define AFMT_AVI_INFO_Q(x)            (((x) & 0x3) << 26)
-#       define AFMT_AVI_INFO_EC(x)           (((x) & 0x3) << 28)
-#       define AFMT_AVI_INFO_ITC(x)          (((x) & 0x1) << 31)
-#       define AFMT_AVI_INFO_ITC_EC_Q_SC(x)  (((x) & 0xff) << 24)
-#define AFMT_AVI_INFO1                       0x7458
-#       define AFMT_AVI_INFO_VIC(x)          (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
-#       define AFMT_AVI_INFO_PR(x)           (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
-#       define AFMT_AVI_INFO_TOP(x)          (((x) & 0xffff) << 16)
-#define AFMT_AVI_INFO2                       0x745c
-#       define AFMT_AVI_INFO_BOTTOM(x)       (((x) & 0xffff) << 0)
-#       define AFMT_AVI_INFO_LEFT(x)         (((x) & 0xffff) << 16)
-#define AFMT_AVI_INFO3                       0x7460
-#       define AFMT_AVI_INFO_RIGHT(x)        (((x) & 0xffff) << 0)
-#       define AFMT_AVI_INFO_VERSION(x)      (((x) & 3) << 24)
-#define AFMT_MPEG_INFO0                      0x7464
-#       define AFMT_MPEG_INFO_CHECKSUM(x)    (((x) & 0xff) << 0)
-#       define AFMT_MPEG_INFO_MB0(x)         (((x) & 0xff) << 8)
-#       define AFMT_MPEG_INFO_MB1(x)         (((x) & 0xff) << 16)
-#       define AFMT_MPEG_INFO_MB2(x)         (((x) & 0xff) << 24)
-#define AFMT_MPEG_INFO1                      0x7468
-#       define AFMT_MPEG_INFO_MB3(x)         (((x) & 0xff) << 0)
-#       define AFMT_MPEG_INFO_MF(x)          (((x) & 3) << 8)
-#       define AFMT_MPEG_INFO_FR(x)          (((x) & 1) << 12)
-#define AFMT_GENERIC0_HDR                    0x746c
-#define AFMT_GENERIC0_0                      0x7470
-#define AFMT_GENERIC0_1                      0x7474
-#define AFMT_GENERIC0_2                      0x7478
-#define AFMT_GENERIC0_3                      0x747c
-#define AFMT_GENERIC0_4                      0x7480
-#define AFMT_GENERIC0_5                      0x7484
-#define AFMT_GENERIC0_6                      0x7488
-#define AFMT_GENERIC1_HDR                    0x748c
-#define AFMT_GENERIC1_0                      0x7490
-#define AFMT_GENERIC1_1                      0x7494
-#define AFMT_GENERIC1_2                      0x7498
-#define AFMT_GENERIC1_3                      0x749c
-#define AFMT_GENERIC1_4                      0x74a0
-#define AFMT_GENERIC1_5                      0x74a4
-#define AFMT_GENERIC1_6                      0x74a8
-#define HDMI_ACR_32_0                        0x74ac
-#       define HDMI_ACR_CTS_32(x)            (((x) & 0xfffff) << 12)
-#define HDMI_ACR_32_1                        0x74b0
-#       define HDMI_ACR_N_32(x)              (((x) & 0xfffff) << 0)
-#define HDMI_ACR_44_0                        0x74b4
-#       define HDMI_ACR_CTS_44(x)            (((x) & 0xfffff) << 12)
-#define HDMI_ACR_44_1                        0x74b8
-#       define HDMI_ACR_N_44(x)              (((x) & 0xfffff) << 0)
-#define HDMI_ACR_48_0                        0x74bc
-#       define HDMI_ACR_CTS_48(x)            (((x) & 0xfffff) << 12)
-#define HDMI_ACR_48_1                        0x74c0
-#       define HDMI_ACR_N_48(x)              (((x) & 0xfffff) << 0)
-#define HDMI_ACR_STATUS_0                    0x74c4
-#define HDMI_ACR_STATUS_1                    0x74c8
-#define AFMT_AUDIO_INFO0                     0x74cc
-#       define AFMT_AUDIO_INFO_CHECKSUM(x)   (((x) & 0xff) << 0)
-#       define AFMT_AUDIO_INFO_CC(x)         (((x) & 7) << 8)
-#       define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x)   (((x) & 0xff) << 16)
-#define AFMT_AUDIO_INFO1                     0x74d0
-#       define AFMT_AUDIO_INFO_CA(x)         (((x) & 0xff) << 0)
-#       define AFMT_AUDIO_INFO_LSV(x)        (((x) & 0xf) << 11)
-#       define AFMT_AUDIO_INFO_DM_INH(x)     (((x) & 1) << 15)
-#       define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
-#define AFMT_60958_0                         0x74d4
-#       define AFMT_60958_CS_A(x)            (((x) & 1) << 0)
-#       define AFMT_60958_CS_B(x)            (((x) & 1) << 1)
-#       define AFMT_60958_CS_C(x)            (((x) & 1) << 2)
-#       define AFMT_60958_CS_D(x)            (((x) & 3) << 3)
-#       define AFMT_60958_CS_MODE(x)         (((x) & 3) << 6)
-#       define AFMT_60958_CS_CATEGORY_CODE(x)      (((x) & 0xff) << 8)
-#       define AFMT_60958_CS_SOURCE_NUMBER(x)      (((x) & 0xf) << 16)
-#       define AFMT_60958_CS_CHANNEL_NUMBER_L(x)   (((x) & 0xf) << 20)
-#       define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
-#       define AFMT_60958_CS_CLOCK_ACCURACY(x)     (((x) & 3) << 28)
-#define AFMT_60958_1                         0x74d8
-#       define AFMT_60958_CS_WORD_LENGTH(x)  (((x) & 0xf) << 0)
-#       define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x)   (((x) & 0xf) << 4)
-#       define AFMT_60958_CS_VALID_L(x)      (((x) & 1) << 16)
-#       define AFMT_60958_CS_VALID_R(x)      (((x) & 1) << 18)
-#       define AFMT_60958_CS_CHANNEL_NUMBER_R(x)   (((x) & 0xf) << 20)
-#define AFMT_AUDIO_CRC_CONTROL               0x74dc
-#       define AFMT_AUDIO_CRC_EN             (1 << 0)
-#define AFMT_RAMP_CONTROL0                   0x74e0
-#       define AFMT_RAMP_MAX_COUNT(x)        (((x) & 0xffffff) << 0)
-#       define AFMT_RAMP_DATA_SIGN           (1 << 31)
-#define AFMT_RAMP_CONTROL1                   0x74e4
-#       define AFMT_RAMP_MIN_COUNT(x)        (((x) & 0xffffff) << 0)
-#       define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
-#define AFMT_RAMP_CONTROL2                   0x74e8
-#       define AFMT_RAMP_INC_COUNT(x)        (((x) & 0xffffff) << 0)
-#define AFMT_RAMP_CONTROL3                   0x74ec
-#       define AFMT_RAMP_DEC_COUNT(x)        (((x) & 0xffffff) << 0)
-#define AFMT_60958_2                         0x74f0
-#       define AFMT_60958_CS_CHANNEL_NUMBER_2(x)   (((x) & 0xf) << 0)
-#       define AFMT_60958_CS_CHANNEL_NUMBER_3(x)   (((x) & 0xf) << 4)
-#       define AFMT_60958_CS_CHANNEL_NUMBER_4(x)   (((x) & 0xf) << 8)
-#       define AFMT_60958_CS_CHANNEL_NUMBER_5(x)   (((x) & 0xf) << 12)
-#       define AFMT_60958_CS_CHANNEL_NUMBER_6(x)   (((x) & 0xf) << 16)
-#       define AFMT_60958_CS_CHANNEL_NUMBER_7(x)   (((x) & 0xf) << 20)
-#define AFMT_STATUS                          0x7600
-#       define AFMT_AUDIO_ENABLE             (1 << 4)
-#       define AFMT_AZ_FORMAT_WTRIG          (1 << 28)
-#       define AFMT_AZ_FORMAT_WTRIG_INT      (1 << 29)
-#       define AFMT_AZ_AUDIO_ENABLE_CHG      (1 << 30)
-#define AFMT_AUDIO_PACKET_CONTROL            0x7604
-#       define AFMT_AUDIO_SAMPLE_SEND        (1 << 0)
-#       define AFMT_AUDIO_TEST_EN            (1 << 12)
-#       define AFMT_AUDIO_CHANNEL_SWAP       (1 << 24)
-#       define AFMT_60958_CS_UPDATE          (1 << 26)
-#       define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
-#       define AFMT_AZ_FORMAT_WTRIG_MASK     (1 << 28)
-#       define AFMT_AZ_FORMAT_WTRIG_ACK      (1 << 29)
-#       define AFMT_AZ_AUDIO_ENABLE_CHG_ACK  (1 << 30)
-#define AFMT_VBI_PACKET_CONTROL              0x7608
-#       define AFMT_GENERIC0_UPDATE          (1 << 2)
-#define AFMT_INFOFRAME_CONTROL0              0x760c
-#       define AFMT_AUDIO_INFO_SOURCE        (1 << 6) /* 0 - sound block; 1 - hdmi regs */
-#       define AFMT_AUDIO_INFO_UPDATE        (1 << 7)
-#       define AFMT_MPEG_INFO_UPDATE         (1 << 10)
-#define AFMT_GENERIC0_7                      0x7610
-/* second instance starts at 0x7800 */
-#define HDMI_OFFSET0                      (0x7400 - 0x7400)
-#define HDMI_OFFSET1                      (0x7800 - 0x7400)
-
-/* DCE3.2 ELD audio interface */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0        0x71c8 /* LPCM */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1        0x71cc /* AC3 */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2        0x71d0 /* MPEG1 */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3        0x71d4 /* MP3 */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4        0x71d8 /* MPEG2 */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5        0x71dc /* AAC */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6        0x71e0 /* DTS */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7        0x71e4 /* ATRAC */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8        0x71e8 /* one bit audio - leave at 0 (default) */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9        0x71ec /* Dolby Digital */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10       0x71f0 /* DTS-HD */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11       0x71f4 /* MAT-MLP */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12       0x71f8 /* DTS */
-#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13       0x71fc /* WMA Pro */
-#       define MAX_CHANNELS(x)                            (((x) & 0x7) << 0)
-/* max channels minus one.  7 = 8 channels */
-#       define SUPPORTED_FREQUENCIES(x)                   (((x) & 0xff) << 8)
-#       define DESCRIPTOR_BYTE_2(x)                       (((x) & 0xff) << 16)
-#       define SUPPORTED_FREQUENCIES_STEREO(x)            (((x) & 0xff) << 24) /* LPCM only */
-/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
- * bit0 = 32 kHz
- * bit1 = 44.1 kHz
- * bit2 = 48 kHz
- * bit3 = 88.2 kHz
- * bit4 = 96 kHz
- * bit5 = 176.4 kHz
- * bit6 = 192 kHz
- */
-
-#define AZ_HOT_PLUG_CONTROL                               0x7300
-#       define AZ_FORCE_CODEC_WAKE                        (1 << 0)
-#       define PIN0_JACK_DETECTION_ENABLE                 (1 << 4)
-#       define PIN1_JACK_DETECTION_ENABLE                 (1 << 5)
-#       define PIN2_JACK_DETECTION_ENABLE                 (1 << 6)
-#       define PIN3_JACK_DETECTION_ENABLE                 (1 << 7)
-#       define PIN0_UNSOLICITED_RESPONSE_ENABLE           (1 << 8)
-#       define PIN1_UNSOLICITED_RESPONSE_ENABLE           (1 << 9)
-#       define PIN2_UNSOLICITED_RESPONSE_ENABLE           (1 << 10)
-#       define PIN3_UNSOLICITED_RESPONSE_ENABLE           (1 << 11)
-#       define CODEC_HOT_PLUG_ENABLE                      (1 << 12)
-#       define PIN0_AUDIO_ENABLED                         (1 << 24)
-#       define PIN1_AUDIO_ENABLED                         (1 << 25)
-#       define PIN2_AUDIO_ENABLED                         (1 << 26)
-#       define PIN3_AUDIO_ENABLED                         (1 << 27)
-#       define AUDIO_ENABLED                              (1 << 31)
-
-
-#define D1GRPH_PRIMARY_SURFACE_ADDRESS                    0x6110
-#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH               0x6914
-#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH               0x6114
-#define D1GRPH_SECONDARY_SURFACE_ADDRESS                  0x6118
-#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH             0x691c
-#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH             0x611c
-
-/* PCIE indirect regs */
-#define PCIE_P_CNTL                                       0x40
-#       define P_PLL_PWRDN_IN_L1L23                       (1 << 3)
-#       define P_PLL_BUF_PDNB                             (1 << 4)
-#       define P_PLL_PDNB                                 (1 << 9)
-#       define P_ALLOW_PRX_FRONTEND_SHUTOFF               (1 << 12)
-/* PCIE PORT regs */
-#define PCIE_LC_CNTL                                      0xa0
-#       define LC_L0S_INACTIVITY(x)                       ((x) << 8)
-#       define LC_L0S_INACTIVITY_MASK                     (0xf << 8)
-#       define LC_L0S_INACTIVITY_SHIFT                    8
-#       define LC_L1_INACTIVITY(x)                        ((x) << 12)
-#       define LC_L1_INACTIVITY_MASK                      (0xf << 12)
-#       define LC_L1_INACTIVITY_SHIFT                     12
-#       define LC_PMI_TO_L1_DIS                           (1 << 16)
-#       define LC_ASPM_TO_L1_DIS                          (1 << 24)
-#define PCIE_LC_TRAINING_CNTL                             0xa1 /* PCIE_P */
-#define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */
-#       define LC_LINK_WIDTH_SHIFT                        0
-#       define LC_LINK_WIDTH_MASK                         0x7
-#       define LC_LINK_WIDTH_X0                           0
-#       define LC_LINK_WIDTH_X1                           1
-#       define LC_LINK_WIDTH_X2                           2
-#       define LC_LINK_WIDTH_X4                           3
-#       define LC_LINK_WIDTH_X8                           4
-#       define LC_LINK_WIDTH_X16                          6
-#       define LC_LINK_WIDTH_RD_SHIFT                     4
-#       define LC_LINK_WIDTH_RD_MASK                      0x70
-#       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)
-#       define LC_RECONFIG_NOW                            (1 << 8)
-#       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)
-#       define LC_RENEGOTIATE_EN                          (1 << 10)
-#       define LC_SHORT_RECONFIG_EN                       (1 << 11)
-#       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)
-#       define LC_UPCONFIGURE_DIS                         (1 << 13)
-#define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */
-#       define LC_GEN2_EN_STRAP                           (1 << 0)
-#       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 1)
-#       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 5)
-#       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 6)
-#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 8)
-#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     3
-#       define LC_CURRENT_DATA_RATE                       (1 << 11)
-#       define LC_HW_VOLTAGE_IF_CONTROL(x)                ((x) << 12)
-#       define LC_HW_VOLTAGE_IF_CONTROL_MASK              (3 << 12)
-#       define LC_HW_VOLTAGE_IF_CONTROL_SHIFT             12
-#       define LC_VOLTAGE_TIMER_SEL_MASK                  (0xf << 14)
-#       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 21)
-#       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 23)
-#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 24)
-#define MM_CFGREGS_CNTL                                   0x544c
-#       define MM_WR_TO_CFG_EN                            (1 << 3)
-#define LINK_CNTL2                                        0x88 /* F0 */
-#       define TARGET_LINK_SPEED_MASK                     (0xf << 0)
-#       define SELECTABLE_DEEMPHASIS                      (1 << 6)
-
-/*
- * PM4
- */
-#define PACKET0(reg, n)	((RADEON_PACKET_TYPE0 << 30) |			\
-			 (((reg) >> 2) & 0xFFFF) |			\
-			 ((n) & 0x3FFF) << 16)
-#define PACKET3(op, n)	((RADEON_PACKET_TYPE3 << 30) |			\
-			 (((op) & 0xFF) << 8) |				\
-			 ((n) & 0x3FFF) << 16)
-
-/* UVD */
-#define UVD_SEMA_ADDR_LOW				0xef00
-#define UVD_SEMA_ADDR_HIGH				0xef04
-#define UVD_SEMA_CMD					0xef08
-#define UVD_GPCOM_VCPU_CMD				0xef0c
-#define UVD_GPCOM_VCPU_DATA0				0xef10
-#define UVD_GPCOM_VCPU_DATA1				0xef14
-
-#define UVD_LMI_EXT40_ADDR				0xf498
-#define UVD_VCPU_CHIP_ID				0xf4d4
-#define UVD_VCPU_CACHE_OFFSET0				0xf4d8
-#define UVD_VCPU_CACHE_SIZE0				0xf4dc
-#define UVD_VCPU_CACHE_OFFSET1				0xf4e0
-#define UVD_VCPU_CACHE_SIZE1				0xf4e4
-#define UVD_VCPU_CACHE_OFFSET2				0xf4e8
-#define UVD_VCPU_CACHE_SIZE2				0xf4ec
-#define UVD_LMI_ADDR_EXT				0xf594
-
-#define UVD_RBC_RB_RPTR					0xf690
-#define UVD_RBC_RB_WPTR					0xf694
-
-#define UVD_CONTEXT_ID					0xf6f4
-
-#endif
diff --git a/hw/display/si_blit_shaders.h b/hw/display/si_blit_shaders.h
deleted file mode 100644
index c739e51e39..0000000000
--- a/hw/display/si_blit_shaders.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef SI_BLIT_SHADERS_H
-#define SI_BLIT_SHADERS_H
-
-extern const u32 si_default_state[];
-
-extern const u32 si_default_size;
-
-#endif
diff --git a/hw/display/si_dpm.h b/hw/display/si_dpm.h
deleted file mode 100644
index 1032a68be7..0000000000
--- a/hw/display/si_dpm.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * Copyright 2012 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __SI_DPM_H__
-#define __SI_DPM_H__
-
-#include "ni_dpm.h"
-#include "sislands_smc.h"
-
-enum si_cac_config_reg_type
-{
-	SISLANDS_CACCONFIG_MMR = 0,
-	SISLANDS_CACCONFIG_CGIND,
-	SISLANDS_CACCONFIG_MAX
-};
-
-struct si_cac_config_reg
-{
-	u32 offset;
-	u32 mask;
-	u32 shift;
-	u32 value;
-	enum si_cac_config_reg_type type;
-};
-
-struct si_powertune_data
-{
-	u32 cac_window;
-	u32 l2_lta_window_size_default;
-	u8 lts_truncate_default;
-	u8 shift_n_default;
-	u8 operating_temp;
-	struct ni_leakage_coeffients leakage_coefficients;
-	u32 fixed_kt;
-	u32 lkge_lut_v0_percent;
-	u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
-	bool enable_powertune_by_default;
-};
-
-struct si_dyn_powertune_data
-{
-	u32 cac_leakage;
-	s32 leakage_minimum_temperature;
-	u32 wintime;
-	u32 l2_lta_window_size;
-	u8 lts_truncate;
-	u8 shift_n;
-	u8 dc_pwr_value;
-	bool disable_uvd_powertune;
-};
-
-struct si_dte_data
-{
-	u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
-	u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
-	u32 k;
-	u32 t0;
-	u32 max_t;
-	u8 window_size;
-	u8 temp_select;
-	u8 dte_mode;
-	u8 tdep_count;
-	u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
-	u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
-	u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
-	u32 t_threshold;
-	bool enable_dte_by_default;
-};
-
-struct si_clock_registers {
-	u32 cg_spll_func_cntl;
-	u32 cg_spll_func_cntl_2;
-	u32 cg_spll_func_cntl_3;
-	u32 cg_spll_func_cntl_4;
-	u32 cg_spll_spread_spectrum;
-	u32 cg_spll_spread_spectrum_2;
-	u32 dll_cntl;
-	u32 mclk_pwrmgt_cntl;
-	u32 mpll_ad_func_cntl;
-	u32 mpll_dq_func_cntl;
-	u32 mpll_func_cntl;
-	u32 mpll_func_cntl_1;
-	u32 mpll_func_cntl_2;
-	u32 mpll_ss1;
-	u32 mpll_ss2;
-};
-
-struct si_mc_reg_entry {
-	u32 mclk_max;
-	u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
-};
-
-struct si_mc_reg_table {
-	u8 last;
-	u8 num_entries;
-	u16 valid_flag;
-	struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
-	SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
-};
-
-#define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT               0
-#define SISLANDS_MCREGISTERTABLE_ACPI_SLOT                  1
-#define SISLANDS_MCREGISTERTABLE_ULV_SLOT                   2
-#define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT     3
-
-struct si_leakage_voltage_entry
-{
-	u16 voltage;
-	u16 leakage_index;
-};
-
-#define SISLANDS_LEAKAGE_INDEX0     0xff01
-#define SISLANDS_MAX_LEAKAGE_COUNT  4
-
-struct si_leakage_voltage
-{
-	u16 count;
-	struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT];
-};
-
-#define SISLANDS_MAX_HARDWARE_POWERLEVELS 5
-
-struct si_ulv_param {
-	bool supported;
-	u32 cg_ulv_control;
-	u32 cg_ulv_parameter;
-	u32 volt_change_delay;
-	struct rv7xx_pl pl;
-	bool one_pcie_lane_in_ulv;
-};
-
-struct si_power_info {
-	/* must be first! */
-	struct ni_power_info ni;
-	struct si_clock_registers clock_registers;
-	struct si_mc_reg_table mc_reg_table;
-	struct atom_voltage_table mvdd_voltage_table;
-	struct atom_voltage_table vddc_phase_shed_table;
-	struct si_leakage_voltage leakage_voltage;
-	u16 mvdd_bootup_value;
-	struct si_ulv_param ulv;
-	u32 max_cu;
-	/* pcie gen */
-	enum radeon_pcie_gen force_pcie_gen;
-	enum radeon_pcie_gen boot_pcie_gen;
-	enum radeon_pcie_gen acpi_pcie_gen;
-	u32 sys_pcie_mask;
-	/* flags */
-	bool enable_dte;
-	bool enable_ppm;
-	bool vddc_phase_shed_control;
-	bool pspp_notify_required;
-	bool sclk_deep_sleep_above_low;
-	bool voltage_control_svi2;
-	bool vddci_control_svi2;
-	/* smc offsets */
-	u32 sram_end;
-	u32 state_table_start;
-	u32 soft_regs_start;
-	u32 mc_reg_table_start;
-	u32 arb_table_start;
-	u32 cac_table_start;
-	u32 dte_table_start;
-	u32 spll_table_start;
-	u32 papm_cfg_table_start;
-	u32 fan_table_start;
-	/* CAC stuff */
-	const struct si_cac_config_reg *cac_weights;
-	const struct si_cac_config_reg *lcac_config;
-	const struct si_cac_config_reg *cac_override;
-	const struct si_powertune_data *powertune_data;
-	struct si_dyn_powertune_data dyn_powertune_data;
-	/* DTE stuff */
-	struct si_dte_data dte_data;
-	/* scratch structs */
-	SMC_SIslands_MCRegisters smc_mc_reg_table;
-	SISLANDS_SMC_STATETABLE smc_statetable;
-	PP_SIslands_PAPMParameters papm_parm;
-	/* SVI2 */
-	u8 svd_gpio_id;
-	u8 svc_gpio_id;
-	/* fan control */
-	bool fan_ctrl_is_in_default_mode;
-	u32 t_min;
-	u32 fan_ctrl_default_mode;
-	bool fan_is_controlled_by_smc;
-};
-
-#define SISLANDS_INITIAL_STATE_ARB_INDEX    0
-#define SISLANDS_ACPI_STATE_ARB_INDEX       1
-#define SISLANDS_ULV_STATE_ARB_INDEX        2
-#define SISLANDS_DRIVER_STATE_ARB_INDEX     3
-
-#define SISLANDS_DPM2_MAX_PULSE_SKIP        256
-
-#define SISLANDS_DPM2_NEAR_TDP_DEC          10
-#define SISLANDS_DPM2_ABOVE_SAFE_INC        5
-#define SISLANDS_DPM2_BELOW_SAFE_INC        20
-
-#define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT            80
-
-#define SISLANDS_DPM2_MAXPS_PERCENT_H                   99
-#define SISLANDS_DPM2_MAXPS_PERCENT_M                   99
-
-#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
-#define SISLANDS_DPM2_SQ_RAMP_MIN_POWER                 0x12
-#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
-#define SISLANDS_DPM2_SQ_RAMP_STI_SIZE                  0x1E
-#define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO                 0xF
-
-#define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN         10
-
-#define SISLANDS_VRC_DFLT                               0xC000B3
-#define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT             1687
-#define SISLANDS_CGULVPARAMETER_DFLT                    0x00040035
-#define SISLANDS_CGULVCONTROL_DFLT                      0x1f007550
-
-
-#endif
diff --git a/hw/display/sid.h b/hw/display/sid.h
deleted file mode 100644
index 65a911ddd5..0000000000
--- a/hw/display/sid.h
+++ /dev/null
@@ -1,1956 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Alex Deucher
- */
-#ifndef SI_H
-#define SI_H
-
-#define TAHITI_RB_BITMAP_WIDTH_PER_SH  2
-
-#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003
-#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002
-#define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02010001
-
-#define SI_MAX_SH_GPRS           256
-#define SI_MAX_TEMP_GPRS         16
-#define SI_MAX_SH_THREADS        256
-#define SI_MAX_SH_STACK_ENTRIES  4096
-#define SI_MAX_FRC_EOV_CNT       16384
-#define SI_MAX_BACKENDS          8
-#define SI_MAX_BACKENDS_MASK     0xFF
-#define SI_MAX_BACKENDS_PER_SE_MASK     0x0F
-#define SI_MAX_SIMDS             12
-#define SI_MAX_SIMDS_MASK        0x0FFF
-#define SI_MAX_SIMDS_PER_SE_MASK        0x00FF
-#define SI_MAX_PIPES             8
-#define SI_MAX_PIPES_MASK        0xFF
-#define SI_MAX_PIPES_PER_SIMD_MASK      0x3F
-#define SI_MAX_LDS_NUM           0xFFFF
-#define SI_MAX_TCC               16
-#define SI_MAX_TCC_MASK          0xFFFF
-
-/* SMC IND accessor regs */
-#define SMC_IND_INDEX_0                              0x200
-#define SMC_IND_DATA_0                               0x204
-
-#define SMC_IND_ACCESS_CNTL                          0x228
-#       define AUTO_INCREMENT_IND_0                  (1 << 0)
-#define SMC_MESSAGE_0                                0x22c
-#define SMC_RESP_0                                   0x230
-
-/* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
-#define SMC_CG_IND_START                    0xc0030000
-#define SMC_CG_IND_END                      0xc0040000
-
-#define	CG_CGTT_LOCAL_0				0x400
-#define	CG_CGTT_LOCAL_1				0x401
-
-/* SMC IND registers */
-#define	SMC_SYSCON_RESET_CNTL				0x80000000
-#       define RST_REG                                  (1 << 0)
-#define	SMC_SYSCON_CLOCK_CNTL_0				0x80000004
-#       define CK_DISABLE                               (1 << 0)
-#       define CKEN                                     (1 << 24)
-
-#define VGA_HDP_CONTROL  				0x328
-#define		VGA_MEMORY_DISABLE				(1 << 4)
-
-#define DCCG_DISP_SLOW_SELECT_REG                       0x4fc
-#define		DCCG_DISP1_SLOW_SELECT(x)		((x) << 0)
-#define		DCCG_DISP1_SLOW_SELECT_MASK		(7 << 0)
-#define		DCCG_DISP1_SLOW_SELECT_SHIFT		0
-#define		DCCG_DISP2_SLOW_SELECT(x)		((x) << 4)
-#define		DCCG_DISP2_SLOW_SELECT_MASK		(7 << 4)
-#define		DCCG_DISP2_SLOW_SELECT_SHIFT		4
-
-#define	CG_SPLL_FUNC_CNTL				0x600
-#define		SPLL_RESET				(1 << 0)
-#define		SPLL_SLEEP				(1 << 1)
-#define		SPLL_BYPASS_EN				(1 << 3)
-#define		SPLL_REF_DIV(x)				((x) << 4)
-#define		SPLL_REF_DIV_MASK			(0x3f << 4)
-#define		SPLL_PDIV_A(x)				((x) << 20)
-#define		SPLL_PDIV_A_MASK			(0x7f << 20)
-#define		SPLL_PDIV_A_SHIFT			20
-#define	CG_SPLL_FUNC_CNTL_2				0x604
-#define		SCLK_MUX_SEL(x)				((x) << 0)
-#define		SCLK_MUX_SEL_MASK			(0x1ff << 0)
-#define		SPLL_CTLREQ_CHG				(1 << 23)
-#define		SCLK_MUX_UPDATE				(1 << 26)
-#define	CG_SPLL_FUNC_CNTL_3				0x608
-#define		SPLL_FB_DIV(x)				((x) << 0)
-#define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)
-#define		SPLL_FB_DIV_SHIFT			0
-#define		SPLL_DITHEN				(1 << 28)
-#define	CG_SPLL_FUNC_CNTL_4				0x60c
-
-#define	SPLL_STATUS					0x614
-#define		SPLL_CHG_STATUS				(1 << 1)
-#define	SPLL_CNTL_MODE					0x618
-#define		SPLL_SW_DIR_CONTROL			(1 << 0)
-#	define SPLL_REFCLK_SEL(x)			((x) << 26)
-#	define SPLL_REFCLK_SEL_MASK			(3 << 26)
-
-#define	CG_SPLL_SPREAD_SPECTRUM				0x620
-#define		SSEN					(1 << 0)
-#define		CLK_S(x)				((x) << 4)
-#define		CLK_S_MASK				(0xfff << 4)
-#define		CLK_S_SHIFT				4
-#define	CG_SPLL_SPREAD_SPECTRUM_2			0x624
-#define		CLK_V(x)				((x) << 0)
-#define		CLK_V_MASK				(0x3ffffff << 0)
-#define		CLK_V_SHIFT				0
-
-#define	CG_SPLL_AUTOSCALE_CNTL				0x62c
-#       define AUTOSCALE_ON_SS_CLEAR                    (1 << 9)
-
-/* discrete uvd clocks */
-#define	CG_UPLL_FUNC_CNTL				0x634
-#	define UPLL_RESET_MASK				0x00000001
-#	define UPLL_SLEEP_MASK				0x00000002
-#	define UPLL_BYPASS_EN_MASK			0x00000004
-#	define UPLL_CTLREQ_MASK				0x00000008
-#	define UPLL_VCO_MODE_MASK			0x00000600
-#	define UPLL_REF_DIV_MASK			0x003F0000
-#	define UPLL_CTLACK_MASK				0x40000000
-#	define UPLL_CTLACK2_MASK			0x80000000
-#define	CG_UPLL_FUNC_CNTL_2				0x638
-#	define UPLL_PDIV_A(x)				((x) << 0)
-#	define UPLL_PDIV_A_MASK				0x0000007F
-#	define UPLL_PDIV_B(x)				((x) << 8)
-#	define UPLL_PDIV_B_MASK				0x00007F00
-#	define VCLK_SRC_SEL(x)				((x) << 20)
-#	define VCLK_SRC_SEL_MASK			0x01F00000
-#	define DCLK_SRC_SEL(x)				((x) << 25)
-#	define DCLK_SRC_SEL_MASK			0x3E000000
-#define	CG_UPLL_FUNC_CNTL_3				0x63C
-#	define UPLL_FB_DIV(x)				((x) << 0)
-#	define UPLL_FB_DIV_MASK				0x01FFFFFF
-#define	CG_UPLL_FUNC_CNTL_4                             0x644
-#	define UPLL_SPARE_ISPARE9			0x00020000
-#define	CG_UPLL_FUNC_CNTL_5				0x648
-#	define RESET_ANTI_MUX_MASK			0x00000200
-#define	CG_UPLL_SPREAD_SPECTRUM				0x650
-#	define SSEN_MASK				0x00000001
-
-#define	MPLL_BYPASSCLK_SEL				0x65c
-#	define MPLL_CLKOUT_SEL(x)			((x) << 8)
-#	define MPLL_CLKOUT_SEL_MASK			0xFF00
-
-#define CG_CLKPIN_CNTL                                    0x660
-#       define XTALIN_DIVIDE                              (1 << 1)
-#       define BCLK_AS_XCLK                               (1 << 2)
-#define CG_CLKPIN_CNTL_2                                  0x664
-#       define FORCE_BIF_REFCLK_EN                        (1 << 3)
-#       define MUX_TCLK_TO_XCLK                           (1 << 8)
-
-#define	THM_CLK_CNTL					0x66c
-#	define CMON_CLK_SEL(x)				((x) << 0)
-#	define CMON_CLK_SEL_MASK			0xFF
-#	define TMON_CLK_SEL(x)				((x) << 8)
-#	define TMON_CLK_SEL_MASK			0xFF00
-#define	MISC_CLK_CNTL					0x670
-#	define DEEP_SLEEP_CLK_SEL(x)			((x) << 0)
-#	define DEEP_SLEEP_CLK_SEL_MASK			0xFF
-#	define ZCLK_SEL(x)				((x) << 8)
-#	define ZCLK_SEL_MASK				0xFF00
-
-#define	CG_THERMAL_CTRL					0x700
-#define 	DPM_EVENT_SRC(x)			((x) << 0)
-#define 	DPM_EVENT_SRC_MASK			(7 << 0)
-#define		DIG_THERM_DPM(x)			((x) << 14)
-#define		DIG_THERM_DPM_MASK			0x003FC000
-#define		DIG_THERM_DPM_SHIFT			14
-#define	CG_THERMAL_STATUS				0x704
-#define		FDO_PWM_DUTY(x)				((x) << 9)
-#define		FDO_PWM_DUTY_MASK			(0xff << 9)
-#define		FDO_PWM_DUTY_SHIFT			9
-#define	CG_THERMAL_INT					0x708
-#define		DIG_THERM_INTH(x)			((x) << 8)
-#define		DIG_THERM_INTH_MASK			0x0000FF00
-#define		DIG_THERM_INTH_SHIFT			8
-#define		DIG_THERM_INTL(x)			((x) << 16)
-#define		DIG_THERM_INTL_MASK			0x00FF0000
-#define		DIG_THERM_INTL_SHIFT			16
-#define 	THERM_INT_MASK_HIGH			(1 << 24)
-#define 	THERM_INT_MASK_LOW			(1 << 25)
-
-#define	CG_MULT_THERMAL_CTRL					0x710
-#define		TEMP_SEL(x)					((x) << 20)
-#define		TEMP_SEL_MASK					(0xff << 20)
-#define		TEMP_SEL_SHIFT					20
-#define	CG_MULT_THERMAL_STATUS					0x714
-#define		ASIC_MAX_TEMP(x)				((x) << 0)
-#define		ASIC_MAX_TEMP_MASK				0x000001ff
-#define		ASIC_MAX_TEMP_SHIFT				0
-#define		CTF_TEMP(x)					((x) << 9)
-#define		CTF_TEMP_MASK					0x0003fe00
-#define		CTF_TEMP_SHIFT					9
-
-#define	CG_FDO_CTRL0					0x754
-#define		FDO_STATIC_DUTY(x)			((x) << 0)
-#define		FDO_STATIC_DUTY_MASK			0x000000FF
-#define		FDO_STATIC_DUTY_SHIFT			0
-#define	CG_FDO_CTRL1					0x758
-#define		FMAX_DUTY100(x)				((x) << 0)
-#define		FMAX_DUTY100_MASK			0x000000FF
-#define		FMAX_DUTY100_SHIFT			0
-#define	CG_FDO_CTRL2					0x75C
-#define		TMIN(x)					((x) << 0)
-#define		TMIN_MASK				0x000000FF
-#define		TMIN_SHIFT				0
-#define		FDO_PWM_MODE(x)				((x) << 11)
-#define		FDO_PWM_MODE_MASK			(7 << 11)
-#define		FDO_PWM_MODE_SHIFT			11
-#define		TACH_PWM_RESP_RATE(x)			((x) << 25)
-#define		TACH_PWM_RESP_RATE_MASK			(0x7f << 25)
-#define		TACH_PWM_RESP_RATE_SHIFT		25
-
-#define CG_TACH_CTRL                                    0x770
-#       define EDGE_PER_REV(x)                          ((x) << 0)
-#       define EDGE_PER_REV_MASK                        (0x7 << 0)
-#       define EDGE_PER_REV_SHIFT                       0
-#       define TARGET_PERIOD(x)                         ((x) << 3)
-#       define TARGET_PERIOD_MASK                       0xfffffff8
-#       define TARGET_PERIOD_SHIFT                      3
-#define CG_TACH_STATUS                                  0x774
-#       define TACH_PERIOD(x)                           ((x) << 0)
-#       define TACH_PERIOD_MASK                         0xffffffff
-#       define TACH_PERIOD_SHIFT                        0
-
-#define GENERAL_PWRMGT                                  0x780
-#       define GLOBAL_PWRMGT_EN                         (1 << 0)
-#       define STATIC_PM_EN                             (1 << 1)
-#       define THERMAL_PROTECTION_DIS                   (1 << 2)
-#       define THERMAL_PROTECTION_TYPE                  (1 << 3)
-#       define SW_SMIO_INDEX(x)                         ((x) << 6)
-#       define SW_SMIO_INDEX_MASK                       (1 << 6)
-#       define SW_SMIO_INDEX_SHIFT                      6
-#       define VOLT_PWRMGT_EN                           (1 << 10)
-#       define DYN_SPREAD_SPECTRUM_EN                   (1 << 23)
-#define CG_TPC                                            0x784
-#define SCLK_PWRMGT_CNTL                                  0x788
-#       define SCLK_PWRMGT_OFF                            (1 << 0)
-#       define SCLK_LOW_D1                                (1 << 1)
-#       define FIR_RESET                                  (1 << 4)
-#       define FIR_FORCE_TREND_SEL                        (1 << 5)
-#       define FIR_TREND_MODE                             (1 << 6)
-#       define DYN_GFX_CLK_OFF_EN                         (1 << 7)
-#       define GFX_CLK_FORCE_ON                           (1 << 8)
-#       define GFX_CLK_REQUEST_OFF                        (1 << 9)
-#       define GFX_CLK_FORCE_OFF                          (1 << 10)
-#       define GFX_CLK_OFF_ACPI_D1                        (1 << 11)
-#       define GFX_CLK_OFF_ACPI_D2                        (1 << 12)
-#       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)
-#       define DYN_LIGHT_SLEEP_EN                         (1 << 14)
-
-#define TARGET_AND_CURRENT_PROFILE_INDEX                  0x798
-#       define CURRENT_STATE_INDEX_MASK                   (0xf << 4)
-#       define CURRENT_STATE_INDEX_SHIFT                  4
-
-#define CG_FTV                                            0x7bc
-
-#define CG_FFCT_0                                         0x7c0
-#       define UTC_0(x)                                   ((x) << 0)
-#       define UTC_0_MASK                                 (0x3ff << 0)
-#       define DTC_0(x)                                   ((x) << 10)
-#       define DTC_0_MASK                                 (0x3ff << 10)
-
-#define CG_BSP                                          0x7fc
-#       define BSP(x)					((x) << 0)
-#       define BSP_MASK					(0xffff << 0)
-#       define BSU(x)					((x) << 16)
-#       define BSU_MASK					(0xf << 16)
-#define CG_AT                                           0x800
-#       define CG_R(x)					((x) << 0)
-#       define CG_R_MASK				(0xffff << 0)
-#       define CG_L(x)					((x) << 16)
-#       define CG_L_MASK				(0xffff << 16)
-
-#define CG_GIT                                          0x804
-#       define CG_GICST(x)                              ((x) << 0)
-#       define CG_GICST_MASK                            (0xffff << 0)
-#       define CG_GIPOT(x)                              ((x) << 16)
-#       define CG_GIPOT_MASK                            (0xffff << 16)
-
-#define CG_SSP                                            0x80c
-#       define SST(x)                                     ((x) << 0)
-#       define SST_MASK                                   (0xffff << 0)
-#       define SSTU(x)                                    ((x) << 16)
-#       define SSTU_MASK                                  (0xf << 16)
-
-#define CG_DISPLAY_GAP_CNTL                               0x828
-#       define DISP1_GAP(x)                               ((x) << 0)
-#       define DISP1_GAP_MASK                             (3 << 0)
-#       define DISP2_GAP(x)                               ((x) << 2)
-#       define DISP2_GAP_MASK                             (3 << 2)
-#       define VBI_TIMER_COUNT(x)                         ((x) << 4)
-#       define VBI_TIMER_COUNT_MASK                       (0x3fff << 4)
-#       define VBI_TIMER_UNIT(x)                          ((x) << 20)
-#       define VBI_TIMER_UNIT_MASK                        (7 << 20)
-#       define DISP1_GAP_MCHG(x)                          ((x) << 24)
-#       define DISP1_GAP_MCHG_MASK                        (3 << 24)
-#       define DISP2_GAP_MCHG(x)                          ((x) << 26)
-#       define DISP2_GAP_MCHG_MASK                        (3 << 26)
-
-#define	CG_ULV_CONTROL					0x878
-#define	CG_ULV_PARAMETER				0x87c
-
-#define	SMC_SCRATCH0					0x884
-
-#define	CG_CAC_CTRL					0x8b8
-#	define CAC_WINDOW(x)				((x) << 0)
-#	define CAC_WINDOW_MASK				0x00ffffff
-
-#define DMIF_ADDR_CONFIG  				0xBD4
-
-#define DMIF_ADDR_CALC  				0xC00
-
-#define	PIPE0_DMIF_BUFFER_CONTROL			  0x0ca0
-#       define DMIF_BUFFERS_ALLOCATED(x)                  ((x) << 0)
-#       define DMIF_BUFFERS_ALLOCATED_COMPLETED           (1 << 4)
-
-#define	SRBM_STATUS				        0xE50
-#define		GRBM_RQ_PENDING 			(1 << 5)
-#define		VMC_BUSY 				(1 << 8)
-#define		MCB_BUSY 				(1 << 9)
-#define		MCB_NON_DISPLAY_BUSY 			(1 << 10)
-#define		MCC_BUSY 				(1 << 11)
-#define		MCD_BUSY 				(1 << 12)
-#define		SEM_BUSY 				(1 << 14)
-#define		IH_BUSY 				(1 << 17)
-
-#define	SRBM_SOFT_RESET				        0x0E60
-#define		SOFT_RESET_BIF				(1 << 1)
-#define		SOFT_RESET_DC				(1 << 5)
-#define		SOFT_RESET_DMA1				(1 << 6)
-#define		SOFT_RESET_GRBM				(1 << 8)
-#define		SOFT_RESET_HDP				(1 << 9)
-#define		SOFT_RESET_IH				(1 << 10)
-#define		SOFT_RESET_MC				(1 << 11)
-#define		SOFT_RESET_ROM				(1 << 14)
-#define		SOFT_RESET_SEM				(1 << 15)
-#define		SOFT_RESET_VMC				(1 << 17)
-#define		SOFT_RESET_DMA				(1 << 20)
-#define		SOFT_RESET_TST				(1 << 21)
-#define		SOFT_RESET_REGBB			(1 << 22)
-#define		SOFT_RESET_ORB				(1 << 23)
-
-#define	CC_SYS_RB_BACKEND_DISABLE			0xe80
-#define	GC_USER_SYS_RB_BACKEND_DISABLE			0xe84
-
-#define SRBM_READ_ERROR					0xE98
-#define SRBM_INT_CNTL					0xEA0
-#define SRBM_INT_ACK					0xEA8
-
-#define	SRBM_STATUS2				        0x0EC4
-#define		DMA_BUSY 				(1 << 5)
-#define		DMA1_BUSY 				(1 << 6)
-
-#define VM_L2_CNTL					0x1400
-#define		ENABLE_L2_CACHE					(1 << 0)
-#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
-#define		L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)		((x) << 2)
-#define		L2_CACHE_PDE_ENDIAN_SWAP_MODE(x)		((x) << 4)
-#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)
-#define		ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE	(1 << 10)
-#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 15)
-#define		CONTEXT1_IDENTITY_ACCESS_MODE(x)		(((x) & 3) << 19)
-#define VM_L2_CNTL2					0x1404
-#define		INVALIDATE_ALL_L1_TLBS				(1 << 0)
-#define		INVALIDATE_L2_CACHE				(1 << 1)
-#define		INVALIDATE_CACHE_MODE(x)			((x) << 26)
-#define			INVALIDATE_PTE_AND_PDE_CACHES		0
-#define			INVALIDATE_ONLY_PTE_CACHES		1
-#define			INVALIDATE_ONLY_PDE_CACHES		2
-#define VM_L2_CNTL3					0x1408
-#define		BANK_SELECT(x)					((x) << 0)
-#define		L2_CACHE_UPDATE_MODE(x)				((x) << 6)
-#define		L2_CACHE_BIGK_FRAGMENT_SIZE(x)			((x) << 15)
-#define		L2_CACHE_BIGK_ASSOCIATIVITY			(1 << 20)
-#define	VM_L2_STATUS					0x140C
-#define		L2_BUSY						(1 << 0)
-#define VM_CONTEXT0_CNTL				0x1410
-#define		ENABLE_CONTEXT					(1 << 0)
-#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
-#define		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 3)
-#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
-#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT	(1 << 6)
-#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT	(1 << 7)
-#define		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 9)
-#define		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 10)
-#define		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 12)
-#define		VALID_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 13)
-#define		READ_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 15)
-#define		READ_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 16)
-#define		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 18)
-#define		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 19)
-#define		PAGE_TABLE_BLOCK_SIZE(x)			(((x) & 0xF) << 24)
-#define VM_CONTEXT1_CNTL				0x1414
-#define VM_CONTEXT0_CNTL2				0x1430
-#define VM_CONTEXT1_CNTL2				0x1434
-#define	VM_CONTEXT8_PAGE_TABLE_BASE_ADDR		0x1438
-#define	VM_CONTEXT9_PAGE_TABLE_BASE_ADDR		0x143c
-#define	VM_CONTEXT10_PAGE_TABLE_BASE_ADDR		0x1440
-#define	VM_CONTEXT11_PAGE_TABLE_BASE_ADDR		0x1444
-#define	VM_CONTEXT12_PAGE_TABLE_BASE_ADDR		0x1448
-#define	VM_CONTEXT13_PAGE_TABLE_BASE_ADDR		0x144c
-#define	VM_CONTEXT14_PAGE_TABLE_BASE_ADDR		0x1450
-#define	VM_CONTEXT15_PAGE_TABLE_BASE_ADDR		0x1454
-
-#define	VM_CONTEXT1_PROTECTION_FAULT_ADDR		0x14FC
-#define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x14DC
-#define		PROTECTIONS_MASK			(0xf << 0)
-#define		PROTECTIONS_SHIFT			0
-		/* bit 0: range
-		 * bit 1: pde0
-		 * bit 2: valid
-		 * bit 3: read
-		 * bit 4: write
-		 */
-#define		MEMORY_CLIENT_ID_MASK			(0xff << 12)
-#define		MEMORY_CLIENT_ID_SHIFT			12
-#define		MEMORY_CLIENT_RW_MASK			(1 << 24)
-#define		MEMORY_CLIENT_RW_SHIFT			24
-#define		FAULT_VMID_MASK				(0xf << 25)
-#define		FAULT_VMID_SHIFT			25
-
-#define VM_INVALIDATE_REQUEST				0x1478
-#define VM_INVALIDATE_RESPONSE				0x147c
-
-#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x1518
-#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR	0x151c
-
-#define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x153c
-#define	VM_CONTEXT1_PAGE_TABLE_BASE_ADDR		0x1540
-#define	VM_CONTEXT2_PAGE_TABLE_BASE_ADDR		0x1544
-#define	VM_CONTEXT3_PAGE_TABLE_BASE_ADDR		0x1548
-#define	VM_CONTEXT4_PAGE_TABLE_BASE_ADDR		0x154c
-#define	VM_CONTEXT5_PAGE_TABLE_BASE_ADDR		0x1550
-#define	VM_CONTEXT6_PAGE_TABLE_BASE_ADDR		0x1554
-#define	VM_CONTEXT7_PAGE_TABLE_BASE_ADDR		0x1558
-#define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x155c
-#define	VM_CONTEXT1_PAGE_TABLE_START_ADDR		0x1560
-
-#define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x157C
-#define	VM_CONTEXT1_PAGE_TABLE_END_ADDR			0x1580
-
-#define VM_L2_CG           				0x15c0
-#define		MC_CG_ENABLE				(1 << 18)
-#define		MC_LS_ENABLE				(1 << 19)
-
-#define MC_SHARED_CHMAP						0x2004
-#define		NOOFCHAN_SHIFT					12
-#define		NOOFCHAN_MASK					0x0000f000
-#define MC_SHARED_CHREMAP					0x2008
-
-#define	MC_VM_FB_LOCATION				0x2024
-#define	MC_VM_AGP_TOP					0x2028
-#define	MC_VM_AGP_BOT					0x202C
-#define	MC_VM_AGP_BASE					0x2030
-#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2034
-#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2038
-#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x203C
-
-#define	MC_VM_MX_L1_TLB_CNTL				0x2064
-#define		ENABLE_L1_TLB					(1 << 0)
-#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)
-#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)
-#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)
-#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)
-#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)
-#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)
-#define		ENABLE_ADVANCED_DRIVER_MODEL			(1 << 6)
-
-#define MC_SHARED_BLACKOUT_CNTL           		0x20ac
-
-#define MC_HUB_MISC_HUB_CG           			0x20b8
-#define MC_HUB_MISC_VM_CG           			0x20bc
-
-#define MC_HUB_MISC_SIP_CG           			0x20c0
-
-#define MC_XPB_CLK_GAT           			0x2478
-
-#define MC_CITF_MISC_RD_CG           			0x2648
-#define MC_CITF_MISC_WR_CG           			0x264c
-#define MC_CITF_MISC_VM_CG           			0x2650
-
-#define	MC_ARB_RAMCFG					0x2760
-#define		NOOFBANK_SHIFT					0
-#define		NOOFBANK_MASK					0x00000003
-#define		NOOFRANK_SHIFT					2
-#define		NOOFRANK_MASK					0x00000004
-#define		NOOFROWS_SHIFT					3
-#define		NOOFROWS_MASK					0x00000038
-#define		NOOFCOLS_SHIFT					6
-#define		NOOFCOLS_MASK					0x000000C0
-#define		CHANSIZE_SHIFT					8
-#define		CHANSIZE_MASK					0x00000100
-#define		CHANSIZE_OVERRIDE				(1 << 11)
-#define		NOOFGROUPS_SHIFT				12
-#define		NOOFGROUPS_MASK					0x00001000
-
-#define	MC_ARB_DRAM_TIMING				0x2774
-#define	MC_ARB_DRAM_TIMING2				0x2778
-
-#define MC_ARB_BURST_TIME                               0x2808
-#define		STATE0(x)				((x) << 0)
-#define		STATE0_MASK				(0x1f << 0)
-#define		STATE0_SHIFT				0
-#define		STATE1(x)				((x) << 5)
-#define		STATE1_MASK				(0x1f << 5)
-#define		STATE1_SHIFT				5
-#define		STATE2(x)				((x) << 10)
-#define		STATE2_MASK				(0x1f << 10)
-#define		STATE2_SHIFT				10
-#define		STATE3(x)				((x) << 15)
-#define		STATE3_MASK				(0x1f << 15)
-#define		STATE3_SHIFT				15
-
-#define	MC_SEQ_TRAIN_WAKEUP_CNTL			0x28e8
-#define		TRAIN_DONE_D0      			(1 << 30)
-#define		TRAIN_DONE_D1      			(1 << 31)
-
-#define MC_SEQ_SUP_CNTL           			0x28c8
-#define		RUN_MASK      				(1 << 0)
-#define MC_SEQ_SUP_PGM           			0x28cc
-#define MC_PMG_AUTO_CMD           			0x28d0
-
-#define MC_IO_PAD_CNTL_D0           			0x29d0
-#define		MEM_FALL_OUT_CMD      			(1 << 8)
-
-#define MC_SEQ_RAS_TIMING                               0x28a0
-#define MC_SEQ_CAS_TIMING                               0x28a4
-#define MC_SEQ_MISC_TIMING                              0x28a8
-#define MC_SEQ_MISC_TIMING2                             0x28ac
-#define MC_SEQ_PMG_TIMING                               0x28b0
-#define MC_SEQ_RD_CTL_D0                                0x28b4
-#define MC_SEQ_RD_CTL_D1                                0x28b8
-#define MC_SEQ_WR_CTL_D0                                0x28bc
-#define MC_SEQ_WR_CTL_D1                                0x28c0
-
-#define MC_SEQ_MISC0           				0x2a00
-#define 	MC_SEQ_MISC0_VEN_ID_SHIFT               8
-#define 	MC_SEQ_MISC0_VEN_ID_MASK                0x00000f00
-#define 	MC_SEQ_MISC0_VEN_ID_VALUE               3
-#define 	MC_SEQ_MISC0_REV_ID_SHIFT               12
-#define 	MC_SEQ_MISC0_REV_ID_MASK                0x0000f000
-#define 	MC_SEQ_MISC0_REV_ID_VALUE               1
-#define 	MC_SEQ_MISC0_GDDR5_SHIFT                28
-#define 	MC_SEQ_MISC0_GDDR5_MASK                 0xf0000000
-#define 	MC_SEQ_MISC0_GDDR5_VALUE                5
-#define MC_SEQ_MISC1                                    0x2a04
-#define MC_SEQ_RESERVE_M                                0x2a08
-#define MC_PMG_CMD_EMRS                                 0x2a0c
-
-#define MC_SEQ_IO_DEBUG_INDEX           		0x2a44
-#define MC_SEQ_IO_DEBUG_DATA           			0x2a48
-
-#define MC_SEQ_MISC5                                    0x2a54
-#define MC_SEQ_MISC6                                    0x2a58
-
-#define MC_SEQ_MISC7                                    0x2a64
-
-#define MC_SEQ_RAS_TIMING_LP                            0x2a6c
-#define MC_SEQ_CAS_TIMING_LP                            0x2a70
-#define MC_SEQ_MISC_TIMING_LP                           0x2a74
-#define MC_SEQ_MISC_TIMING2_LP                          0x2a78
-#define MC_SEQ_WR_CTL_D0_LP                             0x2a7c
-#define MC_SEQ_WR_CTL_D1_LP                             0x2a80
-#define MC_SEQ_PMG_CMD_EMRS_LP                          0x2a84
-#define MC_SEQ_PMG_CMD_MRS_LP                           0x2a88
-
-#define MC_PMG_CMD_MRS                                  0x2aac
-
-#define MC_SEQ_RD_CTL_D0_LP                             0x2b1c
-#define MC_SEQ_RD_CTL_D1_LP                             0x2b20
-
-#define MC_PMG_CMD_MRS1                                 0x2b44
-#define MC_SEQ_PMG_CMD_MRS1_LP                          0x2b48
-#define MC_SEQ_PMG_TIMING_LP                            0x2b4c
-
-#define MC_SEQ_WR_CTL_2                                 0x2b54
-#define MC_SEQ_WR_CTL_2_LP                              0x2b58
-#define MC_PMG_CMD_MRS2                                 0x2b5c
-#define MC_SEQ_PMG_CMD_MRS2_LP                          0x2b60
-
-#define	MCLK_PWRMGT_CNTL				0x2ba0
-#       define DLL_SPEED(x)				((x) << 0)
-#       define DLL_SPEED_MASK				(0x1f << 0)
-#       define DLL_READY                                (1 << 6)
-#       define MC_INT_CNTL                              (1 << 7)
-#       define MRDCK0_PDNB                              (1 << 8)
-#       define MRDCK1_PDNB                              (1 << 9)
-#       define MRDCK0_RESET                             (1 << 16)
-#       define MRDCK1_RESET                             (1 << 17)
-#       define DLL_READY_READ                           (1 << 24)
-#define	DLL_CNTL					0x2ba4
-#       define MRDCK0_BYPASS                            (1 << 24)
-#       define MRDCK1_BYPASS                            (1 << 25)
-
-#define	MPLL_CNTL_MODE					0x2bb0
-#       define MPLL_MCLK_SEL                            (1 << 11)
-#define	MPLL_FUNC_CNTL					0x2bb4
-#define		BWCTRL(x)				((x) << 20)
-#define		BWCTRL_MASK				(0xff << 20)
-#define	MPLL_FUNC_CNTL_1				0x2bb8
-#define		VCO_MODE(x)				((x) << 0)
-#define		VCO_MODE_MASK				(3 << 0)
-#define		CLKFRAC(x)				((x) << 4)
-#define		CLKFRAC_MASK				(0xfff << 4)
-#define		CLKF(x)					((x) << 16)
-#define		CLKF_MASK				(0xfff << 16)
-#define	MPLL_FUNC_CNTL_2				0x2bbc
-#define	MPLL_AD_FUNC_CNTL				0x2bc0
-#define		YCLK_POST_DIV(x)			((x) << 0)
-#define		YCLK_POST_DIV_MASK			(7 << 0)
-#define	MPLL_DQ_FUNC_CNTL				0x2bc4
-#define		YCLK_SEL(x)				((x) << 4)
-#define		YCLK_SEL_MASK				(1 << 4)
-
-#define	MPLL_SS1					0x2bcc
-#define		CLKV(x)					((x) << 0)
-#define		CLKV_MASK				(0x3ffffff << 0)
-#define	MPLL_SS2					0x2bd0
-#define		CLKS(x)					((x) << 0)
-#define		CLKS_MASK				(0xfff << 0)
-
-#define	HDP_HOST_PATH_CNTL				0x2C00
-#define 	CLOCK_GATING_DIS			(1 << 23)
-#define	HDP_NONSURFACE_BASE				0x2C04
-#define	HDP_NONSURFACE_INFO				0x2C08
-#define	HDP_NONSURFACE_SIZE				0x2C0C
-
-#define HDP_ADDR_CONFIG  				0x2F48
-#define HDP_MISC_CNTL					0x2F4C
-#define 	HDP_FLUSH_INVALIDATE_CACHE			(1 << 0)
-#define HDP_MEM_POWER_LS				0x2F50
-#define 	HDP_LS_ENABLE				(1 << 0)
-
-#define ATC_MISC_CG           				0x3350
-
-#define IH_RB_CNTL                                        0x3e00
-#       define IH_RB_ENABLE                               (1 << 0)
-#       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */
-#       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
-#       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
-#       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
-#       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
-#       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)
-#define IH_RB_BASE                                        0x3e04
-#define IH_RB_RPTR                                        0x3e08
-#define IH_RB_WPTR                                        0x3e0c
-#       define RB_OVERFLOW                                (1 << 0)
-#       define WPTR_OFFSET_MASK                           0x3fffc
-#define IH_RB_WPTR_ADDR_HI                                0x3e10
-#define IH_RB_WPTR_ADDR_LO                                0x3e14
-#define IH_CNTL                                           0x3e18
-#       define ENABLE_INTR                                (1 << 0)
-#       define IH_MC_SWAP(x)                              ((x) << 1)
-#       define IH_MC_SWAP_NONE                            0
-#       define IH_MC_SWAP_16BIT                           1
-#       define IH_MC_SWAP_32BIT                           2
-#       define IH_MC_SWAP_64BIT                           3
-#       define RPTR_REARM                                 (1 << 4)
-#       define MC_WRREQ_CREDIT(x)                         ((x) << 15)
-#       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)
-#       define MC_VMID(x)                                 ((x) << 25)
-
-#define	CONFIG_MEMSIZE					0x5428
-
-#define INTERRUPT_CNTL                                    0x5468
-#       define IH_DUMMY_RD_OVERRIDE                       (1 << 0)
-#       define IH_DUMMY_RD_EN                             (1 << 1)
-#       define IH_REQ_NONSNOOP_EN                         (1 << 3)
-#       define GEN_IH_INT_EN                              (1 << 8)
-#define INTERRUPT_CNTL2                                   0x546c
-
-#define HDP_MEM_COHERENCY_FLUSH_CNTL			0x5480
-
-#define	BIF_FB_EN						0x5490
-#define		FB_READ_EN					(1 << 0)
-#define		FB_WRITE_EN					(1 << 1)
-
-#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0
-
-/* DCE6 ELD audio interface */
-#define AZ_F0_CODEC_ENDPOINT_INDEX                       0x5E00
-#       define AZ_ENDPOINT_REG_INDEX(x)                  (((x) & 0xff) << 0)
-#       define AZ_ENDPOINT_REG_WRITE_EN                  (1 << 8)
-#define AZ_F0_CODEC_ENDPOINT_DATA                        0x5E04
-
-#define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER          0x25
-#define		SPEAKER_ALLOCATION(x)			(((x) & 0x7f) << 0)
-#define		SPEAKER_ALLOCATION_MASK			(0x7f << 0)
-#define		SPEAKER_ALLOCATION_SHIFT		0
-#define		HDMI_CONNECTION				(1 << 16)
-#define		DP_CONNECTION				(1 << 17)
-
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0        0x28 /* LPCM */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1        0x29 /* AC3 */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2        0x2A /* MPEG1 */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3        0x2B /* MP3 */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4        0x2C /* MPEG2 */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5        0x2D /* AAC */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6        0x2E /* DTS */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7        0x2F /* ATRAC */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8        0x30 /* one bit audio - leave at 0 (default) */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9        0x31 /* Dolby Digital */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10       0x32 /* DTS-HD */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11       0x33 /* MAT-MLP */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12       0x34 /* DTS */
-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13       0x35 /* WMA Pro */
-#       define MAX_CHANNELS(x)                            (((x) & 0x7) << 0)
-/* max channels minus one.  7 = 8 channels */
-#       define SUPPORTED_FREQUENCIES(x)                   (((x) & 0xff) << 8)
-#       define DESCRIPTOR_BYTE_2(x)                       (((x) & 0xff) << 16)
-#       define SUPPORTED_FREQUENCIES_STEREO(x)            (((x) & 0xff) << 24) /* LPCM only */
-/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
- * bit0 = 32 kHz
- * bit1 = 44.1 kHz
- * bit2 = 48 kHz
- * bit3 = 88.2 kHz
- * bit4 = 96 kHz
- * bit5 = 176.4 kHz
- * bit6 = 192 kHz
- */
-
-#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC         0x37
-#       define VIDEO_LIPSYNC(x)                           (((x) & 0xff) << 0)
-#       define AUDIO_LIPSYNC(x)                           (((x) & 0xff) << 8)
-/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
- * 0   = invalid
- * x   = legal delay value
- * 255 = sync not supported
- */
-#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR             0x38
-#       define HBR_CAPABLE                                (1 << 0) /* enabled by default */
-
-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0               0x3a
-#       define MANUFACTURER_ID(x)                        (((x) & 0xffff) << 0)
-#       define PRODUCT_ID(x)                             (((x) & 0xffff) << 16)
-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1               0x3b
-#       define SINK_DESCRIPTION_LEN(x)                   (((x) & 0xff) << 0)
-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2               0x3c
-#       define PORT_ID0(x)                               (((x) & 0xffffffff) << 0)
-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3               0x3d
-#       define PORT_ID1(x)                               (((x) & 0xffffffff) << 0)
-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4               0x3e
-#       define DESCRIPTION0(x)                           (((x) & 0xff) << 0)
-#       define DESCRIPTION1(x)                           (((x) & 0xff) << 8)
-#       define DESCRIPTION2(x)                           (((x) & 0xff) << 16)
-#       define DESCRIPTION3(x)                           (((x) & 0xff) << 24)
-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5               0x3f
-#       define DESCRIPTION4(x)                           (((x) & 0xff) << 0)
-#       define DESCRIPTION5(x)                           (((x) & 0xff) << 8)
-#       define DESCRIPTION6(x)                           (((x) & 0xff) << 16)
-#       define DESCRIPTION7(x)                           (((x) & 0xff) << 24)
-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6               0x40
-#       define DESCRIPTION8(x)                           (((x) & 0xff) << 0)
-#       define DESCRIPTION9(x)                           (((x) & 0xff) << 8)
-#       define DESCRIPTION10(x)                          (((x) & 0xff) << 16)
-#       define DESCRIPTION11(x)                          (((x) & 0xff) << 24)
-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7               0x41
-#       define DESCRIPTION12(x)                          (((x) & 0xff) << 0)
-#       define DESCRIPTION13(x)                          (((x) & 0xff) << 8)
-#       define DESCRIPTION14(x)                          (((x) & 0xff) << 16)
-#       define DESCRIPTION15(x)                          (((x) & 0xff) << 24)
-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8               0x42
-#       define DESCRIPTION16(x)                          (((x) & 0xff) << 0)
-#       define DESCRIPTION17(x)                          (((x) & 0xff) << 8)
-
-#define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL         0x54
-#       define AUDIO_ENABLED                             (1 << 31)
-
-#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT  0x56
-#define		PORT_CONNECTIVITY_MASK				(3 << 30)
-#define		PORT_CONNECTIVITY_SHIFT				30
-
-#define	DC_LB_MEMORY_SPLIT					0x6b0c
-#define		DC_LB_MEMORY_CONFIG(x)				((x) << 20)
-
-#define	PRIORITY_A_CNT						0x6b18
-#define		PRIORITY_MARK_MASK				0x7fff
-#define		PRIORITY_OFF					(1 << 16)
-#define		PRIORITY_ALWAYS_ON				(1 << 20)
-#define	PRIORITY_B_CNT						0x6b1c
-
-#define	DPG_PIPE_ARBITRATION_CONTROL3				0x6cc8
-#       define LATENCY_WATERMARK_MASK(x)			((x) << 16)
-#define	DPG_PIPE_LATENCY_CONTROL				0x6ccc
-#       define LATENCY_LOW_WATERMARK(x)				((x) << 0)
-#       define LATENCY_HIGH_WATERMARK(x)			((x) << 16)
-
-/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
-#define VLINE_STATUS                                    0x6bb8
-#       define VLINE_OCCURRED                           (1 << 0)
-#       define VLINE_ACK                                (1 << 4)
-#       define VLINE_STAT                               (1 << 12)
-#       define VLINE_INTERRUPT                          (1 << 16)
-#       define VLINE_INTERRUPT_TYPE                     (1 << 17)
-/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
-#define VBLANK_STATUS                                   0x6bbc
-#       define VBLANK_OCCURRED                          (1 << 0)
-#       define VBLANK_ACK                               (1 << 4)
-#       define VBLANK_STAT                              (1 << 12)
-#       define VBLANK_INTERRUPT                         (1 << 16)
-#       define VBLANK_INTERRUPT_TYPE                    (1 << 17)
-
-/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
-#define INT_MASK                                        0x6b40
-#       define VBLANK_INT_MASK                          (1 << 0)
-#       define VLINE_INT_MASK                           (1 << 4)
-
-#define DISP_INTERRUPT_STATUS                           0x60f4
-#       define LB_D1_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D1_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD1_INTERRUPT                        (1 << 17)
-#       define DC_HPD1_RX_INTERRUPT                     (1 << 18)
-#       define DACA_AUTODETECT_INTERRUPT                (1 << 22)
-#       define DACB_AUTODETECT_INTERRUPT                (1 << 23)
-#       define DC_I2C_SW_DONE_INTERRUPT                 (1 << 24)
-#       define DC_I2C_HW_DONE_INTERRUPT                 (1 << 25)
-#define DISP_INTERRUPT_STATUS_CONTINUE                  0x60f8
-#       define LB_D2_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D2_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD2_INTERRUPT                        (1 << 17)
-#       define DC_HPD2_RX_INTERRUPT                     (1 << 18)
-#       define DISP_TIMER_INTERRUPT                     (1 << 24)
-#define DISP_INTERRUPT_STATUS_CONTINUE2                 0x60fc
-#       define LB_D3_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D3_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD3_INTERRUPT                        (1 << 17)
-#       define DC_HPD3_RX_INTERRUPT                     (1 << 18)
-#define DISP_INTERRUPT_STATUS_CONTINUE3                 0x6100
-#       define LB_D4_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D4_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD4_INTERRUPT                        (1 << 17)
-#       define DC_HPD4_RX_INTERRUPT                     (1 << 18)
-#define DISP_INTERRUPT_STATUS_CONTINUE4                 0x614c
-#       define LB_D5_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD5_INTERRUPT                        (1 << 17)
-#       define DC_HPD5_RX_INTERRUPT                     (1 << 18)
-#define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6150
-#       define LB_D6_VLINE_INTERRUPT                    (1 << 2)
-#       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)
-#       define DC_HPD6_INTERRUPT                        (1 << 17)
-#       define DC_HPD6_RX_INTERRUPT                     (1 << 18)
-
-/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
-#define GRPH_INT_STATUS                                 0x6858
-#       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
-#       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
-/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
-#define	GRPH_INT_CONTROL			        0x685c
-#       define GRPH_PFLIP_INT_MASK                      (1 << 0)
-#       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
-
-#define	DAC_AUTODETECT_INT_CONTROL			0x67c8
-
-#define DC_HPD1_INT_STATUS                              0x601c
-#define DC_HPD2_INT_STATUS                              0x6028
-#define DC_HPD3_INT_STATUS                              0x6034
-#define DC_HPD4_INT_STATUS                              0x6040
-#define DC_HPD5_INT_STATUS                              0x604c
-#define DC_HPD6_INT_STATUS                              0x6058
-#       define DC_HPDx_INT_STATUS                       (1 << 0)
-#       define DC_HPDx_SENSE                            (1 << 1)
-#       define DC_HPDx_RX_INT_STATUS                    (1 << 8)
-
-#define DC_HPD1_INT_CONTROL                             0x6020
-#define DC_HPD2_INT_CONTROL                             0x602c
-#define DC_HPD3_INT_CONTROL                             0x6038
-#define DC_HPD4_INT_CONTROL                             0x6044
-#define DC_HPD5_INT_CONTROL                             0x6050
-#define DC_HPD6_INT_CONTROL                             0x605c
-#       define DC_HPDx_INT_ACK                          (1 << 0)
-#       define DC_HPDx_INT_POLARITY                     (1 << 8)
-#       define DC_HPDx_INT_EN                           (1 << 16)
-#       define DC_HPDx_RX_INT_ACK                       (1 << 20)
-#       define DC_HPDx_RX_INT_EN                        (1 << 24)
-
-#define DC_HPD1_CONTROL                                   0x6024
-#define DC_HPD2_CONTROL                                   0x6030
-#define DC_HPD3_CONTROL                                   0x603c
-#define DC_HPD4_CONTROL                                   0x6048
-#define DC_HPD5_CONTROL                                   0x6054
-#define DC_HPD6_CONTROL                                   0x6060
-#       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)
-#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
-#       define DC_HPDx_EN                                 (1 << 28)
-
-#define DPG_PIPE_STUTTER_CONTROL                          0x6cd4
-#       define STUTTER_ENABLE                             (1 << 0)
-
-/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
-#define CRTC_STATUS_FRAME_COUNT                         0x6e98
-
-/* Audio clocks */
-#define DCCG_AUDIO_DTO_SOURCE                           0x05ac
-#       define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
-#       define DCCG_AUDIO_DTO_SEL            (1 << 4)   /* 0=dto0 1=dto1 */
-
-#define DCCG_AUDIO_DTO0_PHASE                           0x05b0
-#define DCCG_AUDIO_DTO0_MODULE                          0x05b4
-#define DCCG_AUDIO_DTO1_PHASE                           0x05c0
-#define DCCG_AUDIO_DTO1_MODULE                          0x05c4
-
-#define DENTIST_DISPCLK_CNTL				0x0490
-#	define DENTIST_DPREFCLK_WDIVIDER(x)		(((x) & 0x7f) << 24)
-#	define DENTIST_DPREFCLK_WDIVIDER_MASK		(0x7f << 24)
-#	define DENTIST_DPREFCLK_WDIVIDER_SHIFT		24
-
-#define AFMT_AUDIO_SRC_CONTROL                          0x713c
-#define		AFMT_AUDIO_SRC_SELECT(x)		(((x) & 7) << 0)
-/* AFMT_AUDIO_SRC_SELECT
- * 0 = stream0
- * 1 = stream1
- * 2 = stream2
- * 3 = stream3
- * 4 = stream4
- * 5 = stream5
- */
-
-#define	GRBM_CNTL					0x8000
-#define		GRBM_READ_TIMEOUT(x)				((x) << 0)
-
-#define	GRBM_STATUS2					0x8008
-#define		RLC_RQ_PENDING 					(1 << 0)
-#define		RLC_BUSY 					(1 << 8)
-#define		TC_BUSY 					(1 << 9)
-
-#define	GRBM_STATUS					0x8010
-#define		CMDFIFO_AVAIL_MASK				0x0000000F
-#define		RING2_RQ_PENDING				(1 << 4)
-#define		SRBM_RQ_PENDING					(1 << 5)
-#define		RING1_RQ_PENDING				(1 << 6)
-#define		CF_RQ_PENDING					(1 << 7)
-#define		PF_RQ_PENDING					(1 << 8)
-#define		GDS_DMA_RQ_PENDING				(1 << 9)
-#define		GRBM_EE_BUSY					(1 << 10)
-#define		DB_CLEAN					(1 << 12)
-#define		CB_CLEAN					(1 << 13)
-#define		TA_BUSY 					(1 << 14)
-#define		GDS_BUSY 					(1 << 15)
-#define		VGT_BUSY					(1 << 17)
-#define		IA_BUSY_NO_DMA					(1 << 18)
-#define		IA_BUSY						(1 << 19)
-#define		SX_BUSY 					(1 << 20)
-#define		SPI_BUSY					(1 << 22)
-#define		BCI_BUSY					(1 << 23)
-#define		SC_BUSY 					(1 << 24)
-#define		PA_BUSY 					(1 << 25)
-#define		DB_BUSY 					(1 << 26)
-#define		CP_COHERENCY_BUSY      				(1 << 28)
-#define		CP_BUSY 					(1 << 29)
-#define		CB_BUSY 					(1 << 30)
-#define		GUI_ACTIVE					(1 << 31)
-#define	GRBM_STATUS_SE0					0x8014
-#define	GRBM_STATUS_SE1					0x8018
-#define		SE_DB_CLEAN					(1 << 1)
-#define		SE_CB_CLEAN					(1 << 2)
-#define		SE_BCI_BUSY					(1 << 22)
-#define		SE_VGT_BUSY					(1 << 23)
-#define		SE_PA_BUSY					(1 << 24)
-#define		SE_TA_BUSY					(1 << 25)
-#define		SE_SX_BUSY					(1 << 26)
-#define		SE_SPI_BUSY					(1 << 27)
-#define		SE_SC_BUSY					(1 << 29)
-#define		SE_DB_BUSY					(1 << 30)
-#define		SE_CB_BUSY					(1 << 31)
-
-#define	GRBM_SOFT_RESET					0x8020
-#define		SOFT_RESET_CP					(1 << 0)
-#define		SOFT_RESET_CB					(1 << 1)
-#define		SOFT_RESET_RLC					(1 << 2)
-#define		SOFT_RESET_DB					(1 << 3)
-#define		SOFT_RESET_GDS					(1 << 4)
-#define		SOFT_RESET_PA					(1 << 5)
-#define		SOFT_RESET_SC					(1 << 6)
-#define		SOFT_RESET_BCI					(1 << 7)
-#define		SOFT_RESET_SPI					(1 << 8)
-#define		SOFT_RESET_SX					(1 << 10)
-#define		SOFT_RESET_TC					(1 << 11)
-#define		SOFT_RESET_TA					(1 << 12)
-#define		SOFT_RESET_VGT					(1 << 14)
-#define		SOFT_RESET_IA					(1 << 15)
-
-#define GRBM_GFX_INDEX          			0x802C
-#define		INSTANCE_INDEX(x)			((x) << 0)
-#define		SH_INDEX(x)     			((x) << 8)
-#define		SE_INDEX(x)     			((x) << 16)
-#define		SH_BROADCAST_WRITES      		(1 << 29)
-#define		INSTANCE_BROADCAST_WRITES      		(1 << 30)
-#define		SE_BROADCAST_WRITES      		(1 << 31)
-
-#define GRBM_INT_CNTL                                   0x8060
-#       define RDERR_INT_ENABLE                         (1 << 0)
-#       define GUI_IDLE_INT_ENABLE                      (1 << 19)
-
-#define	CP_STRMOUT_CNTL					0x84FC
-#define	SCRATCH_REG0					0x8500
-#define	SCRATCH_REG1					0x8504
-#define	SCRATCH_REG2					0x8508
-#define	SCRATCH_REG3					0x850C
-#define	SCRATCH_REG4					0x8510
-#define	SCRATCH_REG5					0x8514
-#define	SCRATCH_REG6					0x8518
-#define	SCRATCH_REG7					0x851C
-
-#define	SCRATCH_UMSK					0x8540
-#define	SCRATCH_ADDR					0x8544
-
-#define	CP_SEM_WAIT_TIMER				0x85BC
-
-#define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x85C8
-
-#define CP_ME_CNTL					0x86D8
-#define		CP_CE_HALT					(1 << 24)
-#define		CP_PFP_HALT					(1 << 26)
-#define		CP_ME_HALT					(1 << 28)
-
-#define	CP_COHER_CNTL2					0x85E8
-
-#define	CP_RB2_RPTR					0x86f8
-#define	CP_RB1_RPTR					0x86fc
-#define	CP_RB0_RPTR					0x8700
-#define	CP_RB_WPTR_DELAY				0x8704
-
-#define	CP_QUEUE_THRESHOLDS				0x8760
-#define		ROQ_IB1_START(x)				((x) << 0)
-#define		ROQ_IB2_START(x)				((x) << 8)
-#define CP_MEQ_THRESHOLDS				0x8764
-#define		MEQ1_START(x)				((x) << 0)
-#define		MEQ2_START(x)				((x) << 8)
-
-#define	CP_PERFMON_CNTL					0x87FC
-
-#define	VGT_VTX_VECT_EJECT_REG				0x88B0
-
-#define	VGT_CACHE_INVALIDATION				0x88C4
-#define		CACHE_INVALIDATION(x)				((x) << 0)
-#define			VC_ONLY						0
-#define			TC_ONLY						1
-#define			VC_AND_TC					2
-#define		AUTO_INVLD_EN(x)				((x) << 6)
-#define			NO_AUTO						0
-#define			ES_AUTO						1
-#define			GS_AUTO						2
-#define			ES_AND_GS_AUTO					3
-#define	VGT_ESGS_RING_SIZE				0x88C8
-#define	VGT_GSVS_RING_SIZE				0x88CC
-
-#define	VGT_GS_VERTEX_REUSE				0x88D4
-
-#define	VGT_PRIMITIVE_TYPE				0x8958
-#define	VGT_INDEX_TYPE					0x895C
-
-#define	VGT_NUM_INDICES					0x8970
-#define	VGT_NUM_INSTANCES				0x8974
-
-#define	VGT_TF_RING_SIZE				0x8988
-
-#define	VGT_HS_OFFCHIP_PARAM				0x89B0
-
-#define	VGT_TF_MEMORY_BASE				0x89B8
-
-#define CC_GC_SHADER_ARRAY_CONFIG			0x89bc
-#define		INACTIVE_CUS_MASK			0xFFFF0000
-#define		INACTIVE_CUS_SHIFT			16
-#define GC_USER_SHADER_ARRAY_CONFIG			0x89c0
-
-#define	PA_CL_ENHANCE					0x8A14
-#define		CLIP_VTX_REORDER_ENA				(1 << 0)
-#define		NUM_CLIP_SEQ(x)					((x) << 1)
-
-#define	PA_SU_LINE_STIPPLE_VALUE			0x8A60
-
-#define	PA_SC_LINE_STIPPLE_STATE			0x8B10
-
-#define	PA_SC_FORCE_EOV_MAX_CNTS			0x8B24
-#define		FORCE_EOV_MAX_CLK_CNT(x)			((x) << 0)
-#define		FORCE_EOV_MAX_REZ_CNT(x)			((x) << 16)
-
-#define	PA_SC_FIFO_SIZE					0x8BCC
-#define		SC_FRONTEND_PRIM_FIFO_SIZE(x)			((x) << 0)
-#define		SC_BACKEND_PRIM_FIFO_SIZE(x)			((x) << 6)
-#define		SC_HIZ_TILE_FIFO_SIZE(x)			((x) << 15)
-#define		SC_EARLYZ_TILE_FIFO_SIZE(x)			((x) << 23)
-
-#define	PA_SC_ENHANCE					0x8BF0
-
-#define	SQ_CONFIG					0x8C00
-
-#define	SQC_CACHES					0x8C08
-
-#define SQ_POWER_THROTTLE                               0x8e58
-#define		MIN_POWER(x)				((x) << 0)
-#define		MIN_POWER_MASK				(0x3fff << 0)
-#define		MIN_POWER_SHIFT				0
-#define		MAX_POWER(x)				((x) << 16)
-#define		MAX_POWER_MASK				(0x3fff << 16)
-#define		MAX_POWER_SHIFT				0
-#define SQ_POWER_THROTTLE2                              0x8e5c
-#define		MAX_POWER_DELTA(x)			((x) << 0)
-#define		MAX_POWER_DELTA_MASK			(0x3fff << 0)
-#define		MAX_POWER_DELTA_SHIFT			0
-#define		STI_SIZE(x)				((x) << 16)
-#define		STI_SIZE_MASK				(0x3ff << 16)
-#define		STI_SIZE_SHIFT				16
-#define		LTI_RATIO(x)				((x) << 27)
-#define		LTI_RATIO_MASK				(0xf << 27)
-#define		LTI_RATIO_SHIFT				27
-
-#define	SX_DEBUG_1					0x9060
-
-#define	SPI_STATIC_THREAD_MGMT_1			0x90E0
-#define	SPI_STATIC_THREAD_MGMT_2			0x90E4
-#define	SPI_STATIC_THREAD_MGMT_3			0x90E8
-#define	SPI_PS_MAX_WAVE_ID				0x90EC
-
-#define	SPI_CONFIG_CNTL					0x9100
-
-#define	SPI_CONFIG_CNTL_1				0x913C
-#define		VTX_DONE_DELAY(x)				((x) << 0)
-#define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)
-
-#define	CGTS_TCC_DISABLE				0x9148
-#define	CGTS_USER_TCC_DISABLE				0x914C
-#define		TCC_DISABLE_MASK				0xFFFF0000
-#define		TCC_DISABLE_SHIFT				16
-#define	CGTS_SM_CTRL_REG				0x9150
-#define		OVERRIDE				(1 << 21)
-#define		LS_OVERRIDE				(1 << 22)
-
-#define	SPI_LB_CU_MASK					0x9354
-
-#define	TA_CNTL_AUX					0x9508
-#define	TA_CS_BC_BASE_ADDR				0x950C
-
-#define CC_RB_BACKEND_DISABLE				0x98F4
-#define		BACKEND_DISABLE(x)     			((x) << 16)
-#define GB_ADDR_CONFIG  				0x98F8
-#define		NUM_PIPES(x)				((x) << 0)
-#define		NUM_PIPES_MASK				0x00000007
-#define		NUM_PIPES_SHIFT				0
-#define		PIPE_INTERLEAVE_SIZE(x)			((x) << 4)
-#define		PIPE_INTERLEAVE_SIZE_MASK		0x00000070
-#define		PIPE_INTERLEAVE_SIZE_SHIFT		4
-#define		NUM_SHADER_ENGINES(x)			((x) << 12)
-#define		NUM_SHADER_ENGINES_MASK			0x00003000
-#define		NUM_SHADER_ENGINES_SHIFT		12
-#define		SHADER_ENGINE_TILE_SIZE(x)     		((x) << 16)
-#define		SHADER_ENGINE_TILE_SIZE_MASK		0x00070000
-#define		SHADER_ENGINE_TILE_SIZE_SHIFT		16
-#define		NUM_GPUS(x)     			((x) << 20)
-#define		NUM_GPUS_MASK				0x00700000
-#define		NUM_GPUS_SHIFT				20
-#define		MULTI_GPU_TILE_SIZE(x)     		((x) << 24)
-#define		MULTI_GPU_TILE_SIZE_MASK		0x03000000
-#define		MULTI_GPU_TILE_SIZE_SHIFT		24
-#define		ROW_SIZE(x)             		((x) << 28)
-#define		ROW_SIZE_MASK				0x30000000
-#define		ROW_SIZE_SHIFT				28
-
-#define	GB_TILE_MODE0					0x9910
-#       define MICRO_TILE_MODE(x)				((x) << 0)
-#              define	ADDR_SURF_DISPLAY_MICRO_TILING		0
-#              define	ADDR_SURF_THIN_MICRO_TILING		1
-#              define	ADDR_SURF_DEPTH_MICRO_TILING		2
-#       define ARRAY_MODE(x)					((x) << 2)
-#              define	ARRAY_LINEAR_GENERAL			0
-#              define	ARRAY_LINEAR_ALIGNED			1
-#              define	ARRAY_1D_TILED_THIN1			2
-#              define	ARRAY_2D_TILED_THIN1			4
-#       define PIPE_CONFIG(x)					((x) << 6)
-#              define	ADDR_SURF_P2				0
-#              define	ADDR_SURF_P4_8x16			4
-#              define	ADDR_SURF_P4_16x16			5
-#              define	ADDR_SURF_P4_16x32			6
-#              define	ADDR_SURF_P4_32x32			7
-#              define	ADDR_SURF_P8_16x16_8x16			8
-#              define	ADDR_SURF_P8_16x32_8x16			9
-#              define	ADDR_SURF_P8_32x32_8x16			10
-#              define	ADDR_SURF_P8_16x32_16x16		11
-#              define	ADDR_SURF_P8_32x32_16x16		12
-#              define	ADDR_SURF_P8_32x32_16x32		13
-#              define	ADDR_SURF_P8_32x64_32x32		14
-#       define TILE_SPLIT(x)					((x) << 11)
-#              define	ADDR_SURF_TILE_SPLIT_64B		0
-#              define	ADDR_SURF_TILE_SPLIT_128B		1
-#              define	ADDR_SURF_TILE_SPLIT_256B		2
-#              define	ADDR_SURF_TILE_SPLIT_512B		3
-#              define	ADDR_SURF_TILE_SPLIT_1KB		4
-#              define	ADDR_SURF_TILE_SPLIT_2KB		5
-#              define	ADDR_SURF_TILE_SPLIT_4KB		6
-#       define BANK_WIDTH(x)					((x) << 14)
-#              define	ADDR_SURF_BANK_WIDTH_1			0
-#              define	ADDR_SURF_BANK_WIDTH_2			1
-#              define	ADDR_SURF_BANK_WIDTH_4			2
-#              define	ADDR_SURF_BANK_WIDTH_8			3
-#       define BANK_HEIGHT(x)					((x) << 16)
-#              define	ADDR_SURF_BANK_HEIGHT_1			0
-#              define	ADDR_SURF_BANK_HEIGHT_2			1
-#              define	ADDR_SURF_BANK_HEIGHT_4			2
-#              define	ADDR_SURF_BANK_HEIGHT_8			3
-#       define MACRO_TILE_ASPECT(x)				((x) << 18)
-#              define	ADDR_SURF_MACRO_ASPECT_1		0
-#              define	ADDR_SURF_MACRO_ASPECT_2		1
-#              define	ADDR_SURF_MACRO_ASPECT_4		2
-#              define	ADDR_SURF_MACRO_ASPECT_8		3
-#       define NUM_BANKS(x)					((x) << 20)
-#              define	ADDR_SURF_2_BANK			0
-#              define	ADDR_SURF_4_BANK			1
-#              define	ADDR_SURF_8_BANK			2
-#              define	ADDR_SURF_16_BANK			3
-
-#define	CB_PERFCOUNTER0_SELECT0				0x9a20
-#define	CB_PERFCOUNTER0_SELECT1				0x9a24
-#define	CB_PERFCOUNTER1_SELECT0				0x9a28
-#define	CB_PERFCOUNTER1_SELECT1				0x9a2c
-#define	CB_PERFCOUNTER2_SELECT0				0x9a30
-#define	CB_PERFCOUNTER2_SELECT1				0x9a34
-#define	CB_PERFCOUNTER3_SELECT0				0x9a38
-#define	CB_PERFCOUNTER3_SELECT1				0x9a3c
-
-#define	CB_CGTT_SCLK_CTRL				0x9a60
-
-#define	GC_USER_RB_BACKEND_DISABLE			0x9B7C
-#define		BACKEND_DISABLE_MASK			0x00FF0000
-#define		BACKEND_DISABLE_SHIFT			16
-
-#define	TCP_CHAN_STEER_LO				0xac0c
-#define	TCP_CHAN_STEER_HI				0xac10
-
-#define	CP_RB0_BASE					0xC100
-#define	CP_RB0_CNTL					0xC104
-#define		RB_BUFSZ(x)					((x) << 0)
-#define		RB_BLKSZ(x)					((x) << 8)
-#define		BUF_SWAP_32BIT					(2 << 16)
-#define		RB_NO_UPDATE					(1 << 27)
-#define		RB_RPTR_WR_ENA					(1 << 31)
-
-#define	CP_RB0_RPTR_ADDR				0xC10C
-#define	CP_RB0_RPTR_ADDR_HI				0xC110
-#define	CP_RB0_WPTR					0xC114
-
-#define	CP_PFP_UCODE_ADDR				0xC150
-#define	CP_PFP_UCODE_DATA				0xC154
-#define	CP_ME_RAM_RADDR					0xC158
-#define	CP_ME_RAM_WADDR					0xC15C
-#define	CP_ME_RAM_DATA					0xC160
-
-#define	CP_CE_UCODE_ADDR				0xC168
-#define	CP_CE_UCODE_DATA				0xC16C
-
-#define	CP_RB1_BASE					0xC180
-#define	CP_RB1_CNTL					0xC184
-#define	CP_RB1_RPTR_ADDR				0xC188
-#define	CP_RB1_RPTR_ADDR_HI				0xC18C
-#define	CP_RB1_WPTR					0xC190
-#define	CP_RB2_BASE					0xC194
-#define	CP_RB2_CNTL					0xC198
-#define	CP_RB2_RPTR_ADDR				0xC19C
-#define	CP_RB2_RPTR_ADDR_HI				0xC1A0
-#define	CP_RB2_WPTR					0xC1A4
-#define CP_INT_CNTL_RING0                               0xC1A8
-#define CP_INT_CNTL_RING1                               0xC1AC
-#define CP_INT_CNTL_RING2                               0xC1B0
-#       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
-#       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
-#       define WAIT_MEM_SEM_INT_ENABLE                  (1 << 21)
-#       define TIME_STAMP_INT_ENABLE                    (1 << 26)
-#       define CP_RINGID2_INT_ENABLE                    (1 << 29)
-#       define CP_RINGID1_INT_ENABLE                    (1 << 30)
-#       define CP_RINGID0_INT_ENABLE                    (1 << 31)
-#define CP_INT_STATUS_RING0                             0xC1B4
-#define CP_INT_STATUS_RING1                             0xC1B8
-#define CP_INT_STATUS_RING2                             0xC1BC
-#       define WAIT_MEM_SEM_INT_STAT                    (1 << 21)
-#       define TIME_STAMP_INT_STAT                      (1 << 26)
-#       define CP_RINGID2_INT_STAT                      (1 << 29)
-#       define CP_RINGID1_INT_STAT                      (1 << 30)
-#       define CP_RINGID0_INT_STAT                      (1 << 31)
-
-#define	CP_MEM_SLP_CNTL					0xC1E4
-#       define CP_MEM_LS_EN                             (1 << 0)
-
-#define	CP_DEBUG					0xC1FC
-
-#define RLC_CNTL                                          0xC300
-#       define RLC_ENABLE                                 (1 << 0)
-#define RLC_RL_BASE                                       0xC304
-#define RLC_RL_SIZE                                       0xC308
-#define RLC_LB_CNTL                                       0xC30C
-#       define LOAD_BALANCE_ENABLE                        (1 << 0)
-#define RLC_SAVE_AND_RESTORE_BASE                         0xC310
-#define RLC_LB_CNTR_MAX                                   0xC314
-#define RLC_LB_CNTR_INIT                                  0xC318
-
-#define RLC_CLEAR_STATE_RESTORE_BASE                      0xC320
-
-#define RLC_UCODE_ADDR                                    0xC32C
-#define RLC_UCODE_DATA                                    0xC330
-
-#define RLC_GPU_CLOCK_COUNT_LSB                           0xC338
-#define RLC_GPU_CLOCK_COUNT_MSB                           0xC33C
-#define RLC_CAPTURE_GPU_CLOCK_COUNT                       0xC340
-#define RLC_MC_CNTL                                       0xC344
-#define RLC_UCODE_CNTL                                    0xC348
-#define RLC_STAT                                          0xC34C
-#       define RLC_BUSY_STATUS                            (1 << 0)
-#       define GFX_POWER_STATUS                           (1 << 1)
-#       define GFX_CLOCK_STATUS                           (1 << 2)
-#       define GFX_LS_STATUS                              (1 << 3)
-
-#define	RLC_PG_CNTL					0xC35C
-#	define GFX_PG_ENABLE				(1 << 0)
-#	define GFX_PG_SRC				(1 << 1)
-
-#define	RLC_CGTT_MGCG_OVERRIDE				0xC400
-#define	RLC_CGCG_CGLS_CTRL				0xC404
-#	define CGCG_EN					(1 << 0)
-#	define CGLS_EN					(1 << 1)
-
-#define	RLC_TTOP_D					0xC414
-#	define RLC_PUD(x)				((x) << 0)
-#	define RLC_PUD_MASK				(0xff << 0)
-#	define RLC_PDD(x)				((x) << 8)
-#	define RLC_PDD_MASK				(0xff << 8)
-#	define RLC_TTPD(x)				((x) << 16)
-#	define RLC_TTPD_MASK				(0xff << 16)
-#	define RLC_MSD(x)				((x) << 24)
-#	define RLC_MSD_MASK				(0xff << 24)
-
-#define RLC_LB_INIT_CU_MASK                               0xC41C
-
-#define	RLC_PG_AO_CU_MASK				0xC42C
-#define	RLC_MAX_PG_CU					0xC430
-#	define MAX_PU_CU(x)				((x) << 0)
-#	define MAX_PU_CU_MASK				(0xff << 0)
-#define	RLC_AUTO_PG_CTRL				0xC434
-#	define AUTO_PG_EN				(1 << 0)
-#	define GRBM_REG_SGIT(x)				((x) << 3)
-#	define GRBM_REG_SGIT_MASK			(0xffff << 3)
-#	define PG_AFTER_GRBM_REG_ST(x)			((x) << 19)
-#	define PG_AFTER_GRBM_REG_ST_MASK		(0x1fff << 19)
-
-#define RLC_SERDES_WR_MASTER_MASK_0                       0xC454
-#define RLC_SERDES_WR_MASTER_MASK_1                       0xC458
-#define RLC_SERDES_WR_CTRL                                0xC45C
-
-#define RLC_SERDES_MASTER_BUSY_0                          0xC464
-#define RLC_SERDES_MASTER_BUSY_1                          0xC468
-
-#define RLC_GCPM_GENERAL_3                                0xC478
-
-#define	DB_RENDER_CONTROL				0x28000
-
-#define DB_DEPTH_INFO                                   0x2803c
-
-#define PA_SC_RASTER_CONFIG                             0x28350
-#       define RASTER_CONFIG_RB_MAP_0                   0
-#       define RASTER_CONFIG_RB_MAP_1                   1
-#       define RASTER_CONFIG_RB_MAP_2                   2
-#       define RASTER_CONFIG_RB_MAP_3                   3
-
-#define VGT_EVENT_INITIATOR                             0x28a90
-#       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)
-#       define SAMPLE_STREAMOUTSTATS2                   (2 << 0)
-#       define SAMPLE_STREAMOUTSTATS3                   (3 << 0)
-#       define CACHE_FLUSH_TS                           (4 << 0)
-#       define CACHE_FLUSH                              (6 << 0)
-#       define CS_PARTIAL_FLUSH                         (7 << 0)
-#       define VGT_STREAMOUT_RESET                      (10 << 0)
-#       define END_OF_PIPE_INCR_DE                      (11 << 0)
-#       define END_OF_PIPE_IB_END                       (12 << 0)
-#       define RST_PIX_CNT                              (13 << 0)
-#       define VS_PARTIAL_FLUSH                         (15 << 0)
-#       define PS_PARTIAL_FLUSH                         (16 << 0)
-#       define CACHE_FLUSH_AND_INV_TS_EVENT             (20 << 0)
-#       define ZPASS_DONE                               (21 << 0)
-#       define CACHE_FLUSH_AND_INV_EVENT                (22 << 0)
-#       define PERFCOUNTER_START                        (23 << 0)
-#       define PERFCOUNTER_STOP                         (24 << 0)
-#       define PIPELINESTAT_START                       (25 << 0)
-#       define PIPELINESTAT_STOP                        (26 << 0)
-#       define PERFCOUNTER_SAMPLE                       (27 << 0)
-#       define SAMPLE_PIPELINESTAT                      (30 << 0)
-#       define SAMPLE_STREAMOUTSTATS                    (32 << 0)
-#       define RESET_VTX_CNT                            (33 << 0)
-#       define VGT_FLUSH                                (36 << 0)
-#       define BOTTOM_OF_PIPE_TS                        (40 << 0)
-#       define DB_CACHE_FLUSH_AND_INV                   (42 << 0)
-#       define FLUSH_AND_INV_DB_DATA_TS                 (43 << 0)
-#       define FLUSH_AND_INV_DB_META                    (44 << 0)
-#       define FLUSH_AND_INV_CB_DATA_TS                 (45 << 0)
-#       define FLUSH_AND_INV_CB_META                    (46 << 0)
-#       define CS_DONE                                  (47 << 0)
-#       define PS_DONE                                  (48 << 0)
-#       define FLUSH_AND_INV_CB_PIXEL_DATA              (49 << 0)
-#       define THREAD_TRACE_START                       (51 << 0)
-#       define THREAD_TRACE_STOP                        (52 << 0)
-#       define THREAD_TRACE_FLUSH                       (54 << 0)
-#       define THREAD_TRACE_FINISH                      (55 << 0)
-
-/* PIF PHY0 registers idx/data 0x8/0xc */
-#define PB0_PIF_CNTL                                      0x10
-#       define LS2_EXIT_TIME(x)                           ((x) << 17)
-#       define LS2_EXIT_TIME_MASK                         (0x7 << 17)
-#       define LS2_EXIT_TIME_SHIFT                        17
-#define PB0_PIF_PAIRING                                   0x11
-#       define MULTI_PIF                                  (1 << 25)
-#define PB0_PIF_PWRDOWN_0                                 0x12
-#       define PLL_POWER_STATE_IN_TXS2_0(x)               ((x) << 7)
-#       define PLL_POWER_STATE_IN_TXS2_0_MASK             (0x7 << 7)
-#       define PLL_POWER_STATE_IN_TXS2_0_SHIFT            7
-#       define PLL_POWER_STATE_IN_OFF_0(x)                ((x) << 10)
-#       define PLL_POWER_STATE_IN_OFF_0_MASK              (0x7 << 10)
-#       define PLL_POWER_STATE_IN_OFF_0_SHIFT             10
-#       define PLL_RAMP_UP_TIME_0(x)                      ((x) << 24)
-#       define PLL_RAMP_UP_TIME_0_MASK                    (0x7 << 24)
-#       define PLL_RAMP_UP_TIME_0_SHIFT                   24
-#define PB0_PIF_PWRDOWN_1                                 0x13
-#       define PLL_POWER_STATE_IN_TXS2_1(x)               ((x) << 7)
-#       define PLL_POWER_STATE_IN_TXS2_1_MASK             (0x7 << 7)
-#       define PLL_POWER_STATE_IN_TXS2_1_SHIFT            7
-#       define PLL_POWER_STATE_IN_OFF_1(x)                ((x) << 10)
-#       define PLL_POWER_STATE_IN_OFF_1_MASK              (0x7 << 10)
-#       define PLL_POWER_STATE_IN_OFF_1_SHIFT             10
-#       define PLL_RAMP_UP_TIME_1(x)                      ((x) << 24)
-#       define PLL_RAMP_UP_TIME_1_MASK                    (0x7 << 24)
-#       define PLL_RAMP_UP_TIME_1_SHIFT                   24
-
-#define PB0_PIF_PWRDOWN_2                                 0x17
-#       define PLL_POWER_STATE_IN_TXS2_2(x)               ((x) << 7)
-#       define PLL_POWER_STATE_IN_TXS2_2_MASK             (0x7 << 7)
-#       define PLL_POWER_STATE_IN_TXS2_2_SHIFT            7
-#       define PLL_POWER_STATE_IN_OFF_2(x)                ((x) << 10)
-#       define PLL_POWER_STATE_IN_OFF_2_MASK              (0x7 << 10)
-#       define PLL_POWER_STATE_IN_OFF_2_SHIFT             10
-#       define PLL_RAMP_UP_TIME_2(x)                      ((x) << 24)
-#       define PLL_RAMP_UP_TIME_2_MASK                    (0x7 << 24)
-#       define PLL_RAMP_UP_TIME_2_SHIFT                   24
-#define PB0_PIF_PWRDOWN_3                                 0x18
-#       define PLL_POWER_STATE_IN_TXS2_3(x)               ((x) << 7)
-#       define PLL_POWER_STATE_IN_TXS2_3_MASK             (0x7 << 7)
-#       define PLL_POWER_STATE_IN_TXS2_3_SHIFT            7
-#       define PLL_POWER_STATE_IN_OFF_3(x)                ((x) << 10)
-#       define PLL_POWER_STATE_IN_OFF_3_MASK              (0x7 << 10)
-#       define PLL_POWER_STATE_IN_OFF_3_SHIFT             10
-#       define PLL_RAMP_UP_TIME_3(x)                      ((x) << 24)
-#       define PLL_RAMP_UP_TIME_3_MASK                    (0x7 << 24)
-#       define PLL_RAMP_UP_TIME_3_SHIFT                   24
-/* PIF PHY1 registers idx/data 0x10/0x14 */
-#define PB1_PIF_CNTL                                      0x10
-#define PB1_PIF_PAIRING                                   0x11
-#define PB1_PIF_PWRDOWN_0                                 0x12
-#define PB1_PIF_PWRDOWN_1                                 0x13
-
-#define PB1_PIF_PWRDOWN_2                                 0x17
-#define PB1_PIF_PWRDOWN_3                                 0x18
-/* PCIE registers idx/data 0x30/0x34 */
-#define PCIE_CNTL2                                        0x1c /* PCIE */
-#       define SLV_MEM_LS_EN                              (1 << 16)
-#       define SLV_MEM_AGGRESSIVE_LS_EN                   (1 << 17)
-#       define MST_MEM_LS_EN                              (1 << 18)
-#       define REPLAY_MEM_LS_EN                           (1 << 19)
-#define PCIE_LC_STATUS1                                   0x28 /* PCIE */
-#       define LC_REVERSE_RCVR                            (1 << 0)
-#       define LC_REVERSE_XMIT                            (1 << 1)
-#       define LC_OPERATING_LINK_WIDTH_MASK               (0x7 << 2)
-#       define LC_OPERATING_LINK_WIDTH_SHIFT              2
-#       define LC_DETECTED_LINK_WIDTH_MASK                (0x7 << 5)
-#       define LC_DETECTED_LINK_WIDTH_SHIFT               5
-
-#define PCIE_P_CNTL                                       0x40 /* PCIE */
-#       define P_IGNORE_EDB_ERR                           (1 << 6)
-
-/* PCIE PORT registers idx/data 0x38/0x3c */
-#define PCIE_LC_CNTL                                      0xa0
-#       define LC_L0S_INACTIVITY(x)                       ((x) << 8)
-#       define LC_L0S_INACTIVITY_MASK                     (0xf << 8)
-#       define LC_L0S_INACTIVITY_SHIFT                    8
-#       define LC_L1_INACTIVITY(x)                        ((x) << 12)
-#       define LC_L1_INACTIVITY_MASK                      (0xf << 12)
-#       define LC_L1_INACTIVITY_SHIFT                     12
-#       define LC_PMI_TO_L1_DIS                           (1 << 16)
-#       define LC_ASPM_TO_L1_DIS                          (1 << 24)
-#define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */
-#       define LC_LINK_WIDTH_SHIFT                        0
-#       define LC_LINK_WIDTH_MASK                         0x7
-#       define LC_LINK_WIDTH_X0                           0
-#       define LC_LINK_WIDTH_X1                           1
-#       define LC_LINK_WIDTH_X2                           2
-#       define LC_LINK_WIDTH_X4                           3
-#       define LC_LINK_WIDTH_X8                           4
-#       define LC_LINK_WIDTH_X16                          6
-#       define LC_LINK_WIDTH_RD_SHIFT                     4
-#       define LC_LINK_WIDTH_RD_MASK                      0x70
-#       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)
-#       define LC_RECONFIG_NOW                            (1 << 8)
-#       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)
-#       define LC_RENEGOTIATE_EN                          (1 << 10)
-#       define LC_SHORT_RECONFIG_EN                       (1 << 11)
-#       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)
-#       define LC_UPCONFIGURE_DIS                         (1 << 13)
-#       define LC_DYN_LANES_PWR_STATE(x)                  ((x) << 21)
-#       define LC_DYN_LANES_PWR_STATE_MASK                (0x3 << 21)
-#       define LC_DYN_LANES_PWR_STATE_SHIFT               21
-#define PCIE_LC_N_FTS_CNTL                                0xa3 /* PCIE_P */
-#       define LC_XMIT_N_FTS(x)                           ((x) << 0)
-#       define LC_XMIT_N_FTS_MASK                         (0xff << 0)
-#       define LC_XMIT_N_FTS_SHIFT                        0
-#       define LC_XMIT_N_FTS_OVERRIDE_EN                  (1 << 8)
-#       define LC_N_FTS_MASK                              (0xff << 24)
-#define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */
-#       define LC_GEN2_EN_STRAP                           (1 << 0)
-#       define LC_GEN3_EN_STRAP                           (1 << 1)
-#       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 2)
-#       define LC_TARGET_LINK_SPEED_OVERRIDE_MASK         (0x3 << 3)
-#       define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT        3
-#       define LC_FORCE_EN_SW_SPEED_CHANGE                (1 << 5)
-#       define LC_FORCE_DIS_SW_SPEED_CHANGE               (1 << 6)
-#       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 7)
-#       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 8)
-#       define LC_INITIATE_LINK_SPEED_CHANGE              (1 << 9)
-#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 10)
-#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     10
-#       define LC_CURRENT_DATA_RATE_MASK                  (0x3 << 13) /* 0/1/2 = gen1/2/3 */
-#       define LC_CURRENT_DATA_RATE_SHIFT                 13
-#       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 16)
-#       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 18)
-#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 19)
-#       define LC_OTHER_SIDE_EVER_SENT_GEN3               (1 << 20)
-#       define LC_OTHER_SIDE_SUPPORTS_GEN3                (1 << 21)
-
-#define PCIE_LC_CNTL2                                     0xb1
-#       define LC_ALLOW_PDWN_IN_L1                        (1 << 17)
-#       define LC_ALLOW_PDWN_IN_L23                       (1 << 18)
-
-#define PCIE_LC_CNTL3                                     0xb5 /* PCIE_P */
-#       define LC_GO_TO_RECOVERY                          (1 << 30)
-#define PCIE_LC_CNTL4                                     0xb6 /* PCIE_P */
-#       define LC_REDO_EQ                                 (1 << 5)
-#       define LC_SET_QUIESCE                             (1 << 13)
-
-/*
- * UVD
- */
-#define UVD_UDEC_ADDR_CONFIG				0xEF4C
-#define UVD_UDEC_DB_ADDR_CONFIG				0xEF50
-#define UVD_UDEC_DBW_ADDR_CONFIG			0xEF54
-#define UVD_NO_OP					0xEFFC
-#define UVD_RBC_RB_RPTR					0xF690
-#define UVD_RBC_RB_WPTR					0xF694
-#define UVD_STATUS					0xf6bc
-
-#define	UVD_CGC_CTRL					0xF4B0
-#	define DCM					(1 << 0)
-#	define CG_DT(x)					((x) << 2)
-#	define CG_DT_MASK				(0xf << 2)
-#	define CLK_OD(x)				((x) << 6)
-#	define CLK_OD_MASK				(0x1f << 6)
-
- /* UVD CTX indirect */
-#define	UVD_CGC_MEM_CTRL				0xC0
-#define	UVD_CGC_CTRL2					0xC1
-#	define DYN_OR_EN				(1 << 0)
-#	define DYN_RR_EN				(1 << 1)
-#	define G_DIV_ID(x)				((x) << 2)
-#	define G_DIV_ID_MASK				(0x7 << 2)
-
-/*
- * PM4
- */
-#define PACKET0(reg, n)	((RADEON_PACKET_TYPE0 << 30) |			\
-			 (((reg) >> 2) & 0xFFFF) |			\
-			 ((n) & 0x3FFF) << 16)
-#define CP_PACKET2			0x80000000
-#define		PACKET2_PAD_SHIFT		0
-#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
-
-#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
-
-#define PACKET3(op, n)	((RADEON_PACKET_TYPE3 << 30) |			\
-			 (((op) & 0xFF) << 8) |				\
-			 ((n) & 0x3FFF) << 16)
-
-#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
-
-/* Packet 3 types */
-#define	PACKET3_NOP					0x10
-#define	PACKET3_SET_BASE				0x11
-#define		PACKET3_BASE_INDEX(x)                  ((x) << 0)
-#define			GDS_PARTITION_BASE		2
-#define			CE_PARTITION_BASE		3
-#define	PACKET3_CLEAR_STATE				0x12
-#define	PACKET3_INDEX_BUFFER_SIZE			0x13
-#define	PACKET3_DISPATCH_DIRECT				0x15
-#define	PACKET3_DISPATCH_INDIRECT			0x16
-#define	PACKET3_ALLOC_GDS				0x1B
-#define	PACKET3_WRITE_GDS_RAM				0x1C
-#define	PACKET3_ATOMIC_GDS				0x1D
-#define	PACKET3_ATOMIC					0x1E
-#define	PACKET3_OCCLUSION_QUERY				0x1F
-#define	PACKET3_SET_PREDICATION				0x20
-#define	PACKET3_REG_RMW					0x21
-#define	PACKET3_COND_EXEC				0x22
-#define	PACKET3_PRED_EXEC				0x23
-#define	PACKET3_DRAW_INDIRECT				0x24
-#define	PACKET3_DRAW_INDEX_INDIRECT			0x25
-#define	PACKET3_INDEX_BASE				0x26
-#define	PACKET3_DRAW_INDEX_2				0x27
-#define	PACKET3_CONTEXT_CONTROL				0x28
-#define	PACKET3_INDEX_TYPE				0x2A
-#define	PACKET3_DRAW_INDIRECT_MULTI			0x2C
-#define	PACKET3_DRAW_INDEX_AUTO				0x2D
-#define	PACKET3_DRAW_INDEX_IMMD				0x2E
-#define	PACKET3_NUM_INSTANCES				0x2F
-#define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30
-#define	PACKET3_INDIRECT_BUFFER_CONST			0x31
-#define	PACKET3_INDIRECT_BUFFER				0x32
-#define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
-#define	PACKET3_DRAW_INDEX_OFFSET_2			0x35
-#define	PACKET3_DRAW_INDEX_MULTI_ELEMENT		0x36
-#define	PACKET3_WRITE_DATA				0x37
-#define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
-                /* 0 - register
-		 * 1 - memory (sync - via GRBM)
-		 * 2 - tc/l2
-		 * 3 - gds
-		 * 4 - reserved
-		 * 5 - memory (async - direct)
-		 */
-#define		WR_ONE_ADDR                             (1 << 16)
-#define		WR_CONFIRM                              (1 << 20)
-#define		WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
-                /* 0 - me
-		 * 1 - pfp
-		 * 2 - ce
-		 */
-#define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38
-#define	PACKET3_MEM_SEMAPHORE				0x39
-#define	PACKET3_MPEG_INDEX				0x3A
-#define	PACKET3_COPY_DW					0x3B
-#define	PACKET3_WAIT_REG_MEM				0x3C
-#define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
-                /* 0 - always
-		 * 1 - <
-		 * 2 - <=
-		 * 3 - ==
-		 * 4 - !=
-		 * 5 - >=
-		 * 6 - >
-		 */
-#define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
-                /* 0 - reg
-		 * 1 - mem
-		 */
-#define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
-                /* 0 - me
-		 * 1 - pfp
-		 */
-#define	PACKET3_MEM_WRITE				0x3D
-#define	PACKET3_COPY_DATA				0x40
-#define	PACKET3_CP_DMA					0x41
-/* 1. header
- * 2. SRC_ADDR_LO or DATA [31:0]
- * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
- *    SRC_ADDR_HI [7:0]
- * 4. DST_ADDR_LO [31:0]
- * 5. DST_ADDR_HI [7:0]
- * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
- */
-#              define PACKET3_CP_DMA_DST_SEL(x)    ((x) << 20)
-                /* 0 - DST_ADDR
-		 * 1 - GDS
-		 */
-#              define PACKET3_CP_DMA_ENGINE(x)     ((x) << 27)
-                /* 0 - ME
-		 * 1 - PFP
-		 */
-#              define PACKET3_CP_DMA_SRC_SEL(x)    ((x) << 29)
-                /* 0 - SRC_ADDR
-		 * 1 - GDS
-		 * 2 - DATA
-		 */
-#              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)
-/* COMMAND */
-#              define PACKET3_CP_DMA_DIS_WC        (1 << 21)
-#              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
-                /* 0 - none
-		 * 1 - 8 in 16
-		 * 2 - 8 in 32
-		 * 3 - 8 in 64
-		 */
-#              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
-                /* 0 - none
-		 * 1 - 8 in 16
-		 * 2 - 8 in 32
-		 * 3 - 8 in 64
-		 */
-#              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)
-                /* 0 - memory
-		 * 1 - register
-		 */
-#              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)
-                /* 0 - memory
-		 * 1 - register
-		 */
-#              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)
-#              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)
-#              define PACKET3_CP_DMA_CMD_RAW_WAIT  (1 << 30)
-#define	PACKET3_PFP_SYNC_ME				0x42
-#define	PACKET3_SURFACE_SYNC				0x43
-#              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
-#              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
-#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
-#              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
-#              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
-#              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
-#              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
-#              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
-#              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
-#              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
-#              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
-#              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
-#              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
-#              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
-#              define PACKET3_TC_ACTION_ENA        (1 << 23)
-#              define PACKET3_CB_ACTION_ENA        (1 << 25)
-#              define PACKET3_DB_ACTION_ENA        (1 << 26)
-#              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
-#              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
-#define	PACKET3_ME_INITIALIZE				0x44
-#define		PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
-#define	PACKET3_COND_WRITE				0x45
-#define	PACKET3_EVENT_WRITE				0x46
-#define		EVENT_TYPE(x)                           ((x) << 0)
-#define		EVENT_INDEX(x)                          ((x) << 8)
-                /* 0 - any non-TS event
-		 * 1 - ZPASS_DONE
-		 * 2 - SAMPLE_PIPELINESTAT
-		 * 3 - SAMPLE_STREAMOUTSTAT*
-		 * 4 - *S_PARTIAL_FLUSH
-		 * 5 - EOP events
-		 * 6 - EOS events
-		 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
-		 */
-#define		INV_L2                                  (1 << 20)
-                /* INV TC L2 cache when EVENT_INDEX = 7 */
-#define	PACKET3_EVENT_WRITE_EOP				0x47
-#define		DATA_SEL(x)                             ((x) << 29)
-                /* 0 - discard
-		 * 1 - send low 32bit data
-		 * 2 - send 64bit data
-		 * 3 - send 64bit counter value
-		 */
-#define		INT_SEL(x)                              ((x) << 24)
-                /* 0 - none
-		 * 1 - interrupt only (DATA_SEL = 0)
-		 * 2 - interrupt when data write is confirmed
-		 */
-#define	PACKET3_EVENT_WRITE_EOS				0x48
-#define	PACKET3_PREAMBLE_CNTL				0x4A
-#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
-#              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
-#define	PACKET3_ONE_REG_WRITE				0x57
-#define	PACKET3_LOAD_CONFIG_REG				0x5F
-#define	PACKET3_LOAD_CONTEXT_REG			0x60
-#define	PACKET3_LOAD_SH_REG				0x61
-#define	PACKET3_SET_CONFIG_REG				0x68
-#define		PACKET3_SET_CONFIG_REG_START			0x00008000
-#define		PACKET3_SET_CONFIG_REG_END			0x0000b000
-#define	PACKET3_SET_CONTEXT_REG				0x69
-#define		PACKET3_SET_CONTEXT_REG_START			0x00028000
-#define		PACKET3_SET_CONTEXT_REG_END			0x00029000
-#define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
-#define	PACKET3_SET_RESOURCE_INDIRECT			0x74
-#define	PACKET3_SET_SH_REG				0x76
-#define		PACKET3_SET_SH_REG_START			0x0000b000
-#define		PACKET3_SET_SH_REG_END				0x0000c000
-#define	PACKET3_SET_SH_REG_OFFSET			0x77
-#define	PACKET3_ME_WRITE				0x7A
-#define	PACKET3_SCRATCH_RAM_WRITE			0x7D
-#define	PACKET3_SCRATCH_RAM_READ			0x7E
-#define	PACKET3_CE_WRITE				0x7F
-#define	PACKET3_LOAD_CONST_RAM				0x80
-#define	PACKET3_WRITE_CONST_RAM				0x81
-#define	PACKET3_WRITE_CONST_RAM_OFFSET			0x82
-#define	PACKET3_DUMP_CONST_RAM				0x83
-#define	PACKET3_INCREMENT_CE_COUNTER			0x84
-#define	PACKET3_INCREMENT_DE_COUNTER			0x85
-#define	PACKET3_WAIT_ON_CE_COUNTER			0x86
-#define	PACKET3_WAIT_ON_DE_COUNTER			0x87
-#define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
-#define	PACKET3_SET_CE_DE_COUNTERS			0x89
-#define	PACKET3_WAIT_ON_AVAIL_BUFFER			0x8A
-#define	PACKET3_SWITCH_BUFFER				0x8B
-
-/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
-#define DMA0_REGISTER_OFFSET                              0x0 /* not a register */
-#define DMA1_REGISTER_OFFSET                              0x800 /* not a register */
-
-#define DMA_RB_CNTL                                       0xd000
-#       define DMA_RB_ENABLE                              (1 << 0)
-#       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */
-#       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */
-#       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)
-#       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */
-#       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */
-#define DMA_RB_BASE                                       0xd004
-#define DMA_RB_RPTR                                       0xd008
-#define DMA_RB_WPTR                                       0xd00c
-
-#define DMA_RB_RPTR_ADDR_HI                               0xd01c
-#define DMA_RB_RPTR_ADDR_LO                               0xd020
-
-#define DMA_IB_CNTL                                       0xd024
-#       define DMA_IB_ENABLE                              (1 << 0)
-#       define DMA_IB_SWAP_ENABLE                         (1 << 4)
-#define DMA_IB_RPTR                                       0xd028
-#define DMA_CNTL                                          0xd02c
-#       define TRAP_ENABLE                                (1 << 0)
-#       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)
-#       define SEM_WAIT_INT_ENABLE                        (1 << 2)
-#       define DATA_SWAP_ENABLE                           (1 << 3)
-#       define FENCE_SWAP_ENABLE                          (1 << 4)
-#       define CTXEMPTY_INT_ENABLE                        (1 << 28)
-#define DMA_STATUS_REG                                    0xd034
-#       define DMA_IDLE                                   (1 << 0)
-#define DMA_TILING_CONFIG  				  0xd0b8
-
-#define	DMA_POWER_CNTL					0xd0bc
-#       define MEM_POWER_OVERRIDE                       (1 << 8)
-#define	DMA_CLK_CTRL					0xd0c0
-
-#define	DMA_PG						0xd0d4
-#	define PG_CNTL_ENABLE				(1 << 0)
-#define	DMA_PGFSM_CONFIG				0xd0d8
-#define	DMA_PGFSM_WRITE					0xd0dc
-
-#define DMA_PACKET(cmd, b, t, s, n)	((((cmd) & 0xF) << 28) |	\
-					 (((b) & 0x1) << 26) |		\
-					 (((t) & 0x1) << 23) |		\
-					 (((s) & 0x1) << 22) |		\
-					 (((n) & 0xFFFFF) << 0))
-
-#define DMA_IB_PACKET(cmd, vmid, n)	((((cmd) & 0xF) << 28) |	\
-					 (((vmid) & 0xF) << 20) |	\
-					 (((n) & 0xFFFFF) << 0))
-
-#define DMA_PTE_PDE_PACKET(n)		((2 << 28) |			\
-					 (1 << 26) |			\
-					 (1 << 21) |			\
-					 (((n) & 0xFFFFF) << 0))
-
-/* async DMA Packet types */
-#define	DMA_PACKET_WRITE				  0x2
-#define	DMA_PACKET_COPY					  0x3
-#define	DMA_PACKET_INDIRECT_BUFFER			  0x4
-#define	DMA_PACKET_SEMAPHORE				  0x5
-#define	DMA_PACKET_FENCE				  0x6
-#define	DMA_PACKET_TRAP					  0x7
-#define	DMA_PACKET_SRBM_WRITE				  0x9
-#define	DMA_PACKET_CONSTANT_FILL			  0xd
-#define	DMA_PACKET_POLL_REG_MEM				  0xe
-#define	DMA_PACKET_NOP					  0xf
-
-#define VCE_STATUS					0x20004
-#define VCE_VCPU_CNTL					0x20014
-#define		VCE_CLK_EN				(1 << 0)
-#define VCE_VCPU_CACHE_OFFSET0				0x20024
-#define VCE_VCPU_CACHE_SIZE0				0x20028
-#define VCE_VCPU_CACHE_OFFSET1				0x2002c
-#define VCE_VCPU_CACHE_SIZE1				0x20030
-#define VCE_VCPU_CACHE_OFFSET2				0x20034
-#define VCE_VCPU_CACHE_SIZE2				0x20038
-#define VCE_VCPU_SCRATCH7				0x200dc
-#define VCE_SOFT_RESET					0x20120
-#define 	VCE_ECPU_SOFT_RESET			(1 << 0)
-#define 	VCE_FME_SOFT_RESET			(1 << 2)
-#define VCE_RB_BASE_LO2					0x2016c
-#define VCE_RB_BASE_HI2					0x20170
-#define VCE_RB_SIZE2					0x20174
-#define VCE_RB_RPTR2					0x20178
-#define VCE_RB_WPTR2					0x2017c
-#define VCE_RB_BASE_LO					0x20180
-#define VCE_RB_BASE_HI					0x20184
-#define VCE_RB_SIZE					0x20188
-#define VCE_RB_RPTR					0x2018c
-#define VCE_RB_WPTR					0x20190
-#define VCE_CLOCK_GATING_A				0x202f8
-#	define CGC_DYN_CLOCK_MODE			(1 << 16)
-#define VCE_CLOCK_GATING_B				0x202fc
-#define VCE_UENC_CLOCK_GATING				0x205bc
-#define VCE_UENC_REG_CLOCK_GATING			0x205c0
-#define VCE_FW_REG_STATUS				0x20e10
-#	define VCE_FW_REG_STATUS_BUSY			(1 << 0)
-#	define VCE_FW_REG_STATUS_PASS			(1 << 3)
-#	define VCE_FW_REG_STATUS_DONE			(1 << 11)
-#define VCE_LMI_FW_START_KEYSEL				0x20e18
-#define VCE_LMI_FW_PERIODIC_CTRL			0x20e20
-#define VCE_LMI_CTRL2					0x20e74
-#define VCE_LMI_CTRL					0x20e98
-#define VCE_LMI_VM_CTRL					0x20ea0
-#define VCE_LMI_SWAP_CNTL				0x20eb4
-#define VCE_LMI_SWAP_CNTL1				0x20eb8
-#define VCE_LMI_CACHE_CTRL				0x20ef4
-
-#define VCE_CMD_NO_OP					0x00000000
-#define VCE_CMD_END					0x00000001
-#define VCE_CMD_IB					0x00000002
-#define VCE_CMD_FENCE					0x00000003
-#define VCE_CMD_TRAP					0x00000004
-#define VCE_CMD_IB_AUTO					0x00000005
-#define VCE_CMD_SEMAPHORE				0x00000006
-
-/* discrete vce clocks */
-#define	CG_VCEPLL_FUNC_CNTL				0xc0030600
-#	define VCEPLL_RESET_MASK			0x00000001
-#	define VCEPLL_SLEEP_MASK			0x00000002
-#	define VCEPLL_BYPASS_EN_MASK			0x00000004
-#	define VCEPLL_CTLREQ_MASK			0x00000008
-#	define VCEPLL_VCO_MODE_MASK			0x00000600
-#	define VCEPLL_REF_DIV_MASK			0x003F0000
-#	define VCEPLL_CTLACK_MASK			0x40000000
-#	define VCEPLL_CTLACK2_MASK			0x80000000
-#define	CG_VCEPLL_FUNC_CNTL_2				0xc0030601
-#	define VCEPLL_PDIV_A(x)				((x) << 0)
-#	define VCEPLL_PDIV_A_MASK			0x0000007F
-#	define VCEPLL_PDIV_B(x)				((x) << 8)
-#	define VCEPLL_PDIV_B_MASK			0x00007F00
-#	define EVCLK_SRC_SEL(x)				((x) << 20)
-#	define EVCLK_SRC_SEL_MASK			0x01F00000
-#	define ECCLK_SRC_SEL(x)				((x) << 25)
-#	define ECCLK_SRC_SEL_MASK			0x3E000000
-#define	CG_VCEPLL_FUNC_CNTL_3				0xc0030602
-#	define VCEPLL_FB_DIV(x)				((x) << 0)
-#	define VCEPLL_FB_DIV_MASK			0x01FFFFFF
-#define	CG_VCEPLL_FUNC_CNTL_4				0xc0030603
-#define	CG_VCEPLL_FUNC_CNTL_5				0xc0030604
-#define	CG_VCEPLL_SPREAD_SPECTRUM			0xc0030606
-#	define VCEPLL_SSEN_MASK				0x00000001
-
-#endif
diff --git a/hw/display/sislands_smc.h b/hw/display/sislands_smc.h
deleted file mode 100644
index 966e3a5560..0000000000
--- a/hw/display/sislands_smc.h
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * Copyright 2013 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef PP_SISLANDS_SMC_H
-#define PP_SISLANDS_SMC_H
-
-#include "ppsmc.h"
-
-#pragma pack(push, 1)
-
-#define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
-
-struct PP_SIslands_Dpm2PerfLevel
-{
-    uint8_t MaxPS;
-    uint8_t TgtAct;
-    uint8_t MaxPS_StepInc;
-    uint8_t MaxPS_StepDec;
-    uint8_t PSSamplingTime;
-    uint8_t NearTDPDec;
-    uint8_t AboveSafeInc;
-    uint8_t BelowSafeInc;
-    uint8_t PSDeltaLimit;
-    uint8_t PSDeltaWin;
-    uint16_t PwrEfficiencyRatio;
-    uint8_t Reserved[4];
-};
-
-typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel;
-
-struct PP_SIslands_DPM2Status
-{
-    uint32_t    dpm2Flags;
-    uint8_t     CurrPSkip;
-    uint8_t     CurrPSkipPowerShift;
-    uint8_t     CurrPSkipTDP;
-    uint8_t     CurrPSkipOCP;
-    uint8_t     MaxSPLLIndex;
-    uint8_t     MinSPLLIndex;
-    uint8_t     CurrSPLLIndex;
-    uint8_t     InfSweepMode;
-    uint8_t     InfSweepDir;
-    uint8_t     TDPexceeded;
-    uint8_t     reserved;
-    uint8_t     SwitchDownThreshold;
-    uint32_t    SwitchDownCounter;
-    uint32_t    SysScalingFactor;
-};
-
-typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status;
-
-struct PP_SIslands_DPM2Parameters
-{
-    uint32_t    TDPLimit;
-    uint32_t    NearTDPLimit;
-    uint32_t    SafePowerLimit;
-    uint32_t    PowerBoostLimit;
-    uint32_t    MinLimitDelta;
-};
-typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters;
-
-struct PP_SIslands_PAPMStatus
-{
-    uint32_t    EstimatedDGPU_T;
-    uint32_t    EstimatedDGPU_P;
-    uint32_t    EstimatedAPU_T;
-    uint32_t    EstimatedAPU_P;
-    uint8_t     dGPU_T_Limit_Exceeded;
-    uint8_t     reserved[3];
-};
-typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus;
-
-struct PP_SIslands_PAPMParameters
-{
-    uint32_t    NearTDPLimitTherm;
-    uint32_t    NearTDPLimitPAPM;
-    uint32_t    PlatformPowerLimit;
-    uint32_t    dGPU_T_Limit;
-    uint32_t    dGPU_T_Warning;
-    uint32_t    dGPU_T_Hysteresis;
-};
-typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters;
-
-struct SISLANDS_SMC_SCLK_VALUE
-{
-    uint32_t    vCG_SPLL_FUNC_CNTL;
-    uint32_t    vCG_SPLL_FUNC_CNTL_2;
-    uint32_t    vCG_SPLL_FUNC_CNTL_3;
-    uint32_t    vCG_SPLL_FUNC_CNTL_4;
-    uint32_t    vCG_SPLL_SPREAD_SPECTRUM;
-    uint32_t    vCG_SPLL_SPREAD_SPECTRUM_2;
-    uint32_t    sclk_value;
-};
-
-typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE;
-
-struct SISLANDS_SMC_MCLK_VALUE
-{
-    uint32_t    vMPLL_FUNC_CNTL;
-    uint32_t    vMPLL_FUNC_CNTL_1;
-    uint32_t    vMPLL_FUNC_CNTL_2;
-    uint32_t    vMPLL_AD_FUNC_CNTL;
-    uint32_t    vMPLL_DQ_FUNC_CNTL;
-    uint32_t    vMCLK_PWRMGT_CNTL;
-    uint32_t    vDLL_CNTL;
-    uint32_t    vMPLL_SS;
-    uint32_t    vMPLL_SS2;
-    uint32_t    mclk_value;
-};
-
-typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE;
-
-struct SISLANDS_SMC_VOLTAGE_VALUE
-{
-    uint16_t    value;
-    uint8_t     index;
-    uint8_t     phase_settings;
-};
-
-typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE;
-
-struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
-{
-    uint8_t                     ACIndex;
-    uint8_t                     displayWatermark;
-    uint8_t                     gen2PCIE;
-    uint8_t                     UVDWatermark;
-    uint8_t                     VCEWatermark;
-    uint8_t                     strobeMode;
-    uint8_t                     mcFlags;
-    uint8_t                     padding;
-    uint32_t                    aT;
-    uint32_t                    bSP;
-    SISLANDS_SMC_SCLK_VALUE     sclk;
-    SISLANDS_SMC_MCLK_VALUE     mclk;
-    SISLANDS_SMC_VOLTAGE_VALUE  vddc;
-    SISLANDS_SMC_VOLTAGE_VALUE  mvdd;
-    SISLANDS_SMC_VOLTAGE_VALUE  vddci;
-    SISLANDS_SMC_VOLTAGE_VALUE  std_vddc;
-    uint8_t                     hysteresisUp;
-    uint8_t                     hysteresisDown;
-    uint8_t                     stateFlags;
-    uint8_t                     arbRefreshState;
-    uint32_t                    SQPowerThrottle;
-    uint32_t                    SQPowerThrottle_2;
-    uint32_t                    MaxPoweredUpCU;
-    SISLANDS_SMC_VOLTAGE_VALUE  high_temp_vddc;
-    SISLANDS_SMC_VOLTAGE_VALUE  low_temp_vddc;
-    uint32_t                    reserved[2];
-    PP_SIslands_Dpm2PerfLevel   dpm2;
-};
-
-#define SISLANDS_SMC_STROBE_RATIO    0x0F
-#define SISLANDS_SMC_STROBE_ENABLE   0x10
-
-#define SISLANDS_SMC_MC_EDC_RD_FLAG  0x01
-#define SISLANDS_SMC_MC_EDC_WR_FLAG  0x02
-#define SISLANDS_SMC_MC_RTT_ENABLE   0x04
-#define SISLANDS_SMC_MC_STUTTER_EN   0x08
-#define SISLANDS_SMC_MC_PG_EN        0x10
-
-typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL;
-
-struct SISLANDS_SMC_SWSTATE
-{
-    uint8_t                             flags;
-    uint8_t                             levelCount;
-    uint8_t                             padding2;
-    uint8_t                             padding3;
-    SISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[1];
-};
-
-typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
-
-#define SISLANDS_SMC_VOLTAGEMASK_VDDC  0
-#define SISLANDS_SMC_VOLTAGEMASK_MVDD  1
-#define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
-#define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3
-#define SISLANDS_SMC_VOLTAGEMASK_MAX   4
-
-struct SISLANDS_SMC_VOLTAGEMASKTABLE
-{
-    uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
-};
-
-typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE;
-
-#define SISLANDS_MAX_NO_VREG_STEPS 32
-
-struct SISLANDS_SMC_STATETABLE
-{
-    uint8_t                             thermalProtectType;
-    uint8_t                             systemFlags;
-    uint8_t                             maxVDDCIndexInPPTable;
-    uint8_t                             extraFlags;
-    uint32_t                            lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
-    SISLANDS_SMC_VOLTAGEMASKTABLE       voltageMaskTable;
-    SISLANDS_SMC_VOLTAGEMASKTABLE       phaseMaskTable;
-    PP_SIslands_DPM2Parameters          dpm2Params;
-    SISLANDS_SMC_SWSTATE                initialState;
-    SISLANDS_SMC_SWSTATE                ACPIState;
-    SISLANDS_SMC_SWSTATE                ULVState;
-    SISLANDS_SMC_SWSTATE                driverState;
-    SISLANDS_SMC_HW_PERFORMANCE_LEVEL   dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
-};
-
-typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;
-
-#define SI_SMC_SOFT_REGISTER_mclk_chg_timeout         0x0
-#define SI_SMC_SOFT_REGISTER_delay_vreg               0xC
-#define SI_SMC_SOFT_REGISTER_delay_acpi               0x28
-#define SI_SMC_SOFT_REGISTER_seq_index                0x5C
-#define SI_SMC_SOFT_REGISTER_mvdd_chg_time            0x60
-#define SI_SMC_SOFT_REGISTER_mclk_switch_lim          0x70
-#define SI_SMC_SOFT_REGISTER_watermark_threshold      0x78
-#define SI_SMC_SOFT_REGISTER_phase_shedding_delay     0x88
-#define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay    0x8C
-#define SI_SMC_SOFT_REGISTER_mc_block_delay           0x98
-#define SI_SMC_SOFT_REGISTER_ticks_per_us             0xA8
-#define SI_SMC_SOFT_REGISTER_crtc_index               0xC4
-#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8
-#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC
-#define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width  0xF4
-#define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen   0xFC
-#define SI_SMC_SOFT_REGISTER_vr_hot_gpio              0x100
-#define SI_SMC_SOFT_REGISTER_svi_rework_plat_type     0x118
-#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd   0x11c
-#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc   0x120
-
-struct PP_SIslands_FanTable
-{
-	uint8_t  fdo_mode;
-	uint8_t  padding;
-	int16_t  temp_min;
-	int16_t  temp_med;
-	int16_t  temp_max;
-	int16_t  slope1;
-	int16_t  slope2;
-	int16_t  fdo_min;
-	int16_t  hys_up;
-	int16_t  hys_down;
-	int16_t  hys_slope;
-	int16_t  temp_resp_lim;
-	int16_t  temp_curr;
-	int16_t  slope_curr;
-	int16_t  pwm_curr;
-	uint32_t refresh_period;
-	int16_t  fdo_max;
-	uint8_t  temp_src;
-	int8_t  padding2;
-};
-
-typedef struct PP_SIslands_FanTable PP_SIslands_FanTable;
-
-#define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
-#define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32
-
-#define SMC_SISLANDS_SCALE_I  7
-#define SMC_SISLANDS_SCALE_R 12
-
-struct PP_SIslands_CacConfig
-{
-    uint16_t   cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
-    uint32_t   lkge_lut_V0;
-    uint32_t   lkge_lut_Vstep;
-    uint32_t   WinTime;
-    uint32_t   R_LL;
-    uint32_t   calculation_repeats;
-    uint32_t   l2numWin_TDP;
-    uint32_t   dc_cac;
-    uint8_t    lts_truncate_n;
-    uint8_t    SHIFT_N;
-    uint8_t    log2_PG_LKG_SCALE;
-    uint8_t    cac_temp;
-    uint32_t   lkge_lut_T0;
-    uint32_t   lkge_lut_Tstep;
-};
-
-typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig;
-
-#define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16
-#define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
-
-struct SMC_SIslands_MCRegisterAddress
-{
-    uint16_t s0;
-    uint16_t s1;
-};
-
-typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress;
-
-struct SMC_SIslands_MCRegisterSet
-{
-    uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
-};
-
-typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet;
-
-struct SMC_SIslands_MCRegisters
-{
-    uint8_t                             last;
-    uint8_t                             reserved[3];
-    SMC_SIslands_MCRegisterAddress      address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
-    SMC_SIslands_MCRegisterSet          data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
-};
-
-typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters;
-
-struct SMC_SIslands_MCArbDramTimingRegisterSet
-{
-    uint32_t mc_arb_dram_timing;
-    uint32_t mc_arb_dram_timing2;
-    uint8_t  mc_arb_rfsh_rate;
-    uint8_t  mc_arb_burst_time;
-    uint8_t  padding[2];
-};
-
-typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet;
-
-struct SMC_SIslands_MCArbDramTimingRegisters
-{
-    uint8_t                                     arb_current;
-    uint8_t                                     reserved[3];
-    SMC_SIslands_MCArbDramTimingRegisterSet     data[16];
-};
-
-typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters;
-
-struct SMC_SISLANDS_SPLL_DIV_TABLE
-{
-    uint32_t    freq[256];
-    uint32_t    ss[256];
-};
-
-#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK  0x01ffffff
-#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
-#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK   0xfe000000
-#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT  25
-#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK   0x000fffff
-#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT  0
-#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK   0xfff00000
-#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT  20
-
-typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE;
-
-#define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5
-
-#define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16
-
-struct Smc_SIslands_DTE_Configuration
-{
-    uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
-    uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
-    uint32_t K;
-    uint32_t T0;
-    uint32_t MaxT;
-    uint8_t  WindowSize;
-    uint8_t  Tdep_count;
-    uint8_t  temp_select;
-    uint8_t  DTE_mode;
-    uint8_t  T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
-    uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
-    uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
-    uint32_t Tthreshold;
-};
-
-typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration;
-
-#define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1
-
-#define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000
-
-#define SISLANDS_SMC_FIRMWARE_HEADER_version                   0x0
-#define SISLANDS_SMC_FIRMWARE_HEADER_flags                     0x4
-#define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters             0xC
-#define SISLANDS_SMC_FIRMWARE_HEADER_stateTable                0x10
-#define SISLANDS_SMC_FIRMWARE_HEADER_fanTable                  0x14
-#define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable            0x18
-#define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable           0x24
-#define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30
-#define SISLANDS_SMC_FIRMWARE_HEADER_spllTable                 0x38
-#define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration          0x40
-#define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters            0x48
-
-#pragma pack(pop)
-
-int si_copy_bytes_to_smc(struct radeon_device *rdev,
-			 u32 smc_start_address,
-			 const u8 *src, u32 byte_count, u32 limit);
-void si_start_smc(struct radeon_device *rdev);
-void si_reset_smc(struct radeon_device *rdev);
-int si_program_jump_on_start(struct radeon_device *rdev);
-void si_stop_smc_clock(struct radeon_device *rdev);
-void si_start_smc_clock(struct radeon_device *rdev);
-bool si_is_smc_running(struct radeon_device *rdev);
-PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
-PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev);
-int si_load_smc_ucode(struct radeon_device *rdev, u32 limit);
-int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
-			   u32 *value, u32 limit);
-int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
-			    u32 value, u32 limit);
-
-#endif
-
diff --git a/hw/display/smu7.h b/hw/display/smu7.h
deleted file mode 100644
index 75a380a152..0000000000
--- a/hw/display/smu7.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright 2013 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef SMU7_H
-#define SMU7_H
-
-#pragma pack(push, 1)
-
-#define SMU7_CONTEXT_ID_SMC        1
-#define SMU7_CONTEXT_ID_VBIOS      2
-
-
-#define SMU7_CONTEXT_ID_SMC        1
-#define SMU7_CONTEXT_ID_VBIOS      2
-
-#define SMU7_MAX_LEVELS_VDDC            8
-#define SMU7_MAX_LEVELS_VDDCI           4
-#define SMU7_MAX_LEVELS_MVDD            4
-#define SMU7_MAX_LEVELS_VDDNB           8
-
-#define SMU7_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   // SCLK + SQ DPM + ULV
-#define SMU7_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
-#define SMU7_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  // LCLK Levels
-#define SMU7_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  // PCIe speed and number of lanes.
-#define SMU7_MAX_LEVELS_UVD             8   // VCLK/DCLK levels for UVD.
-#define SMU7_MAX_LEVELS_VCE             8   // ECLK levels for VCE.
-#define SMU7_MAX_LEVELS_ACP             8   // ACLK levels for ACP.
-#define SMU7_MAX_LEVELS_SAMU            8   // SAMCLK levels for SAMU.
-#define SMU7_MAX_ENTRIES_SMIO           32  // Number of entries in SMIO table.
-
-#define DPM_NO_LIMIT 0
-#define DPM_NO_UP 1
-#define DPM_GO_DOWN 2
-#define DPM_GO_UP 3
-
-#define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
-#define SMU7_FIRST_DPM_MEMORY_LEVEL      0
-
-#define GPIO_CLAMP_MODE_VRHOT      1
-#define GPIO_CLAMP_MODE_THERM      2
-#define GPIO_CLAMP_MODE_DC         4
-
-#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
-#define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
-#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
-#define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
-#define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
-#define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
-#define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
-#define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
-#define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
-#define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
-#define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
-#define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
-#define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
-#define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
-#define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
-#define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
-#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
-#define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
-#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
-#define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
-
-
-struct SMU7_PIDController
-{
-    uint32_t Ki;
-    int32_t LFWindupUL;
-    int32_t LFWindupLL;
-    uint32_t StatePrecision;
-    uint32_t LfPrecision;
-    uint32_t LfOffset;
-    uint32_t MaxState;
-    uint32_t MaxLfFraction;
-    uint32_t StateShift;
-};
-
-typedef struct SMU7_PIDController SMU7_PIDController;
-
-// -------------------------------------------------------------------------------------------------------------------------
-#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
-
-#define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
-#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
-#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
-#define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
-#define SMU7_UVD_DPM_CONFIG_MASK                         0x10
-#define SMU7_VCE_DPM_CONFIG_MASK                         0x20
-#define SMU7_ACP_DPM_CONFIG_MASK                         0x40
-#define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
-#define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
-
-#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
-#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
-#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
-#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
-#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
-#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
-
-struct SMU7_Firmware_Header
-{
-    uint32_t Digest[5];
-    uint32_t Version;
-    uint32_t HeaderSize;
-    uint32_t Flags;
-    uint32_t EntryPoint;
-    uint32_t CodeSize;
-    uint32_t ImageSize;
-
-    uint32_t Rtos;
-    uint32_t SoftRegisters;
-    uint32_t DpmTable;
-    uint32_t FanTable;
-    uint32_t CacConfigTable;
-    uint32_t CacStatusTable;
-
-    uint32_t mcRegisterTable;
-
-    uint32_t mcArbDramTimingTable;
-
-    uint32_t PmFuseTable;
-    uint32_t Globals;
-    uint32_t Reserved[42];
-    uint32_t Signature;
-};
-
-typedef struct SMU7_Firmware_Header SMU7_Firmware_Header;
-
-#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
-
-enum  DisplayConfig {
-    PowerDown = 1,
-    DP54x4,
-    DP54x2,
-    DP54x1,
-    DP27x4,
-    DP27x2,
-    DP27x1,
-    HDMI297,
-    HDMI162,
-    LVDS,
-    DP324x4,
-    DP324x2,
-    DP324x1
-};
-
-#pragma pack(pop)
-
-#endif
-
diff --git a/hw/display/smu7_discrete.h b/hw/display/smu7_discrete.h
deleted file mode 100644
index 0b0b404ff0..0000000000
--- a/hw/display/smu7_discrete.h
+++ /dev/null
@@ -1,514 +0,0 @@
-/*
- * Copyright 2013 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef SMU7_DISCRETE_H
-#define SMU7_DISCRETE_H
-
-#include "smu7.h"
-
-#pragma pack(push, 1)
-
-#define SMU7_DTE_ITERATIONS 5
-#define SMU7_DTE_SOURCES 3
-#define SMU7_DTE_SINKS 1
-#define SMU7_NUM_CPU_TES 0
-#define SMU7_NUM_GPU_TES 1
-#define SMU7_NUM_NON_TES 2
-
-struct SMU7_SoftRegisters
-{
-    uint32_t        RefClockFrequency;
-    uint32_t        PmTimerP;
-    uint32_t        FeatureEnables;
-    uint32_t        PreVBlankGap;
-    uint32_t        VBlankTimeout;
-    uint32_t        TrainTimeGap;
-
-    uint32_t        MvddSwitchTime;
-    uint32_t        LongestAcpiTrainTime;
-    uint32_t        AcpiDelay;
-    uint32_t        G5TrainTime;
-    uint32_t        DelayMpllPwron;
-    uint32_t        VoltageChangeTimeout;
-    uint32_t        HandshakeDisables;
-
-    uint8_t         DisplayPhy1Config;
-    uint8_t         DisplayPhy2Config;
-    uint8_t         DisplayPhy3Config;
-    uint8_t         DisplayPhy4Config;
-
-    uint8_t         DisplayPhy5Config;
-    uint8_t         DisplayPhy6Config;
-    uint8_t         DisplayPhy7Config;
-    uint8_t         DisplayPhy8Config;
-
-    uint32_t        AverageGraphicsA;
-    uint32_t        AverageMemoryA;
-    uint32_t        AverageGioA;
-
-    uint8_t         SClkDpmEnabledLevels;
-    uint8_t         MClkDpmEnabledLevels;
-    uint8_t         LClkDpmEnabledLevels;
-    uint8_t         PCIeDpmEnabledLevels;
-
-    uint8_t         UVDDpmEnabledLevels;
-    uint8_t         SAMUDpmEnabledLevels;
-    uint8_t         ACPDpmEnabledLevels;
-    uint8_t         VCEDpmEnabledLevels;
-
-    uint32_t        DRAM_LOG_ADDR_H;
-    uint32_t        DRAM_LOG_ADDR_L;
-    uint32_t        DRAM_LOG_PHY_ADDR_H;
-    uint32_t        DRAM_LOG_PHY_ADDR_L;
-    uint32_t        DRAM_LOG_BUFF_SIZE;
-    uint32_t        UlvEnterC;
-    uint32_t        UlvTime;
-    uint32_t        Reserved[3];
-
-};
-
-typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
-
-struct SMU7_Discrete_VoltageLevel
-{
-    uint16_t    Voltage;
-    uint16_t    StdVoltageHiSidd;
-    uint16_t    StdVoltageLoSidd;
-    uint8_t     Smio;
-    uint8_t     padding;
-};
-
-typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;
-
-struct SMU7_Discrete_GraphicsLevel
-{
-    uint32_t    Flags;
-    uint32_t    MinVddc;
-    uint32_t    MinVddcPhases;
-
-    uint32_t    SclkFrequency;
-
-    uint8_t     padding1[2];
-    uint16_t    ActivityLevel;
-
-    uint32_t    CgSpllFuncCntl3;
-    uint32_t    CgSpllFuncCntl4;
-    uint32_t    SpllSpreadSpectrum;
-    uint32_t    SpllSpreadSpectrum2;
-    uint32_t    CcPwrDynRm;
-    uint32_t    CcPwrDynRm1;
-    uint8_t     SclkDid;
-    uint8_t     DisplayWatermark;
-    uint8_t     EnabledForActivity;
-    uint8_t     EnabledForThrottle;
-    uint8_t     UpH;
-    uint8_t     DownH;
-    uint8_t     VoltageDownH;
-    uint8_t     PowerThrottle;
-    uint8_t     DeepSleepDivId;
-    uint8_t     padding[3];
-};
-
-typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;
-
-struct SMU7_Discrete_ACPILevel
-{
-    uint32_t    Flags;
-    uint32_t    MinVddc;
-    uint32_t    MinVddcPhases;
-    uint32_t    SclkFrequency;
-    uint8_t     SclkDid;
-    uint8_t     DisplayWatermark;
-    uint8_t     DeepSleepDivId;
-    uint8_t     padding;
-    uint32_t    CgSpllFuncCntl;
-    uint32_t    CgSpllFuncCntl2;
-    uint32_t    CgSpllFuncCntl3;
-    uint32_t    CgSpllFuncCntl4;
-    uint32_t    SpllSpreadSpectrum;
-    uint32_t    SpllSpreadSpectrum2;
-    uint32_t    CcPwrDynRm;
-    uint32_t    CcPwrDynRm1;
-};
-
-typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;
-
-struct SMU7_Discrete_Ulv
-{
-    uint32_t    CcPwrDynRm;
-    uint32_t    CcPwrDynRm1;
-    uint16_t    VddcOffset;
-    uint8_t     VddcOffsetVid;
-    uint8_t     VddcPhase;
-    uint32_t    Reserved;
-};
-
-typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;
-
-struct SMU7_Discrete_MemoryLevel
-{
-    uint32_t    MinVddc;
-    uint32_t    MinVddcPhases;
-    uint32_t    MinVddci;
-    uint32_t    MinMvdd;
-
-    uint32_t    MclkFrequency;
-
-    uint8_t     EdcReadEnable;
-    uint8_t     EdcWriteEnable;
-    uint8_t     RttEnable;
-    uint8_t     StutterEnable;
-
-    uint8_t     StrobeEnable;
-    uint8_t     StrobeRatio;
-    uint8_t     EnabledForThrottle;
-    uint8_t     EnabledForActivity;
-
-    uint8_t     UpH;
-    uint8_t     DownH;
-    uint8_t     VoltageDownH;
-    uint8_t     padding;
-
-    uint16_t    ActivityLevel;
-    uint8_t     DisplayWatermark;
-    uint8_t     padding1;
-
-    uint32_t    MpllFuncCntl;
-    uint32_t    MpllFuncCntl_1;
-    uint32_t    MpllFuncCntl_2;
-    uint32_t    MpllAdFuncCntl;
-    uint32_t    MpllDqFuncCntl;
-    uint32_t    MclkPwrmgtCntl;
-    uint32_t    DllCntl;
-    uint32_t    MpllSs1;
-    uint32_t    MpllSs2;
-};
-
-typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;
-
-struct SMU7_Discrete_LinkLevel
-{
-    uint8_t     PcieGenSpeed;
-    uint8_t     PcieLaneCount;
-    uint8_t     EnabledForActivity;
-    uint8_t     Padding;
-    uint32_t    DownT;
-    uint32_t    UpT;
-    uint32_t    Reserved;
-};
-
-typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;
-
-
-struct SMU7_Discrete_MCArbDramTimingTableEntry
-{
-    uint32_t McArbDramTiming;
-    uint32_t McArbDramTiming2;
-    uint8_t  McArbBurstTime;
-    uint8_t  padding[3];
-};
-
-typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry;
-
-struct SMU7_Discrete_MCArbDramTimingTable
-{
-    SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
-};
-
-typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable;
-
-struct SMU7_Discrete_UvdLevel
-{
-    uint32_t VclkFrequency;
-    uint32_t DclkFrequency;
-    uint16_t MinVddc;
-    uint8_t  MinVddcPhases;
-    uint8_t  VclkDivider;
-    uint8_t  DclkDivider;
-    uint8_t  padding[3];
-};
-
-typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;
-
-struct SMU7_Discrete_ExtClkLevel
-{
-    uint32_t Frequency;
-    uint16_t MinVoltage;
-    uint8_t  MinPhases;
-    uint8_t  Divider;
-};
-
-typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;
-
-struct SMU7_Discrete_StateInfo
-{
-    uint32_t SclkFrequency;
-    uint32_t MclkFrequency;
-    uint32_t VclkFrequency;
-    uint32_t DclkFrequency;
-    uint32_t SamclkFrequency;
-    uint32_t AclkFrequency;
-    uint32_t EclkFrequency;
-    uint16_t MvddVoltage;
-    uint16_t padding16;
-    uint8_t  DisplayWatermark;
-    uint8_t  McArbIndex;
-    uint8_t  McRegIndex;
-    uint8_t  SeqIndex;
-    uint8_t  SclkDid;
-    int8_t   SclkIndex;
-    int8_t   MclkIndex;
-    uint8_t  PCIeGen;
-
-};
-
-typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;
-
-
-struct SMU7_Discrete_DpmTable
-{
-    SMU7_PIDController                  GraphicsPIDController;
-    SMU7_PIDController                  MemoryPIDController;
-    SMU7_PIDController                  LinkPIDController;
-
-    uint32_t                            SystemFlags;
-
-
-    uint32_t                            SmioMaskVddcVid;
-    uint32_t                            SmioMaskVddcPhase;
-    uint32_t                            SmioMaskVddciVid;
-    uint32_t                            SmioMaskMvddVid;
-
-    uint32_t                            VddcLevelCount;
-    uint32_t                            VddciLevelCount;
-    uint32_t                            MvddLevelCount;
-
-    SMU7_Discrete_VoltageLevel          VddcLevel               [SMU7_MAX_LEVELS_VDDC];
-//    SMU7_Discrete_VoltageLevel          VddcStandardReference   [SMU7_MAX_LEVELS_VDDC];
-    SMU7_Discrete_VoltageLevel          VddciLevel              [SMU7_MAX_LEVELS_VDDCI];
-    SMU7_Discrete_VoltageLevel          MvddLevel               [SMU7_MAX_LEVELS_MVDD];
-
-    uint8_t                             GraphicsDpmLevelCount;
-    uint8_t                             MemoryDpmLevelCount;
-    uint8_t                             LinkLevelCount;
-    uint8_t                             UvdLevelCount;
-    uint8_t                             VceLevelCount;
-    uint8_t                             AcpLevelCount;
-    uint8_t                             SamuLevelCount;
-    uint8_t                             MasterDeepSleepControl;
-    uint32_t                            Reserved[5];
-//    uint32_t                            SamuDefaultLevel;
-
-    SMU7_Discrete_GraphicsLevel         GraphicsLevel           [SMU7_MAX_LEVELS_GRAPHICS];
-    SMU7_Discrete_MemoryLevel           MemoryACPILevel;
-    SMU7_Discrete_MemoryLevel           MemoryLevel             [SMU7_MAX_LEVELS_MEMORY];
-    SMU7_Discrete_LinkLevel             LinkLevel               [SMU7_MAX_LEVELS_LINK];
-    SMU7_Discrete_ACPILevel             ACPILevel;
-    SMU7_Discrete_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
-    SMU7_Discrete_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
-    SMU7_Discrete_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
-    SMU7_Discrete_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
-    SMU7_Discrete_Ulv                   Ulv;
-
-    uint32_t                            SclkStepSize;
-    uint32_t                            Smio                    [SMU7_MAX_ENTRIES_SMIO];
-
-    uint8_t                             UvdBootLevel;
-    uint8_t                             VceBootLevel;
-    uint8_t                             AcpBootLevel;
-    uint8_t                             SamuBootLevel;
-
-    uint8_t                             UVDInterval;
-    uint8_t                             VCEInterval;
-    uint8_t                             ACPInterval;
-    uint8_t                             SAMUInterval;
-
-    uint8_t                             GraphicsBootLevel;
-    uint8_t                             GraphicsVoltageChangeEnable;
-    uint8_t                             GraphicsThermThrottleEnable;
-    uint8_t                             GraphicsInterval;
-
-    uint8_t                             VoltageInterval;
-    uint8_t                             ThermalInterval;
-    uint16_t                            TemperatureLimitHigh;
-
-    uint16_t                            TemperatureLimitLow;
-    uint8_t                             MemoryBootLevel;
-    uint8_t                             MemoryVoltageChangeEnable;
-
-    uint8_t                             MemoryInterval;
-    uint8_t                             MemoryThermThrottleEnable;
-    uint16_t                            VddcVddciDelta;
-
-    uint16_t                            VoltageResponseTime;
-    uint16_t                            PhaseResponseTime;
-
-    uint8_t                             PCIeBootLinkLevel;
-    uint8_t                             PCIeGenInterval;
-    uint8_t                             DTEInterval;
-    uint8_t                             DTEMode;
-
-    uint8_t                             SVI2Enable;
-    uint8_t                             VRHotGpio;
-    uint8_t                             AcDcGpio;
-    uint8_t                             ThermGpio;
-
-    uint16_t                            PPM_PkgPwrLimit;
-    uint16_t                            PPM_TemperatureLimit;
-
-    uint16_t                            DefaultTdp;
-    uint16_t                            TargetTdp;
-
-    uint16_t                            FpsHighT;
-    uint16_t                            FpsLowT;
-
-    uint16_t                            BAPMTI_R  [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
-    uint16_t                            BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
-
-    uint8_t                             DTEAmbientTempBase;
-    uint8_t                             DTETjOffset;
-    uint8_t                             GpuTjMax;
-    uint8_t                             GpuTjHyst;
-
-    uint16_t                            BootVddc;
-    uint16_t                            BootVddci;
-
-    uint16_t                            BootMVdd;
-    uint16_t                            padding;
-
-    uint32_t                            BAPM_TEMP_GRADIENT;
-
-    uint32_t                            LowSclkInterruptT;
-};
-
-typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable;
-
-#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
-#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY
-
-struct SMU7_Discrete_MCRegisterAddress
-{
-    uint16_t s0;
-    uint16_t s1;
-};
-
-typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress;
-
-struct SMU7_Discrete_MCRegisterSet
-{
-    uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-};
-
-typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;
-
-struct SMU7_Discrete_MCRegisters
-{
-    uint8_t                             last;
-    uint8_t                             reserved[3];
-    SMU7_Discrete_MCRegisterAddress     address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-    SMU7_Discrete_MCRegisterSet         data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
-};
-
-typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;
-
-struct SMU7_Discrete_FanTable
-{
-	uint16_t FdoMode;
-	int16_t  TempMin;
-	int16_t  TempMed;
-	int16_t  TempMax;
-	int16_t  Slope1;
-	int16_t  Slope2;
-	int16_t  FdoMin;
-	int16_t  HystUp;
-	int16_t  HystDown;
-	int16_t  HystSlope;
-	int16_t  TempRespLim;
-	int16_t  TempCurr;
-	int16_t  SlopeCurr;
-	int16_t  PwmCurr;
-	uint32_t RefreshPeriod;
-	int16_t  FdoMax;
-	uint8_t  TempSrc;
-	int8_t   Padding;
-};
-
-typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable;
-
-
-struct SMU7_Discrete_PmFuses {
-  // dw0-dw1
-  uint8_t BapmVddCVidHiSidd[8];
-
-  // dw2-dw3
-  uint8_t BapmVddCVidLoSidd[8];
-
-  // dw4-dw5
-  uint8_t VddCVid[8];
-
-  // dw6
-  uint8_t SviLoadLineEn;
-  uint8_t SviLoadLineVddC;
-  uint8_t SviLoadLineTrimVddC;
-  uint8_t SviLoadLineOffsetVddC;
-
-  // dw7
-  uint16_t TDC_VDDC_PkgLimit;
-  uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
-  uint8_t TDC_MAWt;
-
-  // dw8
-  uint8_t TdcWaterfallCtl;
-  uint8_t LPMLTemperatureMin;
-  uint8_t LPMLTemperatureMax;
-  uint8_t Reserved;
-
-  // dw9-dw10
-  uint8_t BapmVddCVidHiSidd2[8];
-
-  // dw11-dw12
-  int16_t FuzzyFan_ErrorSetDelta;
-  int16_t FuzzyFan_ErrorRateSetDelta;
-  int16_t FuzzyFan_PwmSetDelta;
-  uint16_t CalcMeasPowerBlend;
-
-  // dw13-dw16
-  uint8_t GnbLPML[16];
-
-  // dw17
-  uint8_t GnbLPMLMaxVid;
-  uint8_t GnbLPMLMinVid;
-  uint8_t Reserved1[2];
-
-  // dw18
-  uint16_t BapmVddCBaseLeakageHiSidd;
-  uint16_t BapmVddCBaseLeakageLoSidd;
-};
-
-typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses;
-
-
-#pragma pack(pop)
-
-#endif
-
diff --git a/hw/display/smu7_fusion.h b/hw/display/smu7_fusion.h
deleted file mode 100644
index 78ada9ffd5..0000000000
--- a/hw/display/smu7_fusion.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * Copyright 2013 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef SMU7_FUSION_H
-#define SMU7_FUSION_H
-
-#include "smu7.h"
-
-#pragma pack(push, 1)
-
-#define SMU7_DTE_ITERATIONS 5
-#define SMU7_DTE_SOURCES 5
-#define SMU7_DTE_SINKS 3
-#define SMU7_NUM_CPU_TES 2
-#define SMU7_NUM_GPU_TES 1
-#define SMU7_NUM_NON_TES 2
-
-// All 'soft registers' should be uint32_t.
-struct SMU7_SoftRegisters
-{
-    uint32_t        RefClockFrequency;
-    uint32_t        PmTimerP;
-    uint32_t        FeatureEnables;
-    uint32_t        HandshakeDisables;
-
-    uint8_t         DisplayPhy1Config;
-    uint8_t         DisplayPhy2Config;
-    uint8_t         DisplayPhy3Config;
-    uint8_t         DisplayPhy4Config;
-
-    uint8_t         DisplayPhy5Config;
-    uint8_t         DisplayPhy6Config;
-    uint8_t         DisplayPhy7Config;
-    uint8_t         DisplayPhy8Config;
-
-    uint32_t        AverageGraphicsA;
-    uint32_t        AverageMemoryA;
-    uint32_t        AverageGioA;
-
-    uint8_t         SClkDpmEnabledLevels;
-    uint8_t         MClkDpmEnabledLevels;
-    uint8_t         LClkDpmEnabledLevels;
-    uint8_t         PCIeDpmEnabledLevels;
-
-    uint8_t         UVDDpmEnabledLevels;
-    uint8_t         SAMUDpmEnabledLevels;
-    uint8_t         ACPDpmEnabledLevels;
-    uint8_t         VCEDpmEnabledLevels;
-
-    uint32_t        DRAM_LOG_ADDR_H;
-    uint32_t        DRAM_LOG_ADDR_L;
-    uint32_t        DRAM_LOG_PHY_ADDR_H;
-    uint32_t        DRAM_LOG_PHY_ADDR_L;
-    uint32_t        DRAM_LOG_BUFF_SIZE;
-    uint32_t        UlvEnterC;
-    uint32_t        UlvTime;
-    uint32_t        Reserved[3];
-
-};
-
-typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
-
-struct SMU7_Fusion_GraphicsLevel
-{
-    uint32_t    MinVddNb;
-
-    uint32_t    SclkFrequency;
-
-    uint8_t     Vid;
-    uint8_t     VidOffset;
-    uint16_t    AT;
-
-    uint8_t     PowerThrottle;
-    uint8_t     GnbSlow;
-    uint8_t     ForceNbPs1;
-    uint8_t     SclkDid;
-
-    uint8_t     DisplayWatermark;
-    uint8_t     EnabledForActivity;
-    uint8_t     EnabledForThrottle;
-    uint8_t     UpH;
-
-    uint8_t     DownH;
-    uint8_t     VoltageDownH;
-    uint8_t     DeepSleepDivId;
-
-    uint8_t     ClkBypassCntl;
-
-    uint32_t    reserved;
-};
-
-typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel;
-
-struct SMU7_Fusion_GIOLevel
-{
-    uint8_t     EnabledForActivity;
-    uint8_t     LclkDid;
-    uint8_t     Vid;
-    uint8_t     VoltageDownH;
-
-    uint32_t    MinVddNb;
-
-    uint16_t    ResidencyCounter;
-    uint8_t     UpH;
-    uint8_t     DownH;
-
-    uint32_t    LclkFrequency;
-
-    uint8_t     ActivityLevel;
-    uint8_t     EnabledForThrottle;
-
-    uint8_t     ClkBypassCntl;
-
-    uint8_t     padding;
-};
-
-typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel;
-
-// UVD VCLK/DCLK state (level) definition.
-struct SMU7_Fusion_UvdLevel
-{
-    uint32_t VclkFrequency;
-    uint32_t DclkFrequency;
-    uint16_t MinVddNb;
-    uint8_t  VclkDivider;
-    uint8_t  DclkDivider;
-
-    uint8_t     VClkBypassCntl;
-    uint8_t     DClkBypassCntl;
-
-    uint8_t     padding[2];
-
-};
-
-typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel;
-
-// Clocks for other external blocks (VCE, ACP, SAMU).
-struct SMU7_Fusion_ExtClkLevel
-{
-    uint32_t Frequency;
-    uint16_t MinVoltage;
-    uint8_t  Divider;
-    uint8_t  ClkBypassCntl;
-
-    uint32_t Reserved;
-};
-typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel;
-
-struct SMU7_Fusion_ACPILevel
-{
-    uint32_t    Flags;
-    uint32_t    MinVddNb;
-    uint32_t    SclkFrequency;
-    uint8_t     SclkDid;
-    uint8_t     GnbSlow;
-    uint8_t     ForceNbPs1;
-    uint8_t     DisplayWatermark;
-    uint8_t     DeepSleepDivId;
-    uint8_t     padding[3];
-};
-
-typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel;
-
-struct SMU7_Fusion_NbDpm
-{
-    uint8_t DpmXNbPsHi;
-    uint8_t DpmXNbPsLo;
-    uint8_t Dpm0PgNbPsHi;
-    uint8_t Dpm0PgNbPsLo;
-    uint8_t EnablePsi1;
-    uint8_t SkipDPM0;
-    uint8_t SkipPG;
-    uint8_t Hysteresis;
-    uint8_t EnableDpmPstatePoll;
-    uint8_t padding[3];
-};
-
-typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm;
-
-struct SMU7_Fusion_StateInfo
-{
-    uint32_t SclkFrequency;
-    uint32_t LclkFrequency;
-    uint32_t VclkFrequency;
-    uint32_t DclkFrequency;
-    uint32_t SamclkFrequency;
-    uint32_t AclkFrequency;
-    uint32_t EclkFrequency;
-    uint8_t  DisplayWatermark;
-    uint8_t  McArbIndex;
-    int8_t   SclkIndex;
-    int8_t   MclkIndex;
-};
-
-typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo;
-
-struct SMU7_Fusion_DpmTable
-{
-    uint32_t                            SystemFlags;
-
-    SMU7_PIDController                  GraphicsPIDController;
-    SMU7_PIDController                  GioPIDController;
-
-    uint8_t                            GraphicsDpmLevelCount;
-    uint8_t                            GIOLevelCount;
-    uint8_t                            UvdLevelCount;
-    uint8_t                            VceLevelCount;
-
-    uint8_t                            AcpLevelCount;
-    uint8_t                            SamuLevelCount;
-    uint16_t                           FpsHighT;
-
-    SMU7_Fusion_GraphicsLevel         GraphicsLevel           [SMU__NUM_SCLK_DPM_STATE];
-    SMU7_Fusion_ACPILevel             ACPILevel;
-    SMU7_Fusion_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
-    SMU7_Fusion_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
-    SMU7_Fusion_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
-    SMU7_Fusion_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
-
-    uint8_t                           UvdBootLevel;
-    uint8_t                           VceBootLevel;
-    uint8_t                           AcpBootLevel;
-    uint8_t                           SamuBootLevel;
-    uint8_t                           UVDInterval;
-    uint8_t                           VCEInterval;
-    uint8_t                           ACPInterval;
-    uint8_t                           SAMUInterval;
-
-    uint8_t                           GraphicsBootLevel;
-    uint8_t                           GraphicsInterval;
-    uint8_t                           GraphicsThermThrottleEnable;
-    uint8_t                           GraphicsVoltageChangeEnable;
-
-    uint8_t                           GraphicsClkSlowEnable;
-    uint8_t                           GraphicsClkSlowDivider;
-    uint16_t                          FpsLowT;
-
-    uint32_t                          DisplayCac;
-    uint32_t                          LowSclkInterruptT;
-
-    uint32_t                          DRAM_LOG_ADDR_H;
-    uint32_t                          DRAM_LOG_ADDR_L;
-    uint32_t                          DRAM_LOG_PHY_ADDR_H;
-    uint32_t                          DRAM_LOG_PHY_ADDR_L;
-    uint32_t                          DRAM_LOG_BUFF_SIZE;
-
-};
-
-struct SMU7_Fusion_GIODpmTable
-{
-
-    SMU7_Fusion_GIOLevel              GIOLevel                [SMU7_MAX_LEVELS_GIO];
-
-    SMU7_PIDController                GioPIDController;
-
-    uint32_t                          GIOLevelCount;
-
-    uint8_t                           Enable;
-    uint8_t                           GIOVoltageChangeEnable;
-    uint8_t                           GIOBootLevel;
-    uint8_t                           padding;
-    uint8_t                           padding1[2];
-    uint8_t                           TargetState;
-    uint8_t                           CurrenttState;
-    uint8_t                           ThrottleOnHtc;
-    uint8_t                           ThermThrottleStatus;
-    uint8_t                           ThermThrottleTempSelect;
-    uint8_t                           ThermThrottleEnable;
-    uint16_t                          TemperatureLimitHigh;
-    uint16_t                          TemperatureLimitLow;
-
-};
-
-typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable;
-typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable;
-
-#pragma pack(pop)
-
-#endif
-
diff --git a/hw/display/sumo_dpm.h b/hw/display/sumo_dpm.h
deleted file mode 100644
index f1651135a4..0000000000
--- a/hw/display/sumo_dpm.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Copyright 2012 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __SUMO_DPM_H__
-#define __SUMO_DPM_H__
-
-#include "atom.h"
-#include "radeon.h"
-
-#define SUMO_MAX_HARDWARE_POWERLEVELS 5
-#define SUMO_PM_NUMBER_OF_TC 15
-
-struct sumo_pl {
-	u32 sclk;
-	u32 vddc_index;
-	u32 ds_divider_index;
-	u32 ss_divider_index;
-	u32 allow_gnb_slow;
-	u32 sclk_dpm_tdp_limit;
-};
-
-/* used for the flags field */
-#define SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE (1 << 0)
-#define SUMO_POWERSTATE_FLAGS_BOOST_STATE       (1 << 1)
-
-struct sumo_ps {
-	struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
-	u32 num_levels;
-	/* flags */
-	u32 flags;
-};
-
-#define NUMBER_OF_M3ARB_PARAM_SETS 10
-#define SUMO_MAX_NUMBER_VOLTAGES    4
-
-struct sumo_disp_clock_voltage_mapping_table {
-	u32 num_max_voltage_levels;
-	u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES];
-};
-
-struct sumo_vid_mapping_entry {
-	u16 vid_2bit;
-	u16 vid_7bit;
-};
-
-struct sumo_vid_mapping_table {
-	u32 num_entries;
-	struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES];
-};
-
-struct sumo_sclk_voltage_mapping_entry {
-	u32 sclk_frequency;
-	u16 vid_2bit;
-	u16 rsv;
-};
-
-struct sumo_sclk_voltage_mapping_table {
-	u32 num_max_dpm_entries;
-	struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];
-};
-
-struct sumo_sys_info {
-	u32 bootup_sclk;
-	u32 min_sclk;
-	u32 bootup_uma_clk;
-	u16 bootup_nb_voltage_index;
-	u8 htc_tmp_lmt;
-	u8 htc_hyst_lmt;
-	struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
-	struct sumo_disp_clock_voltage_mapping_table disp_clk_voltage_mapping_table;
-	struct sumo_vid_mapping_table vid_mapping_table;
-	u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];
-	u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];
-	u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];
-	u32 sclk_dpm_boost_margin;
-	u32 sclk_dpm_throttle_margin;
-	u32 sclk_dpm_tdp_limit_pg;
-	u32 gnb_tdp_limit;
-	u32 sclk_dpm_tdp_limit_boost;
-	u32 boost_sclk;
-	u32 boost_vid_2bit;
-	bool enable_boost;
-};
-
-struct sumo_power_info {
-	u32 asi;
-	u32 pasi;
-	u32 bsp;
-	u32 bsu;
-	u32 pbsp;
-	u32 pbsu;
-	u32 dsp;
-	u32 psp;
-	u32 thermal_auto_throttling;
-	u32 uvd_m3_arbiter;
-	u32 fw_version;
-	struct sumo_sys_info sys_info;
-	struct sumo_pl acpi_pl;
-	struct sumo_pl boot_pl;
-	struct sumo_pl boost_pl;
-	bool disable_gfx_power_gating_in_uvd;
-	bool driver_nbps_policy_disable;
-	bool enable_alt_vddnb;
-	bool enable_dynamic_m3_arbiter;
-	bool enable_gfx_clock_gating;
-	bool enable_gfx_power_gating;
-	bool enable_mg_clock_gating;
-	bool enable_sclk_ds;
-	bool enable_auto_thermal_throttling;
-	bool enable_dynamic_patch_ps;
-	bool enable_dpm;
-	bool enable_boost;
-	struct radeon_ps current_rps;
-	struct sumo_ps current_ps;
-	struct radeon_ps requested_rps;
-	struct sumo_ps requested_ps;
-};
-
-#define SUMO_UTC_DFLT_00                     0x48
-#define SUMO_UTC_DFLT_01                     0x44
-#define SUMO_UTC_DFLT_02                     0x44
-#define SUMO_UTC_DFLT_03                     0x44
-#define SUMO_UTC_DFLT_04                     0x44
-#define SUMO_UTC_DFLT_05                     0x44
-#define SUMO_UTC_DFLT_06                     0x44
-#define SUMO_UTC_DFLT_07                     0x44
-#define SUMO_UTC_DFLT_08                     0x44
-#define SUMO_UTC_DFLT_09                     0x44
-#define SUMO_UTC_DFLT_10                     0x44
-#define SUMO_UTC_DFLT_11                     0x44
-#define SUMO_UTC_DFLT_12                     0x44
-#define SUMO_UTC_DFLT_13                     0x44
-#define SUMO_UTC_DFLT_14                     0x44
-
-#define SUMO_DTC_DFLT_00                     0x48
-#define SUMO_DTC_DFLT_01                     0x44
-#define SUMO_DTC_DFLT_02                     0x44
-#define SUMO_DTC_DFLT_03                     0x44
-#define SUMO_DTC_DFLT_04                     0x44
-#define SUMO_DTC_DFLT_05                     0x44
-#define SUMO_DTC_DFLT_06                     0x44
-#define SUMO_DTC_DFLT_07                     0x44
-#define SUMO_DTC_DFLT_08                     0x44
-#define SUMO_DTC_DFLT_09                     0x44
-#define SUMO_DTC_DFLT_10                     0x44
-#define SUMO_DTC_DFLT_11                     0x44
-#define SUMO_DTC_DFLT_12                     0x44
-#define SUMO_DTC_DFLT_13                     0x44
-#define SUMO_DTC_DFLT_14                     0x44
-
-#define SUMO_AH_DFLT               5
-
-#define SUMO_R_DFLT0               70
-#define SUMO_R_DFLT1               70
-#define SUMO_R_DFLT2               70
-#define SUMO_R_DFLT3               70
-#define SUMO_R_DFLT4               100
-
-#define SUMO_L_DFLT0               0
-#define SUMO_L_DFLT1               20
-#define SUMO_L_DFLT2               20
-#define SUMO_L_DFLT3               20
-#define SUMO_L_DFLT4               20
-#define SUMO_VRC_DFLT              0x30033
-#define SUMO_MGCGTTLOCAL0_DFLT     0
-#define SUMO_MGCGTTLOCAL1_DFLT     0
-#define SUMO_GICST_DFLT            19
-#define SUMO_SST_DFLT              8
-#define SUMO_VOLTAGEDROPT_DFLT     1
-#define SUMO_GFXPOWERGATINGT_DFLT  100
-
-/* sumo_dpm.c */
-void sumo_gfx_clockgating_initialize(struct radeon_device *rdev);
-void sumo_program_vc(struct radeon_device *rdev, u32 vrc);
-void sumo_clear_vc(struct radeon_device *rdev);
-void sumo_program_sstp(struct radeon_device *rdev);
-void sumo_take_smu_control(struct radeon_device *rdev, bool enable);
-void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
-					       struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
-					       ATOM_AVAILABLE_SCLK_LIST *table);
-void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
-				      struct sumo_vid_mapping_table *vid_mapping_table,
-				      ATOM_AVAILABLE_SCLK_LIST *table);
-u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
-			      struct sumo_vid_mapping_table *vid_mapping_table,
-			      u32 vid_2bit);
-u32 sumo_get_sleep_divider_from_id(u32 id);
-u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
-					 u32 sclk,
-					 u32 min_sclk_in_sr);
-
-/* sumo_smc.c */
-void sumo_initialize_m3_arb(struct radeon_device *rdev);
-void sumo_smu_pg_init(struct radeon_device *rdev);
-void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit);
-void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev,
-				      bool powersaving, bool force_nbps1);
-void sumo_boost_state_enable(struct radeon_device *rdev, bool enable);
-void sumo_enable_boost_timer(struct radeon_device *rdev);
-u32 sumo_get_running_fw_version(struct radeon_device *rdev);
-
-#endif
diff --git a/hw/display/sumod.h b/hw/display/sumod.h
deleted file mode 100644
index 7c9c2d4b86..0000000000
--- a/hw/display/sumod.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * Copyright 2012 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Alex Deucher
- */
-#ifndef _SUMOD_H_
-#define _SUMOD_H_
-
-/* pm registers */
-
-/* rcu */
-#define RCU_FW_VERSION                                  0x30c
-
-#define RCU_PWR_GATING_SEQ0                             0x408
-#define RCU_PWR_GATING_SEQ1                             0x40c
-#define RCU_PWR_GATING_CNTL                             0x410
-#       define PWR_GATING_EN                            (1 << 0)
-#       define RSVD_MASK                                (0x3 << 1)
-#       define PCV(x)                                   ((x) << 3)
-#       define PCV_MASK                                 (0x1f << 3)
-#       define PCV_SHIFT                                3
-#       define PCP(x)                                   ((x) << 8)
-#       define PCP_MASK                                 (0xf << 8)
-#       define PCP_SHIFT                                8
-#       define RPW(x)                                   ((x) << 16)
-#       define RPW_MASK                                 (0xf << 16)
-#       define RPW_SHIFT                                16
-#       define ID(x)                                    ((x) << 24)
-#       define ID_MASK                                  (0xf << 24)
-#       define ID_SHIFT                                 24
-#       define PGS(x)                                   ((x) << 28)
-#       define PGS_MASK                                 (0xf << 28)
-#       define PGS_SHIFT                                28
-
-#define RCU_ALTVDDNB_NOTIFY                             0x430
-#define RCU_LCLK_SCALING_CNTL                           0x434
-#       define LCLK_SCALING_EN                          (1 << 0)
-#       define LCLK_SCALING_TYPE                        (1 << 1)
-#       define LCLK_SCALING_TIMER_PRESCALER(x)          ((x) << 4)
-#       define LCLK_SCALING_TIMER_PRESCALER_MASK        (0xf << 4)
-#       define LCLK_SCALING_TIMER_PRESCALER_SHIFT       4
-#       define LCLK_SCALING_TIMER_PERIOD(x)             ((x) << 16)
-#       define LCLK_SCALING_TIMER_PERIOD_MASK           (0xf << 16)
-#       define LCLK_SCALING_TIMER_PERIOD_SHIFT          16
-
-#define RCU_PWR_GATING_CNTL_2                           0x4a0
-#       define MPPU(x)                                  ((x) << 0)
-#       define MPPU_MASK                                (0xffff << 0)
-#       define MPPU_SHIFT                               0
-#       define MPPD(x)                                  ((x) << 16)
-#       define MPPD_MASK                                (0xffff << 16)
-#       define MPPD_SHIFT                               16
-#define RCU_PWR_GATING_CNTL_3                           0x4a4
-#       define DPPU(x)                                  ((x) << 0)
-#       define DPPU_MASK                                (0xffff << 0)
-#       define DPPU_SHIFT                               0
-#       define DPPD(x)                                  ((x) << 16)
-#       define DPPD_MASK                                (0xffff << 16)
-#       define DPPD_SHIFT                               16
-#define RCU_PWR_GATING_CNTL_4                           0x4a8
-#       define RT(x)                                    ((x) << 0)
-#       define RT_MASK                                  (0xffff << 0)
-#       define RT_SHIFT                                 0
-#       define IT(x)                                    ((x) << 16)
-#       define IT_MASK                                  (0xffff << 16)
-#       define IT_SHIFT                                 16
-
-/* yes these two have the same address */
-#define RCU_PWR_GATING_CNTL_5                           0x504
-#define RCU_GPU_BOOST_DISABLE                           0x508
-
-#define MCU_M3ARB_INDEX                                 0x504
-#define MCU_M3ARB_PARAMS                                0x508
-
-#define RCU_GNB_PWR_REP_TIMER_CNTL                      0x50C
-
-#define RCU_SclkDpmTdpLimit01                           0x514
-#define RCU_SclkDpmTdpLimit23                           0x518
-#define RCU_SclkDpmTdpLimit47                           0x51C
-#define RCU_SclkDpmTdpLimitPG                           0x520
-
-#define GNB_TDP_LIMIT                                   0x540
-#define RCU_BOOST_MARGIN                                0x544
-#define RCU_THROTTLE_MARGIN                             0x548
-
-#define SMU_PCIE_PG_ARGS                                0x58C
-#define SMU_PCIE_PG_ARGS_2                              0x598
-#define SMU_PCIE_PG_ARGS_3                              0x59C
-
-/* mmio */
-#define RCU_STATUS                                      0x11c
-#       define GMC_PWR_GATER_BUSY                       (1 << 8)
-#       define GFX_PWR_GATER_BUSY                       (1 << 9)
-#       define UVD_PWR_GATER_BUSY                       (1 << 10)
-#       define PCIE_PWR_GATER_BUSY                      (1 << 11)
-#       define GMC_PWR_GATER_STATE                      (1 << 12)
-#       define GFX_PWR_GATER_STATE                      (1 << 13)
-#       define UVD_PWR_GATER_STATE                      (1 << 14)
-#       define PCIE_PWR_GATER_STATE                     (1 << 15)
-#       define GFX1_PWR_GATER_BUSY                      (1 << 16)
-#       define GFX2_PWR_GATER_BUSY                      (1 << 17)
-#       define GFX1_PWR_GATER_STATE                     (1 << 18)
-#       define GFX2_PWR_GATER_STATE                     (1 << 19)
-
-#define GFX_INT_REQ                                     0x120
-#       define INT_REQ                                  (1 << 0)
-#       define SERV_INDEX(x)                            ((x) << 1)
-#       define SERV_INDEX_MASK                          (0xff << 1)
-#       define SERV_INDEX_SHIFT                         1
-#define GFX_INT_STATUS                                  0x124
-#       define INT_ACK                                  (1 << 0)
-#       define INT_DONE                                 (1 << 1)
-
-#define CG_SCLK_CNTL                                    0x600
-#       define SCLK_DIVIDER(x)                          ((x) << 0)
-#       define SCLK_DIVIDER_MASK                        (0x7f << 0)
-#       define SCLK_DIVIDER_SHIFT                       0
-#define CG_SCLK_STATUS                                  0x604
-#       define SCLK_OVERCLK_DETECT                      (1 << 2)
-
-#define CG_DCLK_CNTL                                    0x610
-#       define DCLK_DIVIDER_MASK                        0x7f
-#       define DCLK_DIR_CNTL_EN                         (1 << 8)
-#define CG_DCLK_STATUS                                  0x614
-#       define DCLK_STATUS                              (1 << 0)
-#define CG_VCLK_CNTL                                    0x618
-#       define VCLK_DIVIDER_MASK                        0x7f
-#       define VCLK_DIR_CNTL_EN                         (1 << 8)
-#define CG_VCLK_STATUS                                  0x61c
-
-#define GENERAL_PWRMGT                                  0x63c
-#       define STATIC_PM_EN                             (1 << 1)
-
-#define SCLK_PWRMGT_CNTL                                0x644
-#       define SCLK_PWRMGT_OFF                          (1 << 0)
-#       define SCLK_LOW_D1                              (1 << 1)
-#       define FIR_RESET                                (1 << 4)
-#       define FIR_FORCE_TREND_SEL                      (1 << 5)
-#       define FIR_TREND_MODE                           (1 << 6)
-#       define DYN_GFX_CLK_OFF_EN                       (1 << 7)
-#       define GFX_CLK_FORCE_ON                         (1 << 8)
-#       define GFX_CLK_REQUEST_OFF                      (1 << 9)
-#       define GFX_CLK_FORCE_OFF                        (1 << 10)
-#       define GFX_CLK_OFF_ACPI_D1                      (1 << 11)
-#       define GFX_CLK_OFF_ACPI_D2                      (1 << 12)
-#       define GFX_CLK_OFF_ACPI_D3                      (1 << 13)
-#       define GFX_VOLTAGE_CHANGE_EN                    (1 << 16)
-#       define GFX_VOLTAGE_CHANGE_MODE                  (1 << 17)
-
-#define TARGET_AND_CURRENT_PROFILE_INDEX                0x66c
-#       define TARG_SCLK_INDEX(x)                       ((x) << 6)
-#       define TARG_SCLK_INDEX_MASK                     (0x7 << 6)
-#       define TARG_SCLK_INDEX_SHIFT                    6
-#       define CURR_SCLK_INDEX(x)                       ((x) << 9)
-#       define CURR_SCLK_INDEX_MASK                     (0x7 << 9)
-#       define CURR_SCLK_INDEX_SHIFT                    9
-#       define TARG_INDEX(x)                            ((x) << 12)
-#       define TARG_INDEX_MASK                          (0x7 << 12)
-#       define TARG_INDEX_SHIFT                         12
-#       define CURR_INDEX(x)                            ((x) << 15)
-#       define CURR_INDEX_MASK                          (0x7 << 15)
-#       define CURR_INDEX_SHIFT                         15
-
-#define CG_SCLK_DPM_CTRL                                0x684
-#       define SCLK_FSTATE_0_DIV(x)                     ((x) << 0)
-#       define SCLK_FSTATE_0_DIV_MASK                   (0x7f << 0)
-#       define SCLK_FSTATE_0_DIV_SHIFT                  0
-#       define SCLK_FSTATE_0_VLD                        (1 << 7)
-#       define SCLK_FSTATE_1_DIV(x)                     ((x) << 8)
-#       define SCLK_FSTATE_1_DIV_MASK                   (0x7f << 8)
-#       define SCLK_FSTATE_1_DIV_SHIFT                  8
-#       define SCLK_FSTATE_1_VLD                        (1 << 15)
-#       define SCLK_FSTATE_2_DIV(x)                     ((x) << 16)
-#       define SCLK_FSTATE_2_DIV_MASK                   (0x7f << 16)
-#       define SCLK_FSTATE_2_DIV_SHIFT                  16
-#       define SCLK_FSTATE_2_VLD                        (1 << 23)
-#       define SCLK_FSTATE_3_DIV(x)                     ((x) << 24)
-#       define SCLK_FSTATE_3_DIV_MASK                   (0x7f << 24)
-#       define SCLK_FSTATE_3_DIV_SHIFT                  24
-#       define SCLK_FSTATE_3_VLD                        (1 << 31)
-#define CG_SCLK_DPM_CTRL_2                              0x688
-#define CG_GCOOR                                        0x68c
-#       define PHC(x)                                   ((x) << 0)
-#       define PHC_MASK                                 (0x1f << 0)
-#       define PHC_SHIFT                                0
-#       define SDC(x)                                   ((x) << 9)
-#       define SDC_MASK                                 (0x3ff << 9)
-#       define SDC_SHIFT                                9
-#       define SU(x)                                    ((x) << 23)
-#       define SU_MASK                                  (0xf << 23)
-#       define SU_SHIFT                                 23
-#       define DIV_ID(x)                                ((x) << 28)
-#       define DIV_ID_MASK                              (0x7 << 28)
-#       define DIV_ID_SHIFT                             28
-
-#define CG_FTV                                          0x690
-#define CG_FFCT_0                                       0x694
-#       define UTC_0(x)                                 ((x) << 0)
-#       define UTC_0_MASK                               (0x3ff << 0)
-#       define UTC_0_SHIFT                              0
-#       define DTC_0(x)                                 ((x) << 10)
-#       define DTC_0_MASK                               (0x3ff << 10)
-#       define DTC_0_SHIFT                              10
-
-#define CG_GIT                                          0x6d8
-#       define CG_GICST(x)                              ((x) << 0)
-#       define CG_GICST_MASK                            (0xffff << 0)
-#       define CG_GICST_SHIFT                           0
-#       define CG_GIPOT(x)                              ((x) << 16)
-#       define CG_GIPOT_MASK                            (0xffff << 16)
-#       define CG_GIPOT_SHIFT                           16
-
-#define CG_SCLK_DPM_CTRL_3                              0x6e0
-#       define FORCE_SCLK_STATE(x)                      ((x) << 0)
-#       define FORCE_SCLK_STATE_MASK                    (0x7 << 0)
-#       define FORCE_SCLK_STATE_SHIFT                   0
-#       define FORCE_SCLK_STATE_EN                      (1 << 3)
-#       define GNB_TT(x)                                ((x) << 8)
-#       define GNB_TT_MASK                              (0xff << 8)
-#       define GNB_TT_SHIFT                             8
-#       define GNB_THERMTHRO_MASK                       (1 << 16)
-#       define CNB_THERMTHRO_MASK_SCLK                  (1 << 17)
-#       define DPM_SCLK_ENABLE                          (1 << 18)
-#       define GNB_SLOW_FSTATE_0_MASK                   (1 << 23)
-#       define GNB_SLOW_FSTATE_0_SHIFT                  23
-#       define FORCE_NB_PSTATE_1                        (1 << 31)
-
-#define CG_SSP                                          0x6e8
-#       define SST(x)                                   ((x) << 0)
-#       define SST_MASK                                 (0xffff << 0)
-#       define SST_SHIFT                                0
-#       define SSTU(x)                                  ((x) << 16)
-#       define SSTU_MASK                                (0xffff << 16)
-#       define SSTU_SHIFT                               16
-
-#define CG_ACPI_CNTL                                    0x70c
-#       define SCLK_ACPI_DIV(x)                         ((x) << 0)
-#       define SCLK_ACPI_DIV_MASK                       (0x7f << 0)
-#       define SCLK_ACPI_DIV_SHIFT                      0
-
-#define CG_SCLK_DPM_CTRL_4                              0x71c
-#       define DC_HDC(x)                                ((x) << 14)
-#       define DC_HDC_MASK                              (0x3fff << 14)
-#       define DC_HDC_SHIFT                             14
-#       define DC_HU(x)                                 ((x) << 28)
-#       define DC_HU_MASK                               (0xf << 28)
-#       define DC_HU_SHIFT                              28
-#define CG_SCLK_DPM_CTRL_5                              0x720
-#       define SCLK_FSTATE_BOOTUP(x)                    ((x) << 0)
-#       define SCLK_FSTATE_BOOTUP_MASK                  (0x7 << 0)
-#       define SCLK_FSTATE_BOOTUP_SHIFT                 0
-#       define TT_TP(x)                                 ((x) << 3)
-#       define TT_TP_MASK                               (0xffff << 3)
-#       define TT_TP_SHIFT                              3
-#       define TT_TU(x)                                 ((x) << 19)
-#       define TT_TU_MASK                               (0xff << 19)
-#       define TT_TU_SHIFT                              19
-#define CG_SCLK_DPM_CTRL_6                              0x724
-#define CG_AT_0                                         0x728
-#       define CG_R(x)                                  ((x) << 0)
-#       define CG_R_MASK                                (0xffff << 0)
-#       define CG_R_SHIFT                               0
-#       define CG_L(x)                                  ((x) << 16)
-#       define CG_L_MASK                                (0xffff << 16)
-#       define CG_L_SHIFT                               16
-#define CG_AT_1                                         0x72c
-#define CG_AT_2                                         0x730
-#define	CG_THERMAL_INT					0x734
-#define		DIG_THERM_INTH(x)			((x) << 8)
-#define		DIG_THERM_INTH_MASK			0x0000FF00
-#define		DIG_THERM_INTH_SHIFT			8
-#define		DIG_THERM_INTL(x)			((x) << 16)
-#define		DIG_THERM_INTL_MASK			0x00FF0000
-#define		DIG_THERM_INTL_SHIFT			16
-#define 	THERM_INT_MASK_HIGH			(1 << 24)
-#define 	THERM_INT_MASK_LOW			(1 << 25)
-#define CG_AT_3                                         0x738
-#define CG_AT_4                                         0x73c
-#define CG_AT_5                                         0x740
-#define CG_AT_6                                         0x744
-#define CG_AT_7                                         0x748
-
-#define CG_BSP_0                                        0x750
-#       define BSP(x)                                   ((x) << 0)
-#       define BSP_MASK                                 (0xffff << 0)
-#       define BSP_SHIFT                                0
-#       define BSU(x)                                   ((x) << 16)
-#       define BSU_MASK                                 (0xf << 16)
-#       define BSU_SHIFT                                16
-
-#define CG_CG_VOLTAGE_CNTL                              0x770
-#       define REQ                                      (1 << 0)
-#       define LEVEL(x)                                 ((x) << 1)
-#       define LEVEL_MASK                               (0x3 << 1)
-#       define LEVEL_SHIFT                              1
-#       define CG_VOLTAGE_EN                            (1 << 3)
-#       define FORCE                                    (1 << 4)
-#       define PERIOD(x)                                ((x) << 8)
-#       define PERIOD_MASK                              (0xffff << 8)
-#       define PERIOD_SHIFT                             8
-#       define UNIT(x)                                  ((x) << 24)
-#       define UNIT_MASK                                (0xf << 24)
-#       define UNIT_SHIFT                               24
-
-#define CG_ACPI_VOLTAGE_CNTL                            0x780
-#       define ACPI_VOLTAGE_EN                          (1 << 8)
-
-#define CG_DPM_VOLTAGE_CNTL                             0x788
-#       define DPM_STATE0_LEVEL_MASK                    (0x3 << 0)
-#       define DPM_STATE0_LEVEL_SHIFT                   0
-#       define DPM_VOLTAGE_EN                           (1 << 16)
-
-#define CG_PWR_GATING_CNTL                              0x7ac
-#       define DYN_PWR_DOWN_EN                          (1 << 0)
-#       define ACPI_PWR_DOWN_EN                         (1 << 1)
-#       define GFX_CLK_OFF_PWR_DOWN_EN                  (1 << 2)
-#       define IOC_DISGPU_PWR_DOWN_EN                   (1 << 3)
-#       define FORCE_POWR_ON                            (1 << 4)
-#       define PGP(x)                                   ((x) << 8)
-#       define PGP_MASK                                 (0xffff << 8)
-#       define PGP_SHIFT                                8
-#       define PGU(x)                                   ((x) << 24)
-#       define PGU_MASK                                 (0xf << 24)
-#       define PGU_SHIFT                                24
-
-#define CG_CGTT_LOCAL_0                                 0x7d0
-#define CG_CGTT_LOCAL_1                                 0x7d4
-
-#define DEEP_SLEEP_CNTL                                 0x818
-#       define R_DIS                                    (1 << 3)
-#       define HS(x)                                    ((x) << 4)
-#       define HS_MASK                                  (0xfff << 4)
-#       define HS_SHIFT                                 4
-#       define ENABLE_DS                                (1 << 31)
-#define DEEP_SLEEP_CNTL2                                0x81c
-#       define LB_UFP_EN                                (1 << 0)
-#       define INOUT_C(x)                               ((x) << 4)
-#       define INOUT_C_MASK                             (0xff << 4)
-#       define INOUT_C_SHIFT                            4
-
-#define CG_SCRATCH2                                     0x824
-
-#define CG_SCLK_DPM_CTRL_11                             0x830
-
-#define HW_REV   					0x5564
-#       define ATI_REV_ID_MASK                          (0xf << 28)
-#       define ATI_REV_ID_SHIFT                         28
-/* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */
-
-#define DOUT_SCRATCH3   				0x611c
-
-#define GB_ADDR_CONFIG  				0x98f8
-
-#endif
diff --git a/hw/display/trinity_dpm.h b/hw/display/trinity_dpm.h
deleted file mode 100644
index c261657750..0000000000
--- a/hw/display/trinity_dpm.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Copyright 2012 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __TRINITY_DPM_H__
-#define __TRINITY_DPM_H__
-
-#include "sumo_dpm.h"
-
-#define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0)
-
-struct trinity_pl {
-	u32 sclk;
-	u8 vddc_index;
-	u8 ds_divider_index;
-	u8 ss_divider_index;
-	u8 allow_gnb_slow;
-	u8 force_nbp_state;
-	u8 display_wm;
-	u8 vce_wm;
-};
-
-#define TRINITY_POWERSTATE_FLAGS_NBPS_FORCEHIGH  (1 << 0)
-#define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1 << 1)
-#define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOLOW  (1 << 2)
-
-#define TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE    (1 << 0)
-
-struct trinity_ps {
-	u32 num_levels;
-	struct trinity_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
-
-	u32 nbps_flags;
-	u32 bapm_flags;
-
-	u8 Dpm0PgNbPsLo;
-	u8 Dpm0PgNbPsHi;
-	u8 DpmXNbPsLo;
-	u8 DpmXNbPsHi;
-
-	u32 vclk_low_divider;
-	u32 vclk_high_divider;
-	u32 dclk_low_divider;
-	u32 dclk_high_divider;
-};
-
-#define TRINITY_NUM_NBPSTATES   4
-
-struct trinity_uvd_clock_table_entry
-{
-	u32 vclk;
-	u32 dclk;
-	u8 vclk_did;
-	u8 dclk_did;
-	u8 rsv[2];
-};
-
-struct trinity_sys_info {
-	u32 bootup_uma_clk;
-	u32 bootup_sclk;
-	u32 min_sclk;
-	u32 dentist_vco_freq;
-	u32 nb_dpm_enable;
-	u32 nbp_mclk[TRINITY_NUM_NBPSTATES];
-	u32 nbp_nclk[TRINITY_NUM_NBPSTATES];
-	u16 nbp_voltage_index[TRINITY_NUM_NBPSTATES];
-	u16 bootup_nb_voltage_index;
-	u8 htc_tmp_lmt;
-	u8 htc_hyst_lmt;
-	struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
-	struct sumo_vid_mapping_table vid_mapping_table;
-	u32 uma_channel_number;
-	struct trinity_uvd_clock_table_entry uvd_clock_table_entries[4];
-};
-
-struct trinity_power_info {
-	u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
-	u32 dpm_interval;
-	u32 thermal_auto_throttling;
-	struct trinity_sys_info sys_info;
-	struct trinity_pl boot_pl;
-	u32 min_sclk_did;
-	bool enable_nbps_policy;
-	bool voltage_drop_in_dce;
-	bool override_dynamic_mgpg;
-	bool enable_gfx_clock_gating;
-	bool enable_gfx_power_gating;
-	bool enable_mg_clock_gating;
-	bool enable_gfx_dynamic_mgpg;
-	bool enable_auto_thermal_throttling;
-	bool enable_dpm;
-	bool enable_sclk_ds;
-	bool enable_bapm;
-	bool uvd_dpm;
-	struct radeon_ps current_rps;
-	struct trinity_ps current_ps;
-	struct radeon_ps requested_rps;
-	struct trinity_ps requested_ps;
-};
-
-#define TRINITY_AT_DFLT            30
-
-/* trinity_smc.c */
-int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable);
-int trinity_dpm_config(struct radeon_device *rdev, bool enable);
-int trinity_uvd_dpm_config(struct radeon_device *rdev);
-int trinity_dpm_force_state(struct radeon_device *rdev, u32 n);
-int trinity_dpm_n_levels_disabled(struct radeon_device *rdev, u32 n);
-int trinity_dpm_no_forced_level(struct radeon_device *rdev);
-int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev,
-					  bool enable);
-int trinity_gfx_dynamic_mgpg_config(struct radeon_device *rdev);
-void trinity_acquire_mutex(struct radeon_device *rdev);
-void trinity_release_mutex(struct radeon_device *rdev);
-
-#endif
diff --git a/hw/display/trinityd.h b/hw/display/trinityd.h
deleted file mode 100644
index fd32e27717..0000000000
--- a/hw/display/trinityd.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * Copyright 2012 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Alex Deucher
- */
-#ifndef _TRINITYD_H_
-#define _TRINITYD_H_
-
-/* pm registers */
-
-/* cg */
-#define CG_CGTT_LOCAL_0                                 0x0
-#define CG_CGTT_LOCAL_1                                 0x1
-
-/* smc */
-#define SMU_SCLK_DPM_STATE_0_CNTL_0                     0x1f000
-#       define STATE_VALID(x)                           ((x) << 0)
-#       define STATE_VALID_MASK                         (0xff << 0)
-#       define STATE_VALID_SHIFT                        0
-#       define CLK_DIVIDER(x)                           ((x) << 8)
-#       define CLK_DIVIDER_MASK                         (0xff << 8)
-#       define CLK_DIVIDER_SHIFT                        8
-#       define VID(x)                                   ((x) << 16)
-#       define VID_MASK                                 (0xff << 16)
-#       define VID_SHIFT                                16
-#       define LVRT(x)                                  ((x) << 24)
-#       define LVRT_MASK                                (0xff << 24)
-#       define LVRT_SHIFT                               24
-#define SMU_SCLK_DPM_STATE_0_CNTL_1                     0x1f004
-#       define DS_DIV(x)                                ((x) << 0)
-#       define DS_DIV_MASK                              (0xff << 0)
-#       define DS_DIV_SHIFT                             0
-#       define DS_SH_DIV(x)                             ((x) << 8)
-#       define DS_SH_DIV_MASK                           (0xff << 8)
-#       define DS_SH_DIV_SHIFT                          8
-#       define DISPLAY_WM(x)                            ((x) << 16)
-#       define DISPLAY_WM_MASK                          (0xff << 16)
-#       define DISPLAY_WM_SHIFT                         16
-#       define VCE_WM(x)                                ((x) << 24)
-#       define VCE_WM_MASK                              (0xff << 24)
-#       define VCE_WM_SHIFT                             24
-
-#define SMU_SCLK_DPM_STATE_0_CNTL_3                     0x1f00c
-#       define GNB_SLOW(x)                              ((x) << 0)
-#       define GNB_SLOW_MASK                            (0xff << 0)
-#       define GNB_SLOW_SHIFT                           0
-#       define FORCE_NBPS1(x)                           ((x) << 8)
-#       define FORCE_NBPS1_MASK                         (0xff << 8)
-#       define FORCE_NBPS1_SHIFT                        8
-#define SMU_SCLK_DPM_STATE_0_AT                         0x1f010
-#       define AT(x)                                    ((x) << 0)
-#       define AT_MASK                                  (0xff << 0)
-#       define AT_SHIFT                                 0
-
-#define SMU_SCLK_DPM_STATE_0_PG_CNTL                    0x1f014
-#       define PD_SCLK_DIVIDER(x)                       ((x) << 16)
-#       define PD_SCLK_DIVIDER_MASK                     (0xff << 16)
-#       define PD_SCLK_DIVIDER_SHIFT                    16
-
-#define SMU_SCLK_DPM_STATE_1_CNTL_0                     0x1f020
-
-#define SMU_SCLK_DPM_CNTL                               0x1f100
-#       define SCLK_DPM_EN(x)                           ((x) << 0)
-#       define SCLK_DPM_EN_MASK                         (0xff << 0)
-#       define SCLK_DPM_EN_SHIFT                        0
-#       define SCLK_DPM_BOOT_STATE(x)                   ((x) << 16)
-#       define SCLK_DPM_BOOT_STATE_MASK                 (0xff << 16)
-#       define SCLK_DPM_BOOT_STATE_SHIFT                16
-#       define VOLTAGE_CHG_EN(x)                        ((x) << 24)
-#       define VOLTAGE_CHG_EN_MASK                      (0xff << 24)
-#       define VOLTAGE_CHG_EN_SHIFT                     24
-
-#define SMU_SCLK_DPM_TT_CNTL                            0x1f108
-#       define SCLK_TT_EN(x)                            ((x) << 0)
-#       define SCLK_TT_EN_MASK                          (0xff << 0)
-#       define SCLK_TT_EN_SHIFT                         0
-#define SMU_SCLK_DPM_TTT                                0x1f10c
-#       define LT(x)                                    ((x) << 0)
-#       define LT_MASK                                  (0xffff << 0)
-#       define LT_SHIFT                                 0
-#       define HT(x)                                    ((x) << 16)
-#       define HT_MASK                                  (0xffff << 16)
-#       define HT_SHIFT                                 16
-
-#define SMU_UVD_DPM_STATES                              0x1f1a0
-#define SMU_UVD_DPM_CNTL                                0x1f1a4
-
-#define SMU_S_PG_CNTL                                   0x1f118
-#       define DS_PG_EN(x)                              ((x) << 16)
-#       define DS_PG_EN_MASK                            (0xff << 16)
-#       define DS_PG_EN_SHIFT                           16
-
-#define GFX_POWER_GATING_CNTL                           0x1f38c
-#       define PDS_DIV(x)                               ((x) << 0)
-#       define PDS_DIV_MASK                             (0xff << 0)
-#       define PDS_DIV_SHIFT                            0
-#       define SSSD(x)                                  ((x) << 8)
-#       define SSSD_MASK                                (0xff << 8)
-#       define SSSD_SHIFT                               8
-
-#define PM_CONFIG                                       0x1f428
-#       define SVI_Mode                                 (1 << 29)
-
-#define PM_I_CNTL_1                                     0x1f464
-#       define SCLK_DPM(x)                              ((x) << 0)
-#       define SCLK_DPM_MASK                            (0xff << 0)
-#       define SCLK_DPM_SHIFT                           0
-#       define DS_PG_CNTL(x)                            ((x) << 16)
-#       define DS_PG_CNTL_MASK                          (0xff << 16)
-#       define DS_PG_CNTL_SHIFT                         16
-#define PM_TP                                           0x1f468
-
-#define NB_PSTATE_CONFIG                                0x1f5f8
-#       define Dpm0PgNbPsLo(x)                          ((x) << 0)
-#       define Dpm0PgNbPsLo_MASK                        (3 << 0)
-#       define Dpm0PgNbPsLo_SHIFT                       0
-#       define Dpm0PgNbPsHi(x)                          ((x) << 2)
-#       define Dpm0PgNbPsHi_MASK                        (3 << 2)
-#       define Dpm0PgNbPsHi_SHIFT                       2
-#       define DpmXNbPsLo(x)                            ((x) << 4)
-#       define DpmXNbPsLo_MASK                          (3 << 4)
-#       define DpmXNbPsLo_SHIFT                         4
-#       define DpmXNbPsHi(x)                            ((x) << 6)
-#       define DpmXNbPsHi_MASK                          (3 << 6)
-#       define DpmXNbPsHi_SHIFT                         6
-
-#define DC_CAC_VALUE                                    0x1f908
-
-#define GPU_CAC_AVRG_CNTL                               0x1f920
-#       define WINDOW_SIZE(x)                           ((x) << 0)
-#       define WINDOW_SIZE_MASK                         (0xff << 0)
-#       define WINDOW_SIZE_SHIFT                        0
-
-#define CC_SMU_MISC_FUSES                               0xe0001004
-#       define MinSClkDid(x)                   ((x) << 2)
-#       define MinSClkDid_MASK                 (0x7f << 2)
-#       define MinSClkDid_SHIFT                2
-
-#define CC_SMU_TST_EFUSE1_MISC                          0xe000101c
-#       define RB_BACKEND_DISABLE(x)                    ((x) << 16)
-#       define RB_BACKEND_DISABLE_MASK                  (3 << 16)
-#       define RB_BACKEND_DISABLE_SHIFT                 16
-
-#define SMU_SCRATCH_A                                   0xe0003024
-
-#define SMU_SCRATCH0                                    0xe0003040
-
-/* mmio */
-#define SMC_INT_REQ                                     0x220
-
-#define SMC_MESSAGE_0                                   0x22c
-#define SMC_RESP_0                                      0x230
-
-#define GENERAL_PWRMGT                                  0x670
-#       define GLOBAL_PWRMGT_EN                         (1 << 0)
-
-#define SCLK_PWRMGT_CNTL                                0x678
-#       define DYN_PWR_DOWN_EN                          (1 << 2)
-#       define RESET_BUSY_CNT                           (1 << 4)
-#       define RESET_SCLK_CNT                           (1 << 5)
-#       define DYN_GFX_CLK_OFF_EN                       (1 << 7)
-#       define GFX_CLK_FORCE_ON                         (1 << 8)
-#       define DYNAMIC_PM_EN                            (1 << 21)
-
-#define TARGET_AND_CURRENT_PROFILE_INDEX                0x684
-#       define TARGET_STATE(x)                          ((x) << 0)
-#       define TARGET_STATE_MASK                        (0xf << 0)
-#       define TARGET_STATE_SHIFT                       0
-#       define CURRENT_STATE(x)                         ((x) << 4)
-#       define CURRENT_STATE_MASK                       (0xf << 4)
-#       define CURRENT_STATE_SHIFT                      4
-
-#define CG_GIPOTS                                       0x6d8
-#       define CG_GIPOT(x)                              ((x) << 16)
-#       define CG_GIPOT_MASK                            (0xffff << 16)
-#       define CG_GIPOT_SHIFT                           16
-
-#define CG_PG_CTRL                                      0x6e0
-#       define SP(x)                                    ((x) << 0)
-#       define SP_MASK                                  (0xffff << 0)
-#       define SP_SHIFT                                 0
-#       define SU(x)                                    ((x) << 16)
-#       define SU_MASK                                  (0xffff << 16)
-#       define SU_SHIFT                                 16
-
-#define CG_MISC_REG                                     0x708
-
-#define CG_THERMAL_INT_CTRL                             0x738
-#       define DIG_THERM_INTH(x)                        ((x) << 0)
-#       define DIG_THERM_INTH_MASK                      (0xff << 0)
-#       define DIG_THERM_INTH_SHIFT                     0
-#       define DIG_THERM_INTL(x)                        ((x) << 8)
-#       define DIG_THERM_INTL_MASK                      (0xff << 8)
-#       define DIG_THERM_INTL_SHIFT                     8
-#       define THERM_INTH_MASK                          (1 << 24)
-#       define THERM_INTL_MASK                          (1 << 25)
-
-#define CG_CG_VOLTAGE_CNTL                              0x770
-#       define EN                                       (1 << 9)
-
-#define HW_REV   					0x5564
-#       define ATI_REV_ID_MASK                          (0xf << 28)
-#       define ATI_REV_ID_SHIFT                         28
-/* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */
-
-#define CGTS_SM_CTRL_REG                                0x9150
-
-#define GB_ADDR_CONFIG                                  0x98f8
-
-#endif
