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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d20sm8818922wra.4.2019.11.01.01.51.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2019 01:51:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/11] target/arm: Allow SVE to be disabled via a CPU property Date: Fri, 1 Nov 2019 08:51:32 +0000 Message-Id: <20191101085140.5205-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191101085140.5205-1-peter.maydell@linaro.org> References: <20191101085140.5205-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via a CPU property") we can disable the 'max' cpu model's VFP and neon features, but there's no way to disable SVE. Add the 'sve=on|off' property to give it that flexibility. We also rename cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them to follow the typical *_get/set_ pattern. Signed-off-by: Andrew Jones Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Tested-by: Masayoshi Mizuma Reviewed-by: Beata Michalska Message-id: 20191031142734.8590-4-drjones@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 ++- target/arm/cpu64.c | 52 ++++++++++++++++++++++++++++++++++------ target/arm/monitor.c | 2 +- tests/arm-cpu-features.c | 1 + 4 files changed, 49 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ab3e1a03616..72a27ec4b0e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -200,7 +200,8 @@ static void arm_cpu_reset(CPUState *s) env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cptr_el[3] |= CPTR_EZ; /* with maximum vector length */ - env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; + env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ? + cpu->sve_max_vq - 1 : 0; env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; /* diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d7f5bf610a7..89a8ae77fe8 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -256,15 +256,23 @@ static void aarch64_a72_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } -static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { ARMCPU *cpu = ARM_CPU(obj); - visit_type_uint32(v, name, &cpu->sve_max_vq, errp); + uint32_t value; + + /* All vector lengths are disabled when SVE is off. */ + if (!cpu_isar_feature(aa64_sve, cpu)) { + value = 0; + } else { + value = cpu->sve_max_vq; + } + visit_type_uint32(v, name, &value, errp); } -static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { ARMCPU *cpu = ARM_CPU(obj); Error *err = NULL; @@ -279,6 +287,34 @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, error_propagate(errp, err); } +static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + bool value = cpu_isar_feature(aa64_sve, cpu); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + Error *err = NULL; + bool value; + uint64_t t; + + visit_type_bool(v, name, &value, &err); + if (err) { + error_propagate(errp, err); + return; + } + + t = cpu->isar.id_aa64pfr0; + t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); + cpu->isar.id_aa64pfr0 = t; +} + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -391,8 +427,10 @@ static void aarch64_max_initfn(Object *obj) #endif cpu->sve_max_vq = ARM_MAX_VQ; - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq, - cpu_max_set_sve_vq, NULL, NULL, &error_fatal); + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, + cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal); + object_property_add(obj, "sve", "bool", cpu_arm_get_sve, + cpu_arm_set_sve, NULL, NULL, &error_fatal); } } diff --git a/target/arm/monitor.c b/target/arm/monitor.c index 560970de7f5..2209b27b9a0 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -97,7 +97,7 @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp) * then the order that considers those dependencies must be used. */ static const char *cpu_model_advertised_features[] = { - "aarch64", "pmu", + "aarch64", "pmu", "sve", NULL }; diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c index 6ebb03d7ad6..d5e18eb6662 100644 --- a/tests/arm-cpu-features.c +++ b/tests/arm-cpu-features.c @@ -197,6 +197,7 @@ static void test_query_cpu_model_expansion(const void *data) if (g_str_equal(qtest_get_arch(), "aarch64")) { assert_has_feature(qts, "max", "aarch64"); + assert_has_feature(qts, "max", "sve"); assert_has_feature(qts, "cortex-a57", "pmu"); assert_has_feature(qts, "cortex-a57", "aarch64");