From patchwork Mon Oct 28 16:34:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1185617 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.b="RMagsn1T"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4722TC0XrYz9sP3 for ; Tue, 29 Oct 2019 04:56:13 +1100 (AEDT) Received: from localhost ([::1]:39828 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP9FS-0003vz-66 for incoming@patchwork.ozlabs.org; Mon, 28 Oct 2019 13:56:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41092) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP7z7-00021q-MW for qemu-devel@nongnu.org; Mon, 28 Oct 2019 12:35:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iP7z6-0007F9-FU for qemu-devel@nongnu.org; Mon, 28 Oct 2019 12:35:13 -0400 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:39417 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iP7z6-0007EK-Bb for qemu-devel@nongnu.org; Mon, 28 Oct 2019 12:35:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1572280511; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mPc092PHODzreV/kPpF7b8LLvV0SzNzKY/NFFvHaLRU=; b=RMagsn1TLlNTLqQVkq3AJm6Ygkoxa4ADZiGIyylblm4N1SBtHWpGRKx0jRsi0cpQUXX5I5 hPxfJEzWRPfLn7yLKKXltXTfnnuW/L0JZVLUyHcvHpqMCZ+YdJLSQUeOsO2wD7jUa6H7go 7B3bVgTuLNav5K35yY7KPbLEPiPd7cQ= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-244-ETrxUxEKPpuEvgW4Pu6YOw-1; Mon, 28 Oct 2019 12:35:07 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id EC2FF1005509; Mon, 28 Oct 2019 16:35:05 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-87.brq.redhat.com [10.40.204.87]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 836E31C941; Mon, 28 Oct 2019 16:35:01 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 02/20] piix4: Add the Reset Control Register Date: Mon, 28 Oct 2019 17:34:29 +0100 Message-Id: <20191028163447.18541-3-philmd@redhat.com> In-Reply-To: <20191028163447.18541-1-philmd@redhat.com> References: <20191028163447.18541-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-MC-Unique: ETrxUxEKPpuEvgW4Pu6YOw-1 X-Mimecast-Spam-Score: 0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S . Tsirkin" , Li Qiang , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Markovic , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Hervé Poussineau The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Hervé Poussineau Message-Id: <20171216090228.28505-7-hpoussin@reactos.org> Reviewed-by: Aleksandar Markovic Reviewed-by: Li Qiang [PMD: rebased, updated includes] Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 890d999abf..7a1361a9dd 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -2,6 +2,7 @@ * QEMU PIIX4 PCI Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Hervé Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,11 +29,17 @@ #include "hw/isa/isa.h" #include "hw/sysbus.h" #include "migration/vmstate.h" +#include "sysemu/reset.h" +#include "sysemu/runstate.h" PCIDevice *piix4_dev; typedef struct PIIX4State { PCIDevice dev; + + /* Reset Control Register */ + MemoryRegion rcr_mem; + uint8_t rcr; } PIIX4State; #define TYPE_PIIX4_PCI_DEVICE "PIIX4" @@ -87,15 +94,51 @@ static const VMStateDescription vmstate_piix4 = { } }; +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int len) +{ + PIIX4State *s = opaque; + + if (val & 4) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + } + + s->rcr = val & 2; /* keep System Reset type only */ +} + +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +{ + PIIX4State *s = opaque; + + return s->rcr; +} + +static const MemoryRegionOps piix4_rcr_ops = { + .read = piix4_rcr_read, + .write = piix4_rcr_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + static void piix4_realize(PCIDevice *dev, Error **errp) { - PIIX4State *d = PIIX4_PCI_DEVICE(dev); + PIIX4State *s = PIIX4_PCI_DEVICE(dev); - if (!isa_bus_new(DEVICE(d), pci_address_space(dev), + if (!isa_bus_new(DEVICE(dev), pci_address_space(dev), pci_address_space_io(dev), errp)) { return; } - piix4_dev = &d->dev; + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(dev), + RCR_IOPORT, &s->rcr_mem, 1); + + piix4_dev = dev; } int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)