diff mbox series

[v2,03/12] target/sparc: Define an enumeration for accessing env->regwptr

Message ID 20191025113921.9412-4-richard.henderson@linaro.org
State New
Headers show
Series linux-user sparc fixes | expand

Commit Message

Richard Henderson Oct. 25, 2019, 11:39 a.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/cpu.h | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

Comments

Laurent Vivier Nov. 5, 2019, 9:45 a.m. UTC | #1 
Le 25/10/2019 à 13:39, Richard Henderson a écrit :
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/sparc/cpu.h | 33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index 778aa8e073..ae97c7d9f7 100644
> --- a/target/sparc/cpu.h
> +++ b/target/sparc/cpu.h
> @@ -13,6 +13,39 @@
>  
>  /*#define EXCP_INTERRUPT 0x100*/
>  
> +/* Windowed register indexes.  */
> +enum {
> +    WREG_O0,
> +    WREG_O1,
> +    WREG_O2,
> +    WREG_O3,
> +    WREG_O4,
> +    WREG_O5,
> +    WREG_O6,
> +    WREG_O7,
> +
> +    WREG_L0,
> +    WREG_L1,
> +    WREG_L2,
> +    WREG_L3,
> +    WREG_L4,
> +    WREG_L5,
> +    WREG_L6,
> +    WREG_L7,
> +
> +    WREG_I0,
> +    WREG_I1,
> +    WREG_I2,
> +    WREG_I3,
> +    WREG_I4,
> +    WREG_I5,
> +    WREG_I6,
> +    WREG_I7,
> +
> +    WREG_SP = WREG_O6,
> +    WREG_FP = WREG_I6,
> +};
> +
>  /* trap definitions */
>  #ifndef TARGET_SPARC64
>  #define TT_TFAULT   0x01
> 

Applied to my linux-user branch.

Thanks,
Laurent
diff mbox series

Patch

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 778aa8e073..ae97c7d9f7 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -13,6 +13,39 @@ 
 
 /*#define EXCP_INTERRUPT 0x100*/
 
+/* Windowed register indexes.  */
+enum {
+    WREG_O0,
+    WREG_O1,
+    WREG_O2,
+    WREG_O3,
+    WREG_O4,
+    WREG_O5,
+    WREG_O6,
+    WREG_O7,
+
+    WREG_L0,
+    WREG_L1,
+    WREG_L2,
+    WREG_L3,
+    WREG_L4,
+    WREG_L5,
+    WREG_L6,
+    WREG_L7,
+
+    WREG_I0,
+    WREG_I1,
+    WREG_I2,
+    WREG_I3,
+    WREG_I4,
+    WREG_I5,
+    WREG_I6,
+    WREG_I7,
+
+    WREG_SP = WREG_O6,
+    WREG_FP = WREG_I6,
+};
+
 /* trap definitions */
 #ifndef TARGET_SPARC64
 #define TT_TFAULT   0x01