From patchwork Tue Oct 22 16:21:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= X-Patchwork-Id: 1181504 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.b="DSNKM2Zk"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46yK216kbWz9sPf for ; Wed, 23 Oct 2019 03:38:17 +1100 (AEDT) Received: from localhost ([::1]:35902 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMxAl-0007Db-ER for incoming@patchwork.ozlabs.org; Tue, 22 Oct 2019 12:38:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38688) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMwxD-0008Bx-D5 for qemu-devel@nongnu.org; Tue, 22 Oct 2019 12:24:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iMwxB-0007se-Tu for qemu-devel@nongnu.org; Tue, 22 Oct 2019 12:24:15 -0400 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:56279 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iMwxB-0007sO-Pw for qemu-devel@nongnu.org; Tue, 22 Oct 2019 12:24:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571761453; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NTsqm6EGzYbEhal4RyEW+fMR+YdqVobEJtdxNWuQUac=; b=DSNKM2ZkzQZcPzFIkEl3eFn1ixGxAtWXhJu7LQy7hqiUveKpvd85D4/kNm+UrWnQS4lhW0 LsFOh/KyzD26KDYOlwu0t0+j9CpZ16TD98AZ+bcCZ4k701P1+wvHisXASs5ZtjFx3sOoAJ 4eX+5f/9hkfY2rhXLSXR+1gRMu5YxSM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-304-NQ1U3zqVMNm1PWmQVGn_qQ-1; Tue, 22 Oct 2019 12:24:11 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 67F4F107AD31; Tue, 22 Oct 2019 16:24:09 +0000 (UTC) Received: from localhost (ovpn-112-21.ams2.redhat.com [10.36.112.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id 66AF05D6A9; Tue, 22 Oct 2019 16:24:02 +0000 (UTC) From: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= To: qemu-devel@nongnu.org Subject: [PATCH v2 20/28] sparc: move PIL irq handling to cpu.c Date: Tue, 22 Oct 2019 18:21:29 +0200 Message-Id: <20191022162137.27161-21-marcandre.lureau@redhat.com> In-Reply-To: <20191022162137.27161-1-marcandre.lureau@redhat.com> References: <20191022162137.27161-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: NQ1U3zqVMNm1PWmQVGn_qQ-1 X-Mimecast-Spam-Score: 0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , Peter Maydell , "Michael S. Tsirkin" , Jason Wang , Mark Cave-Ayland , KONRAD Frederic , "Edgar E. Iglesias" , Aleksandar Rikalo , Magnus Damm , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Artyom Tarasenko , Eduardo Habkost , Fabien Chouteau , qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-ppc@nongnu.org, Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Rather than tweaking CPU bits from leon3 machine, move it to cpu.c. Suggested-by: Peter Maydell Signed-off-by: Marc-André Lureau --- hw/sparc/leon3.c | 37 ------------------------------------- hw/sparc/trace-events | 4 ---- target/sparc/cpu.c | 39 +++++++++++++++++++++++++++++++++++++++ target/sparc/trace-events | 4 ++++ 4 files changed, 43 insertions(+), 41 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 6db6ea9b5c..fec460f524 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -38,7 +38,6 @@ #include "hw/boards.h" #include "hw/loader.h" #include "elf.h" -#include "trace.h" #include "exec/address-spaces.h" #include "hw/sparc/grlib.h" @@ -143,41 +142,6 @@ void leon3_irq_ack(void *irq_manager, int intno) grlib_irqmp_ack((DeviceState *)irq_manager, intno); } -static void leon3_set_pil_in(void *opaque, int n, int level) -{ - CPUSPARCState *env = opaque; - uint32_t pil_in = level; - CPUState *cs; - - assert(env != NULL); - - env->pil_in = pil_in; - - if (env->pil_in && (env->interrupt_index == 0 || - (env->interrupt_index & ~15) == TT_EXTINT)) { - unsigned int i; - - for (i = 15; i > 0; i--) { - if (env->pil_in & (1 << i)) { - int old_interrupt = env->interrupt_index; - - env->interrupt_index = TT_EXTINT | i; - if (old_interrupt != env->interrupt_index) { - cs = env_cpu(env); - trace_leon3_set_irq(i); - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } - break; - } - } - } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { - cs = env_cpu(env); - trace_leon3_reset_irq(env->interrupt_index & 15); - env->interrupt_index = 0; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } -} - static void leon3_generic_hw_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; @@ -226,7 +190,6 @@ static void leon3_generic_hw_init(MachineState *machine) /* Allocate IRQ manager */ dev = qdev_create(NULL, TYPE_GRLIB_IRQMP); - env->pil_irq = qemu_allocate_irq(leon3_set_pil_in, env, 0); qdev_connect_gpio_out_named(dev, "grlib-irq", 0, env->pil_irq); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET); diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events index 355b07ae05..0299df24d4 100644 --- a/hw/sparc/trace-events +++ b/hw/sparc/trace-events @@ -15,7 +15,3 @@ sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush 0x%x" sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr 0x%"PRIx64" => pte 0x%"PRIx64", *pte = 0x%x" sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva 0x%"PRIx64" => pa 0x%"PRIx64" iopte = 0x%x" sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64 - -# leon3.c -leon3_set_irq(int intno) "Set CPU IRQ %d" -leon3_reset_irq(int intno) "Reset CPU IRQ %d" diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bc65929552..693ffef3d1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -25,6 +25,8 @@ #include "exec/exec-all.h" #include "hw/qdev-properties.h" #include "qapi/visitor.h" +#include "trace.h" +#include "hw/irq.h" //#define DEBUG_FEATURES @@ -540,6 +542,41 @@ static const sparc_def_t sparc_defs[] = { #endif }; +static void sparc_set_pil_in(void *opaque, int n, int level) +{ + CPUSPARCState *env = opaque; + uint32_t pil_in = level; + CPUState *cs; + + assert(env != NULL); + + env->pil_in = pil_in; + + if (env->pil_in && (env->interrupt_index == 0 || + (env->interrupt_index & ~15) == TT_EXTINT)) { + unsigned int i; + + for (i = 15; i > 0; i--) { + if (env->pil_in & (1 << i)) { + int old_interrupt = env->interrupt_index; + + env->interrupt_index = TT_EXTINT | i; + if (old_interrupt != env->interrupt_index) { + cs = env_cpu(env); + trace_sparc_set_irq(i); + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } + break; + } + } + } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { + cs = env_cpu(env); + trace_sparc_reset_irq(env->interrupt_index & 15); + env->interrupt_index = 0; + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + static const char * const feature_name[] = { "float", "float128", @@ -762,6 +799,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) env->version |= env->def.nwindows - 1; #endif + env->pil_irq = qemu_allocate_irq(sparc_set_pil_in, env, 0); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/sparc/trace-events b/target/sparc/trace-events index 6a064e2327..01c3174067 100644 --- a/target/sparc/trace-events +++ b/target/sparc/trace-events @@ -26,3 +26,7 @@ win_helper_no_switch_pstate(uint32_t new_pstate_regs) "change_pstate: regs new=0 win_helper_wrpil(uint32_t psrpil, uint32_t new_pil) "old=0x%x new=0x%x" win_helper_done(uint32_t tl) "tl=%d" win_helper_retry(uint32_t tl) "tl=%d" + +# cpu.c +sparc_set_irq(int intno) "Set CPU IRQ %d" +sparc_reset_irq(int intno) "Reset CPU IRQ %d"