From patchwork Fri Oct 18 13:47:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1179389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46vnf92m2Jz9sNx for ; Sat, 19 Oct 2019 00:57:21 +1100 (AEDT) Received: from localhost ([::1]:40430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLSkp-0005Iu-89 for incoming@patchwork.ozlabs.org; Fri, 18 Oct 2019 09:57:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54966) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLSdH-0004PO-T4 for qemu-devel@nongnu.org; Fri, 18 Oct 2019 09:49:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLSdG-00064N-70 for qemu-devel@nongnu.org; Fri, 18 Oct 2019 09:49:31 -0400 Received: from mx1.redhat.com ([209.132.183.28]:23220) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iLSdF-00063y-UU for qemu-devel@nongnu.org; Fri, 18 Oct 2019 09:49:30 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 154BC11A1F; Fri, 18 Oct 2019 13:49:29 +0000 (UTC) Received: from x1w.redhat.com (unknown [10.40.205.74]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4969460BF4; Fri, 18 Oct 2019 13:49:17 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 08/20] piix4: Add a MC146818 RTC Controller as specified in datasheet Date: Fri, 18 Oct 2019 15:47:42 +0200 Message-Id: <20191018134754.16362-9-philmd@redhat.com> In-Reply-To: <20191018134754.16362-1-philmd@redhat.com> References: <20191018134754.16362-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Fri, 18 Oct 2019 13:49:29 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , "Michael S. Tsirkin" , Paul Durrant , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Paolo Bonzini , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Markovic , Igor Mammedov , Anthony Perard , xen-devel@lists.xenproject.org, Aleksandar Rikalo , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Aurelien Jarno , Eduardo Habkost Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Remove mc146818rtc instanciated in malta board, to not have it twice. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Hervé Poussineau Message-Id: <20171216090228.28505-13-hpoussin@reactos.org> [PMD: rebased, set RTC base_year to 2000] Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 3 ++- hw/acpi/piix4.c | 2 +- hw/i386/acpi-build.c | 3 +-- hw/i386/pc_piix.c | 1 + hw/isa/piix4.c | 22 ++++++++++++++++++++++ hw/mips/mips_malta.c | 4 +--- include/hw/acpi/piix4.h | 6 ------ include/hw/i386/pc.h | 6 ------ include/hw/southbridge/piix.h | 20 ++++++++++++++++++++ 9 files changed, 48 insertions(+), 19 deletions(-) delete mode 100644 include/hw/acpi/piix4.h create mode 100644 include/hw/southbridge/piix.h diff --git a/MAINTAINERS b/MAINTAINERS index c9f625fc2e..556f58bd8c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1235,7 +1235,7 @@ F: hw/i2c/smbus_ich9.c F: hw/acpi/piix4.c F: hw/acpi/ich9.c F: include/hw/acpi/ich9.h -F: include/hw/acpi/piix4.h +F: include/hw/southbridge/piix.h F: hw/misc/sga.c F: hw/isa/apm.c F: include/hw/isa/apm.h @@ -1720,6 +1720,7 @@ M: Hervé Poussineau M: Philippe Mathieu-Daudé S: Maintained F: hw/isa/piix4.c +F: include/hw/southbridge/piix.h Firmware configuration (fw_cfg) M: Philippe Mathieu-Daudé diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 4e079b39bd..2efd1605b8 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "hw/i386/pc.h" +#include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/isa/apm.h" #include "hw/i2c/pm_smbus.h" @@ -32,7 +33,6 @@ #include "qapi/error.h" #include "qemu/range.h" #include "exec/address-spaces.h" -#include "hw/acpi/piix4.h" #include "hw/acpi/pcihp.h" #include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/cpu.h" diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 1d077a7cb7..56c427f772 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -34,7 +34,6 @@ #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" #include "hw/acpi/cpu.h" -#include "hw/acpi/piix4.h" #include "hw/nvram/fw_cfg.h" #include "hw/acpi/bios-linker-loader.h" #include "hw/isa/isa.h" @@ -52,7 +51,7 @@ #include "sysemu/reset.h" /* Supported chipsets: */ -#include "hw/acpi/piix4.h" +#include "hw/southbridge/piix.h" #include "hw/acpi/pcihp.h" #include "hw/i386/ich9.h" #include "hw/pci/pci_bus.h" diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6824b72124..431965d921 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -29,6 +29,7 @@ #include "hw/loader.h" #include "hw/i386/pc.h" #include "hw/i386/apic.h" +#include "hw/southbridge/piix.h" #include "hw/display/ramfb.h" #include "hw/firmware/smbios.h" #include "hw/pci/pci.h" diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index dda8bc3f90..b35b8a5f71 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -24,6 +24,7 @@ */ #include "qemu/osdep.h" +#include "qapi/error.h" #include "hw/irq.h" #include "hw/i386/pc.h" #include "hw/pci/pci.h" @@ -31,6 +32,7 @@ #include "hw/sysbus.h" #include "hw/dma/i8257.h" #include "hw/timer/i8254.h" +#include "hw/timer/mc146818rtc.h" #include "migration/vmstate.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" @@ -42,6 +44,7 @@ typedef struct PIIX4State { qemu_irq cpu_intr; qemu_irq *isa; + RTCState rtc; /* Reset Control Register */ MemoryRegion rcr_mem; uint8_t rcr; @@ -145,6 +148,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) PIIX4State *s = PIIX4_PCI_DEVICE(dev); ISABus *isa_bus; qemu_irq *i8259_out_irq; + Error *err = NULL; isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), pci_address_space_io(dev), errp); @@ -175,9 +179,26 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* DMA */ i8257_dma_init(isa_bus, 0); + /* RTC */ + qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus)); + qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); + object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ); + piix4_dev = dev; } +static void piix4_init(Object *obj) +{ + PIIX4State *s = PIIX4_PCI_DEVICE(obj); + + object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC); +} + static void piix4_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -202,6 +223,7 @@ static const TypeInfo piix4_info = { .name = TYPE_PIIX4_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIX4State), + .instance_init = piix4_init, .class_init = piix4_class_init, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 16d7a0e785..528c34a1c3 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -26,7 +26,7 @@ #include "qemu/units.h" #include "qemu-common.h" #include "cpu.h" -#include "hw/i386/pc.h" +#include "hw/southbridge/piix.h" #include "hw/isa/superio.h" #include "hw/char/serial.h" #include "net/net.h" @@ -44,7 +44,6 @@ #include "hw/irq.h" #include "hw/loader.h" #include "elf.h" -#include "hw/timer/mc146818rtc.h" #include "exec/address-spaces.h" #include "hw/sysbus.h" /* SysBusDevice */ #include "qemu/host-utils.h" @@ -1425,7 +1424,6 @@ void mips_malta_init(MachineState *machine) pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci"); smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_get_irq(NULL, 9), NULL, 0, NULL); - mc146818_rtc_init(isa_bus, 2000, NULL); /* generate SPD EEPROM data */ generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h deleted file mode 100644 index 028bb53e3d..0000000000 --- a/include/hw/acpi/piix4.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef HW_ACPI_PIIX4_H -#define HW_ACPI_PIIX4_H - -#define TYPE_PIIX4_PM "PIIX4_PM" - -#endif diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 374f3e8835..cf922fd162 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -248,12 +248,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0); #define PORT92_A20_LINE "a20" -/* acpi_piix.c */ - -I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq, qemu_irq smi_irq, - int smm_enabled, DeviceState **piix4_pm); - /* hpet.c */ extern int no_hpet; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h new file mode 100644 index 0000000000..b8ce26fec4 --- /dev/null +++ b/include/hw/southbridge/piix.h @@ -0,0 +1,20 @@ +/* + * QEMU PIIX South Bridge Emulation + * + * Copyright (c) 2006 Fabrice Bellard + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_SOUTHBRIDGE_PIIX_H +#define HW_SOUTHBRIDGE_PIIX_H + +#define TYPE_PIIX4_PM "PIIX4_PM" + +I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, + qemu_irq sci_irq, qemu_irq smi_irq, + int smm_enabled, DeviceState **piix4_pm); + +#endif