From patchwork Thu Oct 10 13:15:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1174551 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46psJK1SrSz9sPJ for ; Fri, 11 Oct 2019 00:24:49 +1100 (AEDT) Received: from localhost ([::1]:39454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIYQw-0001D1-MQ for incoming@patchwork.ozlabs.org; Thu, 10 Oct 2019 09:24:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40452) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIYIm-000847-QP for qemu-devel@nongnu.org; Thu, 10 Oct 2019 09:16:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIYIk-00020n-4A for qemu-devel@nongnu.org; Thu, 10 Oct 2019 09:16:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:31514) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iIYIf-0001zD-Qq; Thu, 10 Oct 2019 09:16:13 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EAC193065603; Thu, 10 Oct 2019 13:16:12 +0000 (UTC) Received: from x1w.redhat.com (unknown [10.40.205.241]) by smtp.corp.redhat.com (Postfix) with ESMTPS id BE5BD600C4; Thu, 10 Oct 2019 13:15:52 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Eduardo Habkost , qemu-devel@nongnu.org Subject: [PATCH v3 2/8] hw/isa/piix4: Convert reset handler to DeviceReset Date: Thu, 10 Oct 2019 15:15:21 +0200 Message-Id: <20191010131527.32513-3-philmd@redhat.com> In-Reply-To: <20191010131527.32513-1-philmd@redhat.com> References: <20191010131527.32513-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.47]); Thu, 10 Oct 2019 13:16:13 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Aleksandar Markovic , qemu-block@nongnu.org, "Michael S. Tsirkin" , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?b?RGF1ZMOp?= , Li Qiang , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Igor Mammedov , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , John Snow Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The PIIX4/ISA is a PCI device within the PIIX4 chipset, it will be reset when the PCI bus it stands on is reset. Convert its reset handler into a proper Device reset method. Reviewed-by: Li Qiang Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 3294056cd5..890d999abf 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -28,7 +28,6 @@ #include "hw/isa/isa.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "sysemu/reset.h" PCIDevice *piix4_dev; @@ -40,9 +39,9 @@ typedef struct PIIX4State { #define PIIX4_PCI_DEVICE(obj) \ OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE) -static void piix4_reset(void *opaque) +static void piix4_isa_reset(DeviceState *dev) { - PIIX4State *d = opaque; + PIIX4State *d = PIIX4_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; // master, memory and I/O @@ -97,7 +96,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } piix4_dev = &d->dev; - qemu_register_reset(piix4_reset, d); } int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn) @@ -118,6 +116,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; k->class_id = PCI_CLASS_BRIDGE_ISA; + dc->reset = piix4_isa_reset; dc->desc = "ISA bridge"; dc->vmsd = &vmstate_piix4; /*