Message ID | 20191010065950.23169-3-ganeshgr@linux.ibm.com |
---|---|
State | New |
Headers | show |
Series | target-ppc/spapr: Add FWNMI support in QEMU for PowerKVM guests | expand |
On Thu, Oct 10, 2019 at 12:29:45PM +0530, Ganesh Goudar wrote: > From: Aravinda Prasad <arawinda.p@gmail.com> > > Introduce the KVM capability KVM_CAP_PPC_FWNMI so that > the KVM causes guest exit with NMI as exit reason > when it encounters a machine check exception on the > address belonging to a guest. Without this capability > enabled, KVM redirects machine check exceptions to > guest's 0x200 vector. > > This patch also introduces fwnmi-mce capability to > deal with the case when a guest with the > KVM_CAP_PPC_FWNMI capability enabled is attempted > to migrate to a host that does not support this > capability. I think the commit message needs some updating. This doesn't really introduce the KVM cap. It introduces the spapr capability, and validates it against the kernel's exising capability. > > [eliminate cap_ppc_fwnmi] > Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> > Signed-off-by: Aravinda Prasad <arawinda.p@gmail.com> > --- > hw/ppc/spapr.c | 1 + > hw/ppc/spapr_caps.c | 29 +++++++++++++++++++++++++++++ > include/hw/ppc/spapr.h | 4 +++- > target/ppc/kvm.c | 8 ++++++++ > target/ppc/kvm_ppc.h | 6 ++++++ > 5 files changed, 47 insertions(+), 1 deletion(-) > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index 514a17ae74..7e6a15c9b4 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -4441,6 +4441,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) > smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; > smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; > smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; > + smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF; > spapr_caps_add_properties(smc, &error_abort); > smc->irq = &spapr_irq_dual; > smc->dr_phb_enabled = true; To have migration work correctly, you also need to add &vmstate_spapr_cap_fwnmi_mce to the list in vmstate_spapr. (Yes, that makes three places you have to put things to get migration right, which is really easy to mess up - I've done it more than once myself - unfortunately, I haven't come up with a better way yet). > diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c > index 481dfd2a27..778bf32181 100644 > --- a/hw/ppc/spapr_caps.c > +++ b/hw/ppc/spapr_caps.c > @@ -496,6 +496,25 @@ static void cap_ccf_assist_apply(SpaprMachineState *spapr, uint8_t val, > } > } > > +static void cap_fwnmi_mce_apply(SpaprMachineState *spapr, uint8_t val, > + Error **errp) > +{ > + if (!val) { > + return; /* Disabled by default */ > + } > + > + if (tcg_enabled()) { > + /* > + * TCG support may not be correct in some conditions (e.g., in case > + * of software injected faults like duplicate SLBs). > + */ > + warn_report("Firmware Assisted Non-Maskable Interrupts not supported in TCG"); > + } else if (kvm_enabled() && kvmppc_set_fwnmi()) { When checking integer error code return values (like kvmppc_set_fwnmi()) please include an explicit != 0, to make it clearer that's what's happening, rather than a function returning a bool. > + error_setg(errp, > +"Firmware Assisted Non-Maskable Interrupts not supported by KVM, try cap-fwnmi-mce=off"); > + } > +} > + > SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = { > [SPAPR_CAP_HTM] = { > .name = "htm", > @@ -595,6 +614,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = { > .type = "bool", > .apply = cap_ccf_assist_apply, > }, > + [SPAPR_CAP_FWNMI_MCE] = { > + .name = "fwnmi-mce", > + .description = "Handle fwnmi machine check exceptions", > + .index = SPAPR_CAP_FWNMI_MCE, > + .get = spapr_cap_get_bool, > + .set = spapr_cap_set_bool, > + .type = "bool", > + .apply = cap_fwnmi_mce_apply, > + }, > }; > > static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr, > @@ -734,6 +762,7 @@ SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXPAGESIZE); > SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV); > SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER); > SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); > +SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI_MCE); > > void spapr_caps_init(SpaprMachineState *spapr) > { > diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h > index cbd1a4c9f3..dcd2e7d0cc 100644 > --- a/include/hw/ppc/spapr.h > +++ b/include/hw/ppc/spapr.h > @@ -79,8 +79,10 @@ typedef enum { > #define SPAPR_CAP_LARGE_DECREMENTER 0x08 > /* Count Cache Flush Assist HW Instruction */ > #define SPAPR_CAP_CCF_ASSIST 0x09 > +/* FWNMI machine check handling */ > +#define SPAPR_CAP_FWNMI_MCE 0x0A > /* Num Caps */ > -#define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) > +#define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI_MCE + 1) > > /* > * Capability Values > diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c > index 820724cc7d..d56f11a883 100644 > --- a/target/ppc/kvm.c > +++ b/target/ppc/kvm.c > @@ -2060,6 +2060,14 @@ void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) > } > } > > +int kvmppc_set_fwnmi(void) > +{ > + PowerPCCPU *cpu = POWERPC_CPU(first_cpu); > + CPUState *cs = CPU(cpu); > + > + return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); > +} > + > int kvmppc_smt_threads(void) > { > return cap_ppc_smt ? cap_ppc_smt : 1; > diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h > index 98bd7d5da6..5727a5025f 100644 > --- a/target/ppc/kvm_ppc.h > +++ b/target/ppc/kvm_ppc.h > @@ -27,6 +27,7 @@ void kvmppc_enable_h_page_init(void); > void kvmppc_set_papr(PowerPCCPU *cpu); > int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr); > void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy); > +int kvmppc_set_fwnmi(void); > int kvmppc_smt_threads(void); > void kvmppc_hint_smt_possible(Error **errp); > int kvmppc_set_smt_threads(int smt); > @@ -159,6 +160,11 @@ static inline void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) > { > } > > +static inline int kvmppc_set_fwnmi(void) > +{ > + return -1; > +} > + > static inline int kvmppc_smt_threads(void) > { > return 1;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 514a17ae74..7e6a15c9b4 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4441,6 +4441,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; + smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF; spapr_caps_add_properties(smc, &error_abort); smc->irq = &spapr_irq_dual; smc->dr_phb_enabled = true; diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 481dfd2a27..778bf32181 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -496,6 +496,25 @@ static void cap_ccf_assist_apply(SpaprMachineState *spapr, uint8_t val, } } +static void cap_fwnmi_mce_apply(SpaprMachineState *spapr, uint8_t val, + Error **errp) +{ + if (!val) { + return; /* Disabled by default */ + } + + if (tcg_enabled()) { + /* + * TCG support may not be correct in some conditions (e.g., in case + * of software injected faults like duplicate SLBs). + */ + warn_report("Firmware Assisted Non-Maskable Interrupts not supported in TCG"); + } else if (kvm_enabled() && kvmppc_set_fwnmi()) { + error_setg(errp, +"Firmware Assisted Non-Maskable Interrupts not supported by KVM, try cap-fwnmi-mce=off"); + } +} + SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = { [SPAPR_CAP_HTM] = { .name = "htm", @@ -595,6 +614,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = { .type = "bool", .apply = cap_ccf_assist_apply, }, + [SPAPR_CAP_FWNMI_MCE] = { + .name = "fwnmi-mce", + .description = "Handle fwnmi machine check exceptions", + .index = SPAPR_CAP_FWNMI_MCE, + .get = spapr_cap_get_bool, + .set = spapr_cap_set_bool, + .type = "bool", + .apply = cap_fwnmi_mce_apply, + }, }; static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr, @@ -734,6 +762,7 @@ SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXPAGESIZE); SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV); SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER); SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); +SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI_MCE); void spapr_caps_init(SpaprMachineState *spapr) { diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index cbd1a4c9f3..dcd2e7d0cc 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -79,8 +79,10 @@ typedef enum { #define SPAPR_CAP_LARGE_DECREMENTER 0x08 /* Count Cache Flush Assist HW Instruction */ #define SPAPR_CAP_CCF_ASSIST 0x09 +/* FWNMI machine check handling */ +#define SPAPR_CAP_FWNMI_MCE 0x0A /* Num Caps */ -#define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) +#define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI_MCE + 1) /* * Capability Values diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 820724cc7d..d56f11a883 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2060,6 +2060,14 @@ void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) } } +int kvmppc_set_fwnmi(void) +{ + PowerPCCPU *cpu = POWERPC_CPU(first_cpu); + CPUState *cs = CPU(cpu); + + return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); +} + int kvmppc_smt_threads(void) { return cap_ppc_smt ? cap_ppc_smt : 1; diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 98bd7d5da6..5727a5025f 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -27,6 +27,7 @@ void kvmppc_enable_h_page_init(void); void kvmppc_set_papr(PowerPCCPU *cpu); int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr); void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy); +int kvmppc_set_fwnmi(void); int kvmppc_smt_threads(void); void kvmppc_hint_smt_possible(Error **errp); int kvmppc_set_smt_threads(int smt); @@ -159,6 +160,11 @@ static inline void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) { } +static inline int kvmppc_set_fwnmi(void) +{ + return -1; +} + static inline int kvmppc_smt_threads(void) { return 1;