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intel_iommu: TM field should not be in reserved bits

Message ID 20190926054922.21110-1-qi1.zhang@intel.com
State New
Headers show
Series intel_iommu: TM field should not be in reserved bits | expand

Commit Message

Zhang, Qi1 Sept. 26, 2019, 5:49 a.m. UTC 
From: "Zhang, Qi" <qi1.zhang@intel.com>

When dt is supported, TM field should not be Reserved(0).

Refer to VT-d Spec 9.8

Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
---
 hw/i386/intel_iommu.c | 7 +++++++
 1 file changed, 7 insertions(+)
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Patch

diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index f1de8fdb75..2696ceeb9d 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3567,6 +3567,13 @@  static void vtd_init(IntelIOMMUState *s)
 
     if (x86_iommu->dt_supported) {
         s->ecap |= VTD_ECAP_DT;
+        vtd_paging_entry_rsvd_field[1] &= ~(1ULL << 62);
+        vtd_paging_entry_rsvd_field[2] &= ~(1ULL << 62);
+        vtd_paging_entry_rsvd_field[3] &= ~(1ULL << 62);
+
+        vtd_paging_entry_rsvd_field[5] &= ~(1ULL << 62);
+        vtd_paging_entry_rsvd_field[6] &= ~(1ULL << 62);
+        vtd_paging_entry_rsvd_field[7] &= ~(1ULL << 62);
     }
 
     if (x86_iommu->pt_supported) {