From patchwork Wed Sep 18 14:56:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1164038 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46YPm65qddz9sNf for ; Thu, 19 Sep 2019 01:58:46 +1000 (AEST) Received: from localhost ([::1]:60350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcLs-0002bP-4s for incoming@patchwork.ozlabs.org; Wed, 18 Sep 2019 11:58:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49764) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAbsh-0007VX-JP for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAbsg-000712-8Z for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:35 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:41433) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iAbsg-00070f-1y for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:34 -0400 Received: by mail-pl1-f194.google.com with SMTP id t10so110100plr.8 for ; Wed, 18 Sep 2019 08:28:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=D9npBpsUm7+Rm801Ap/KYbHj9DAYTiffDSrfZbUWHdg=; b=a8DFyDIkuFXGkTQEhC6yZui3Cj2lLUSYAtetZ3dljp9vRnoPySYVYG41FzNb6+3mS3 wcE6ckWPtjWUYTgHghu8ALALCVciLcCDLaYO1buycs9XAXXqHHwULlKEjAxBuQT8n50V uRWmQ2uHpmIWRcwKpWBOn8IwvTk6nIZMOaj0vX6cOEbotog+Hf8pwA3Pd0qnbbHuRWBP JseQ6PyGe4m7VySBP3AlzxkWggzZQHsPwvyLjRFbTle1wv4JR4W/xokt/HTqXYnFkEJq qkGUYvuIm+evSCfFr5aIbGnpkRpIJNOBn5WmBr2wcoYTryTh+nmT4vrpN3Mn28Xjs2uB xdIQ== X-Gm-Message-State: APjAAAVazR+JagM0LfF1uFxxeXvE+exSQSbWo+XtXbRobsb4IeELleFD Q7oVl8/0xk3Ogh104B9+aOCHTw== X-Google-Smtp-Source: APXvYqwIfUQEUkht3MU59SaBctpDy3grrAP0U9Adq56baFslqV28pQJjs21XCgaLzBx5OIO+e6FaWw== X-Received: by 2002:a17:902:aa93:: with SMTP id d19mr4662415plr.249.1568820512886; Wed, 18 Sep 2019 08:28:32 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id z19sm5605735pgv.35.2019.09.18.08.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2019 08:28:32 -0700 (PDT) Date: Wed, 18 Sep 2019 07:56:26 -0700 Message-Id: <20190918145640.17349-35-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918145640.17349-1-palmer@sifive.com> References: <20190918145640.17349-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.194 Subject: [Qemu-devel] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 23 +++++++++++++++++++++++ include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d80b203cc1..7eefe9796a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -79,6 +79,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, char ethclk_names[] = "pclk\0hclk\0tx_clk"; uint32_t plic_phandle, ethclk_phandle, phandle = 1; uint32_t uartclk_phandle; + uint32_t hfclk_phandle, rtcclk_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -97,6 +98,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + hfclk_phandle = phandle++; + nodename = g_strdup_printf("/hfclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_HFCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + + rtcclk_phandle = phandle++; + nodename = g_strdup_printf("/rtcclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_RTCCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + nodename = g_strdup_printf("/memory@%lx", (long)memmap[SIFIVE_U_DRAM].base); qemu_fdt_add_subnode(fdt, nodename); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 6b2b5b68e2..24418145aa 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -69,6 +69,8 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, + SIFIVE_U_HFCLK_FREQ = 33333333, + SIFIVE_U_RTCCLK_FREQ = 1000000, SIFIVE_U_GEM_CLOCK_FREQ = 125000000 };