| Message ID | 20190910071019.16689-2-bala24@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | add Homer/OCC common area emulation for PowerNV | expand |
On 10/09/2019 09:10, Balamuruhan S wrote: > During PowerNV boot skiboot populates the device tree by > retrieving base address of homer/occ common area from > PBA BARs and prd ipoll mask by accessing xscom read/write > accesses. > > Signed-off-by: Balamuruhan S <bala24@linux.ibm.com> LGTM, Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > hw/ppc/pnv_xscom.c | 34 ++++++++++++++++++++++++++++++---- > include/hw/ppc/pnv.h | 18 ++++++++++++++++++ > 2 files changed, 48 insertions(+), 4 deletions(-) > > diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c > index 67aab98fef..f01d788a65 100644 > --- a/hw/ppc/pnv_xscom.c > +++ b/hw/ppc/pnv_xscom.c > @@ -36,6 +36,16 @@ > #define PRD_P9_IPOLL_REG_MASK 0x000F0033 > #define PRD_P9_IPOLL_REG_STATUS 0x000F0034 > > +/* PBA BARs */ > +#define P8_PBA_BAR0 0x2013f00 > +#define P8_PBA_BAR2 0x2013f02 > +#define P8_PBA_BARMASK0 0x2013f04 > +#define P8_PBA_BARMASK2 0x2013f06 > +#define P9_PBA_BAR0 0x5012b00 > +#define P9_PBA_BAR2 0x5012b02 > +#define P9_PBA_BARMASK0 0x5012b04 > +#define P9_PBA_BARMASK2 0x5012b06 > + > static void xscom_complete(CPUState *cs, uint64_t hmer_bits) > { > /* > @@ -74,6 +84,26 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) > case 0x18002: /* ECID2 */ > return 0; > > + case P9_PBA_BAR0: > + return PNV9_HOMER_BASE(chip); > + case P8_PBA_BAR0: > + return PNV_HOMER_BASE(chip); > + > + case P9_PBA_BARMASK0: /* P9 homer region size */ > + return PNV9_HOMER_SIZE; > + case P8_PBA_BARMASK0: /* P8 homer region size */ > + return PNV_HOMER_SIZE; > + > + case P9_PBA_BAR2: /* P9 occ common area */ > + return PNV9_OCC_COMMON_AREA(chip); > + case P8_PBA_BAR2: /* P8 occ common area */ > + return PNV_OCC_COMMON_AREA(chip); > + > + case P9_PBA_BARMASK2: /* P9 occ common area size */ > + return PNV9_OCC_COMMON_AREA_SIZE; > + case P8_PBA_BARMASK2: /* P8 occ common area size */ > + return PNV_OCC_COMMON_AREA_SIZE; > + > case 0x1010c00: /* PIBAM FIR */ > case 0x1010c03: /* PIBAM FIR MASK */ > > @@ -93,13 +123,9 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) > case 0x2020009: /* ADU stuff, error register */ > case 0x202000f: /* ADU stuff, receive status register*/ > return 0; > - case 0x2013f00: /* PBA stuff */ > case 0x2013f01: /* PBA stuff */ > - case 0x2013f02: /* PBA stuff */ > case 0x2013f03: /* PBA stuff */ > - case 0x2013f04: /* PBA stuff */ > case 0x2013f05: /* PBA stuff */ > - case 0x2013f06: /* PBA stuff */ > case 0x2013f07: /* PBA stuff */ > return 0; > case 0x2013028: /* CAPP stuff */ > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index fb123edc4e..63a4b7b6a7 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -198,6 +198,16 @@ void pnv_bmc_powerdown(IPMIBmc *bmc); > #define PNV_XSCOM_BASE(chip) \ > (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) > > +#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000700000ull > +#define PNV_OCC_COMMON_AREA(chip) \ > + (0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ > + PNV_OCC_COMMON_AREA_SIZE)) > + > +#define PNV_HOMER_SIZE 0x0000000000300000ull > +#define PNV_HOMER_BASE(chip) \ > + (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) > + > + > /* > * XSCOM 0x20109CA defines the ICP BAR: > * > @@ -256,4 +266,12 @@ void pnv_bmc_powerdown(IPMIBmc *bmc); > #define PNV9_XSCOM_SIZE 0x0000000400000000ull > #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) > > +#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000700000ull > +#define PNV9_OCC_COMMON_AREA(chip) \ > + (0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ > + PNV9_OCC_COMMON_AREA_SIZE)) > + > +#define PNV9_HOMER_SIZE 0x0000000000300000ull > +#define PNV9_HOMER_BASE(chip) \ > + (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) > #endif /* PPC_PNV_H */ >
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 67aab98fef..f01d788a65 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -36,6 +36,16 @@ #define PRD_P9_IPOLL_REG_MASK 0x000F0033 #define PRD_P9_IPOLL_REG_STATUS 0x000F0034 +/* PBA BARs */ +#define P8_PBA_BAR0 0x2013f00 +#define P8_PBA_BAR2 0x2013f02 +#define P8_PBA_BARMASK0 0x2013f04 +#define P8_PBA_BARMASK2 0x2013f06 +#define P9_PBA_BAR0 0x5012b00 +#define P9_PBA_BAR2 0x5012b02 +#define P9_PBA_BARMASK0 0x5012b04 +#define P9_PBA_BARMASK2 0x5012b06 + static void xscom_complete(CPUState *cs, uint64_t hmer_bits) { /* @@ -74,6 +84,26 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) case 0x18002: /* ECID2 */ return 0; + case P9_PBA_BAR0: + return PNV9_HOMER_BASE(chip); + case P8_PBA_BAR0: + return PNV_HOMER_BASE(chip); + + case P9_PBA_BARMASK0: /* P9 homer region size */ + return PNV9_HOMER_SIZE; + case P8_PBA_BARMASK0: /* P8 homer region size */ + return PNV_HOMER_SIZE; + + case P9_PBA_BAR2: /* P9 occ common area */ + return PNV9_OCC_COMMON_AREA(chip); + case P8_PBA_BAR2: /* P8 occ common area */ + return PNV_OCC_COMMON_AREA(chip); + + case P9_PBA_BARMASK2: /* P9 occ common area size */ + return PNV9_OCC_COMMON_AREA_SIZE; + case P8_PBA_BARMASK2: /* P8 occ common area size */ + return PNV_OCC_COMMON_AREA_SIZE; + case 0x1010c00: /* PIBAM FIR */ case 0x1010c03: /* PIBAM FIR MASK */ @@ -93,13 +123,9 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) case 0x2020009: /* ADU stuff, error register */ case 0x202000f: /* ADU stuff, receive status register*/ return 0; - case 0x2013f00: /* PBA stuff */ case 0x2013f01: /* PBA stuff */ - case 0x2013f02: /* PBA stuff */ case 0x2013f03: /* PBA stuff */ - case 0x2013f04: /* PBA stuff */ case 0x2013f05: /* PBA stuff */ - case 0x2013f06: /* PBA stuff */ case 0x2013f07: /* PBA stuff */ return 0; case 0x2013028: /* CAPP stuff */ diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index fb123edc4e..63a4b7b6a7 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -198,6 +198,16 @@ void pnv_bmc_powerdown(IPMIBmc *bmc); #define PNV_XSCOM_BASE(chip) \ (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) +#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000700000ull +#define PNV_OCC_COMMON_AREA(chip) \ + (0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ + PNV_OCC_COMMON_AREA_SIZE)) + +#define PNV_HOMER_SIZE 0x0000000000300000ull +#define PNV_HOMER_BASE(chip) \ + (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) + + /* * XSCOM 0x20109CA defines the ICP BAR: * @@ -256,4 +266,12 @@ void pnv_bmc_powerdown(IPMIBmc *bmc); #define PNV9_XSCOM_SIZE 0x0000000400000000ull #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) +#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000700000ull +#define PNV9_OCC_COMMON_AREA(chip) \ + (0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ + PNV9_OCC_COMMON_AREA_SIZE)) + +#define PNV9_HOMER_SIZE 0x0000000000300000ull +#define PNV9_HOMER_BASE(chip) \ + (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) #endif /* PPC_PNV_H */
During PowerNV boot skiboot populates the device tree by retrieving base address of homer/occ common area from PBA BARs and prd ipoll mask by accessing xscom read/write accesses. Signed-off-by: Balamuruhan S <bala24@linux.ibm.com> --- hw/ppc/pnv_xscom.c | 34 ++++++++++++++++++++++++++++++---- include/hw/ppc/pnv.h | 18 ++++++++++++++++++ 2 files changed, 48 insertions(+), 4 deletions(-)