From patchwork Tue Sep 3 11:47:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1156948 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46N4zZ5553z9s7T for ; Tue, 3 Sep 2019 21:51:22 +1000 (AEST) Received: from localhost ([::1]:44440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i57LE-0000Zl-F9 for incoming@patchwork.ozlabs.org; Tue, 03 Sep 2019 07:51:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55175) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i57Ht-0005A5-HX for qemu-devel@nongnu.org; Tue, 03 Sep 2019 07:47:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i57Hs-00061l-Fg for qemu-devel@nongnu.org; Tue, 03 Sep 2019 07:47:53 -0400 Received: from mx1.redhat.com ([209.132.183.28]:57510) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i57Hq-0005zk-8d; Tue, 03 Sep 2019 07:47:50 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7F43A30832EA; Tue, 3 Sep 2019 11:47:49 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-102.brq.redhat.com [10.40.204.102]) by smtp.corp.redhat.com (Postfix) with ESMTPS id EAFAF67600; Tue, 3 Sep 2019 11:47:46 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 13:47:28 +0200 Message-Id: <20190903114729.3400-5-philmd@redhat.com> In-Reply-To: <20190903114729.3400-1-philmd@redhat.com> References: <20190903114729.3400-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.44]); Tue, 03 Sep 2019 11:47:49 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 4/5] target/arm: Restrict R and M profiles to TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" KVM is only able to run on CPUs based on the A-Profile architecture. The following CPUs are disabled: * M-Profile Architecture - Cortex-M3 - Cortex-M4 - Cortex-M33 * R-Profile Architecture - Cortex-R5 - Cortex-R5F Signed-off-by: Philippe Mathieu-Daudé --- v2: list cpus --- target/arm/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f69780147c..299c59fde4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -462,7 +462,9 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return ret; } -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if (!defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)) \ + && defined(CONFIG_TCG) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); @@ -1902,8 +1904,6 @@ static void cortex_m0_initfn(Object *obj) cpu->midr = 0x410cc200; } -#endif - static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -2057,6 +2057,8 @@ static void cortex_r5f_initfn(Object *obj) cpu->isar.mvfr1 = 0x00000011; } +#endif + static const ARMCPRegInfo cortexa8_cp_reginfo[] = { { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, @@ -2545,7 +2547,6 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, { .name = "cortex-m0", .initfn = cortex_m0_initfn, .class_init = arm_v7m_class_init }, -#endif { .name = "cortex-m3", .initfn = cortex_m3_initfn, .class_init = arm_v7m_class_init }, { .name = "cortex-m4", .initfn = cortex_m4_initfn, @@ -2554,6 +2555,7 @@ static const ARMCPUInfo arm_cpus[] = { .class_init = arm_v7m_class_init }, { .name = "cortex-r5", .initfn = cortex_r5_initfn }, { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, +#endif { .name = "cortex-a7", .initfn = cortex_a7_initfn }, { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn },