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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 4sm8705796wro.78.2019.08.16.06.17.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2019 06:17:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 16 Aug 2019 14:17:10 +0100 Message-Id: <20190816131719.28244-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190816131719.28244-1-peter.maydell@linaro.org> References: <20190816131719.28244-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f Subject: [Qemu-devel] [PULL 20/29] target/arm/cpu: Use div-round-up to determine predicate register array size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Unless we're guaranteed to always increase ARM_MAX_VQ by a multiple of four, then we should use DIV_ROUND_UP to ensure we get an appropriate array size. Signed-off-by: Andrew Jones Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d12c7460859..ab5d58a9d41 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -195,7 +195,7 @@ typedef struct ARMVectorReg { #ifdef TARGET_AARCH64 /* In AArch32 mode, predicate registers do not exist at all. */ typedef struct ARMPredicateReg { - uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); + uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); } ARMPredicateReg; /* In AArch32 mode, PAC keys do not exist at all. */