[for-4.2,22/24] target/arm: Update regime_is_user for EL2&0

Message ID	20190719210326.15466-23-richard.henderson@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Fri, 19 Jul 2019 14:03:24 -0700 Message-Id: <20190719210326.15466-23-richard.henderson@linaro.org> In-Reply-To: <20190719210326.15466-1-richard.henderson@linaro.org> References: <20190719210326.15466-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH for-4.2 22/24] target/arm: Update regime_is_user for EL2&0 Precedence: list Cc: peter.maydell@linaro.org, beata.michalska@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/arm: Implement ARMv8.1-VHE \| expand [for-4.2,00/24] target/arm: Implement ARMv8.1-VHE [for-4.2,01/24] cputlb: Add tlb_set_asid_for_mmuidx [for-4.2,02/24] cputlb: Add tlb_flush_asid_by_mmuidx and friends [for-4.2,03/24] target/arm: Install ASIDs for long-form from EL1 [for-4.2,04/24] target/arm: Install ASIDs for short-form from EL1 [for-4.2,05/24] target/arm: Install ASIDs for EL2 [for-4.2,06/24] target/arm: Define isar_feature_aa64_vh [for-4.2,07/24] target/arm: Enable HCR_E2H for VHE [for-4.2,08/24] target/arm: Add CONTEXTIDR_EL2 [for-4.2,09/24] target/arm: Add TTBR1_EL2 [for-4.2,10/24] target/arm: Update CNTVCT_EL0 for VHE [for-4.2,11/24] target/arm: Add the hypervisor virtual counter [for-4.2,12/24] target/arm: Add VHE system register redirection and aliasing [for-4.2,13/24] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask [for-4.2,14/24] target/arm: Simplify tlb_force_broadcast alternatives [for-4.2,15/24] target/arm: Reorganize ARMMMUIdx [for-4.2,16/24] target/arm: Add regime_has_2_ranges [for-4.2,17/24] target/arm: Update arm_mmu_idx for VHE [for-4.2,18/24] target/arm: Update arm_sctlr for VHE [for-4.2,19/24] target/arm: Install asids for E2&0 translation regime [for-4.2,20/24] target/arm: Flush tlbs for E2&0 translation regime [for-4.2,21/24] target/arm: Update arm_phys_excp_target_el for TGE [for-4.2,22/24] target/arm: Update regime_is_user for EL2&0 [for-4.2,23/24] target/arm: Update {fp, sve}_exception_el for VHE [for-4.2,24/24] target/arm: Enable ARMv8.1-VHE in -cpu max

Message ID

20190719210326.15466-23-richard.henderson@linaro.org

State

New

Headers

From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 19 Jul 2019 14:03:24 -0700
Message-Id: <20190719210326.15466-23-richard.henderson@linaro.org>
In-Reply-To: <20190719210326.15466-1-richard.henderson@linaro.org>
References: <20190719210326.15466-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH for-4.2 22/24] target/arm: Update
	regime_is_user for EL2&0
Precedence: list
Cc: peter.maydell@linaro.org, beata.michalska@linaro.org
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

target/arm: Implement ARMv8.1-VHE | expand

Commit Message

Richard Henderson July 19, 2019, 9:03 p.m. UTC

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index f06e7bcd77..ae3ec9ea67 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8885,6 +8885,7 @@  static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
 {
     switch (mmu_idx) {
     case ARMMMUIdx_SE0:
+    case ARMMMUIdx_EL20_0:
     case ARMMMUIdx_Stage1_E0:
     case ARMMMUIdx_MUser:
     case ARMMMUIdx_MSUser:

[for-4.2,22/24] target/arm: Update regime_is_user for EL2&0

Commit Message

Patch