From patchwork Tue Jul 2 06:08:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 1126022 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="REVhtQNa"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45dFRK3Wqzz9s4Y for ; Tue, 2 Jul 2019 16:57:17 +1000 (AEST) Received: from localhost ([::1]:49676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hiCj5-0001aC-Hr for incoming@patchwork.ozlabs.org; Tue, 02 Jul 2019 02:57:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59257) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hiC07-0006Cw-4a for qemu-devel@nongnu.org; Tue, 02 Jul 2019 02:10:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hiC06-0003g4-0X for qemu-devel@nongnu.org; Tue, 02 Jul 2019 02:10:47 -0400 Received: from bilbo.ozlabs.org ([203.11.71.1]:54135 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hiC05-0003Rj-L7; Tue, 02 Jul 2019 02:10:45 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 45dDMp3qRcz9sRD; Tue, 2 Jul 2019 16:09:07 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1562047750; bh=O0BwGIFtuIEU4BNo5FlE86BSBTHsHhMIiptJ5Ab7+DE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=REVhtQNa5tJEbL9nHBikuvwitgdSyVAJ4bqoK7l65/0YZwbDrTA5OdAlk5snrGWwt Iqo2tvxaRTosN+8XotqRk7aQsEP5IF7Ns7UvXBgkiBw8oiecTYbrqVAOjh/o6cHcmh 9koFDj6QTZwh6LadNxXTI6jCbI9vuxbgqd0zkw24= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 2 Jul 2019 16:08:56 +1000 Message-Id: <20190702060857.3926-49-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190702060857.3926-1-david@gibson.dropbear.id.au> References: <20190702060857.3926-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 48/49] ppc/xive: Fix TM_PULL_POOL_CTX special operation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson , rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater When a CPU is reseted, the hypervisor (Linux or OPAL) invalidates the POOL interrupt context of a CPU with this special command. It returns the POOL CAM line value and resets the VP bit. Fixes: 4836b45510aa ("ppc/xive: activate HV support") Signed-off-by: Cédric Le Goater Message-Id: <20190630204601.30574-5-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/xive.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 534f56f86b..cf77bdb7d3 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -132,6 +132,11 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) xive_tctx_notify(tctx, ring); } +static inline uint32_t xive_tctx_word2(uint8_t *ring) +{ + return *((uint32_t *) &ring[TM_WORD2]); +} + /* * XIVE Thread Interrupt Management Area (TIMA) */ @@ -150,11 +155,12 @@ static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, unsigned size) { - uint64_t ret; + uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); + uint32_t qw2w2; - ret = tctx->regs[TM_QW2_HV_POOL + TM_WORD2] & TM_QW2W2_POOL_CAM; - tctx->regs[TM_QW2_HV_POOL + TM_WORD2] &= ~TM_QW2W2_POOL_CAM; - return ret; + qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); + memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); + return qw2w2; } static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, @@ -484,11 +490,6 @@ const MemoryRegionOps xive_tm_ops = { }, }; -static inline uint32_t xive_tctx_word2(uint8_t *ring) -{ - return *((uint32_t *) &ring[TM_WORD2]); -} - static char *xive_tctx_ring_print(uint8_t *ring) { uint32_t w2 = xive_tctx_word2(ring);