Message ID | 20190416125744.27770-8-peter.maydell@linaro.org |
---|---|
State | New |
Headers | show |
Series | target/arm: Implement M profile floating point | expand |
On 4/16/19 5:57 AM, Peter Maydell wrote: > If the floating point extension is present, then the SG instruction > must clear the CONTROL_S.SFPA bit. Implement this. > > (On a no-FPU system the bit will always be zero, so we don't need > to make the clearing of the bit conditional on ARM_FEATURE_VFP.) > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/helper.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/helper.c b/target/arm/helper.c index 27e5f98bc73..b4f1609a1c6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8809,6 +8809,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32 ", executing it\n", env->regs[15]); env->regs[14] &= ~1; + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; switch_v7m_security_state(env, true); xpsr_write(env, 0, XPSR_IT); env->regs[15] += 4;
If the floating point extension is present, then the SG instruction must clear the CONTROL_S.SFPA bit. Implement this. (On a no-FPU system the bit will always be zero, so we don't need to make the clearing of the bit conditional on ARM_FEATURE_VFP.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 1 + 1 file changed, 1 insertion(+)