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[2001:b011:7001:1cad:363a:ebbe:dac8:3f4c]) by smtp.gmail.com with ESMTPSA id 10sm19931256pft.83.2019.03.19.05.54.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Mar 2019 05:54:53 -0700 (PDT) Date: Tue, 19 Mar 2019 05:47:58 -0700 Message-Id: <20190319124803.13826-15-palmer@sifive.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190319124803.13826-1-palmer@sifive.com> References: <20190319124803.13826-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42f Subject: [Qemu-devel] [PULL 14/19] RISC-V: Convert trap debugging to trace events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Michael Clark , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Michael Clark Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- Makefile.objs | 1 + target/riscv/cpu_helper.c | 12 +++--------- target/riscv/trace-events | 2 ++ 3 files changed, 6 insertions(+), 9 deletions(-) create mode 100644 target/riscv/trace-events diff --git a/Makefile.objs b/Makefile.objs index 72debbf5c5de..cf065de5ed44 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -186,6 +186,7 @@ trace-events-subdirs += target/hppa trace-events-subdirs += target/i386 trace-events-subdirs += target/mips trace-events-subdirs += target/ppc +trace-events-subdirs += target/riscv trace-events-subdirs += target/s390x trace-events-subdirs += target/sparc trace-events-subdirs += ui diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a02f4dad8c00..6d3fbc340165 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,8 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "tcg-op.h" - -#define RISCV_DEBUG_INTERRUPT 0 +#include "trace.h" int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -493,13 +492,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) } } - if (RISCV_DEBUG_INTERRUPT) { - qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": %s %s, " - "epc 0x" TARGET_FMT_lx ": tval 0x" TARGET_FMT_lx "\n", - env->mhartid, async ? "intr" : "trap", - (async ? riscv_intr_names : riscv_excp_names)[cause], - env->pc, tval); - } + trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16 ? + (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); if (env->priv <= PRV_S && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { diff --git a/target/riscv/trace-events b/target/riscv/trace-events new file mode 100644 index 000000000000..48af0373df6e --- /dev/null +++ b/target/riscv/trace-events @@ -0,0 +1,2 @@ +# target/riscv/cpu_helper.c +riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"