From patchwork Wed Mar 13 14:36:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1056098 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="IUZ/SQMQ"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44KFTr45v6z9s4V for ; Thu, 14 Mar 2019 02:03:44 +1100 (AEDT) Received: from localhost ([127.0.0.1]:46039 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h45Py-0007vt-6W for incoming@patchwork.ozlabs.org; Wed, 13 Mar 2019 11:03:42 -0400 Received: from eggs.gnu.org ([209.51.188.92]:60852) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h4565-0000a4-Sp for qemu-devel@nongnu.org; Wed, 13 Mar 2019 10:43:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h450x-0004NO-Ai for qemu-devel@nongnu.org; Wed, 13 Mar 2019 10:37:52 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:41542) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h450x-0004Mo-2n for qemu-devel@nongnu.org; Wed, 13 Mar 2019 10:37:51 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d25so1512992pfn.8 for ; Wed, 13 Mar 2019 07:37:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding:cc:from:to; bh=5rYctR7eI37R5sMwCD3qvyZIBLK3WZhWz7ppR4vewcU=; b=IUZ/SQMQ5xtlFJ3+KC5q+L0Xdu1Q9aAA7mLGEK1GaNUxztXJXevOlPaXOwygnNx0Py v3ys/iE/tlAmfNVhy9u5mSgo08qAHLiDDNruDgpyPjd3AShXIdQLWYoYAujNM1YdyTI5 zxFctDisxvXZmjTGNjERCuWlzv0JeIcSkygTNWb4mSKLRe5Fo6vn8H2gY484nVJSsGKD M1L7gyCcENApfCKsdyt4JzXpwRbMmw63nMgG9K7MMLqdSjPtXu82XW9w/O3+ba4JSFGW Bco7oSl2c219QPWiZDPd980B+gniqt9pp/Bt6h9Ghtxoq1dDh81MBzYtim73Byzp1NkT qUIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=5rYctR7eI37R5sMwCD3qvyZIBLK3WZhWz7ppR4vewcU=; b=MSJDdkzfztlmGHdturGp6Sq2RlukgypE9pJIrdBLFBaM6D+VxNlKcZ/4BBt3Njbnk1 Cm9QXKa3Jy/qqLvVOMhQKkB/lWbwE8hQ9YL8CqL7O2pc0EmDqV4Huv3TFXU5vMUT1hVp YbQSI5Ofc4vHeIk+zYuNK+w/sAAS9lYL9cCjhlASmyT2UxI9W1k7gZABfnuzOoVw1V8g Cxk/g0EpStxdgTify1dw4DWgRk04mCA5SEO//28a59qCCkY9uUyjtF++QhHBIPorE7UV tL/bZk7OzvDf4HkAt29lAx95rgd6wt0r/vibJhdWE+3Pgk7uJXTM5i09AskWDaBSY+A9 oucA== X-Gm-Message-State: APjAAAUByMCAG24HFkDWTyeqY0g4otyMjznPBBjAKRbPDuTjwt7K/rqa utifAs/XuYyK+rrsONYR7Sz07g== X-Google-Smtp-Source: APXvYqwRoc+N8WdLYLtpWZsxutbAWY91Ka4izB/BLFQiH15qioXnh6UtXdBPzw1S+ERDjQH2tIcm8Q== X-Received: by 2002:a63:6a88:: with SMTP id f130mr40090543pgc.114.1552487870170; Wed, 13 Mar 2019 07:37:50 -0700 (PDT) Received: from localhost (60-250-203-158.HINET-IP.hinet.net. [60.250.203.158]) by smtp.gmail.com with ESMTPSA id s79sm22414888pfa.61.2019.03.13.07.37.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Mar 2019 07:37:49 -0700 (PDT) Date: Wed, 13 Mar 2019 07:36:48 -0700 Message-Id: <20190313143705.29129-13-palmer@sifive.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190313143705.29129-1-palmer@sifive.com> References: <20190313143705.29129-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42c Subject: [Qemu-devel] [PULL 12/29] target/riscv: Convert RV64F insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Peer Adelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32-64.decode | 6 +++ target/riscv/insn_trans/trans_rvf.inc.c | 60 +++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 0bee95c9840d..6319f872ac1d 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st + +# *** RV64F Standard Extension (in addition to RV32F) *** +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 0f837903491b..172dbfa919b6 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -377,3 +377,63 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) return true; } + +#ifdef TARGET_RISCV64 +static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + tcg_temp_free(t0); + return true; +} +#endif