Message ID | 20190313143705.29129-1-palmer@sifive.com |
---|---|
State | New |
Headers | show |
Series | [PULL] target/riscv: Convert to decodetree | expand |
On Wed, 13 Mar 2019 at 14:37, Palmer Dabbelt <palmer@sifive.com> wrote: > > merged tag 'pull-request-2019-03-12' > Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 > The following changes since commit 3f3bbfc7cef4490c5ed5550766a81e7d18f08db1: > > Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-03-12' into staging (2019-03-12 21:06:26 +0000) > > are available in the Git repository at: > > git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf4 > > for you to fetch changes up to 25e6ca30c668783cd72ff97080ff44e141b99f9b: > > target/riscv: Remove decode_RV32_64G() (2019-03-13 10:40:50 +0100) Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0 for any user-visible changes. -- PMM
merged tag 'pull-request-2019-03-12' Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 The following changes since commit 3f3bbfc7cef4490c5ed5550766a81e7d18f08db1: Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-03-12' into staging (2019-03-12 21:06:26 +0000) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf4 for you to fetch changes up to 25e6ca30c668783cd72ff97080ff44e141b99f9b: target/riscv: Remove decode_RV32_64G() (2019-03-13 10:40:50 +0100) ---------------------------------------------------------------- target/riscv: Convert to decodetree Bastian: this patchset converts the RISC-V decoder to decodetree in four major steps: 1) Convert 32-bit instructions to decodetree [Patch 1-15]: Many of the gen_* functions are called by the decode functions for 16-bit and 32-bit functions. If we move translation code from the gen_* functions to the generated trans_* functions of decode-tree, we get a lot of duplication. Therefore, we mostly generate calls to the old gen_* function which are properly replaced after step 2). Each of the trans_ functions are grouped into files corresponding to their ISA extension, e.g. addi which is in RV32I is translated in the file 'trans_rvi.inc.c'. 2) Convert 16-bit instructions to decodetree [Patch 16-18]: All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus, we convert the arguments in the 16 bit trans_ function to the arguments of the corresponding 32 bit instruction and call the 32 bit trans_ function. 3) Remove old manual decoding in gen_* function [Patch 19-29]: this move all manual translation code into the trans_* instructions of decode tree, such that we can remove the old decode_* functions. Palmer: This, with some additional cleanup patches, passed Alistar's testing on rv32 and rv64 as well as my testing on rv64, so I think it's good to go. I've run my standard test against this exact tag. I still don't have a Mac to try this on, sorry! If this doesn't work then I'll go try to find one tomorrow. ---------------------------------------------------------------- Bastian Koppelmann (29): target/riscv: Activate decodetree and implemnt LUI & AUIPC target/riscv: Convert RVXI branch insns to decodetree target/riscv: Convert RV32I load/store insns to decodetree target/riscv: Convert RV64I load/store insns to decodetree target/riscv: Convert RVXI arithmetic insns to decodetree target/riscv: Convert RVXI fence insns to decodetree target/riscv: Convert RVXI csr insns to decodetree target/riscv: Convert RVXM insns to decodetree target/riscv: Convert RV32A insns to decodetree target/riscv: Convert RV64A insns to decodetree target/riscv: Convert RV32F insns to decodetree target/riscv: Convert RV64F insns to decodetree target/riscv: Convert RV32D insns to decodetree target/riscv: Convert RV64D insns to decodetree target/riscv: Convert RV priv insns to decodetree target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Remove gen_jalr() target/riscv: Remove manual decoding from gen_branch() target/riscv: Remove manual decoding from gen_load() target/riscv: Remove manual decoding from gen_store() target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Remove shift and slt insn manual decoding target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Rename trans_arith to gen_arith target/riscv: Remove gen_system() target/riscv: Remove decode_RV32_64G() target/riscv/Makefile.objs | 19 + target/riscv/insn16.decode | 129 ++ target/riscv/insn32-64.decode | 72 + target/riscv/insn32.decode | 201 +++ target/riscv/insn_trans/trans_privileged.inc.c | 110 ++ target/riscv/insn_trans/trans_rva.inc.c | 218 +++ target/riscv/insn_trans/trans_rvc.inc.c | 327 +++++ target/riscv/insn_trans/trans_rvd.inc.c | 442 ++++++ target/riscv/insn_trans/trans_rvf.inc.c | 439 ++++++ target/riscv/insn_trans/trans_rvi.inc.c | 568 ++++++++ target/riscv/insn_trans/trans_rvm.inc.c | 120 ++ target/riscv/translate.c | 1847 ++++-------------------- 12 files changed, 2897 insertions(+), 1595 deletions(-) create mode 100644 target/riscv/insn16.decode create mode 100644 target/riscv/insn32-64.decode create mode 100644 target/riscv/insn32.decode create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c create mode 100644 target/riscv/insn_trans/trans_rva.inc.c create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c From Palmer Dabbelt <palmer@sifive.com> # This line is ignored. From: Palmer Dabbelt <palmer@sifive.com> Reply-To: Subject: In-Reply-To: