From patchwork Sun Mar 3 17:23:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1050907 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44C9Hk62wXz9s9T for ; Mon, 4 Mar 2019 04:33:54 +1100 (AEDT) Received: from localhost ([127.0.0.1]:42259 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0Uzo-0003lM-Sq for incoming@patchwork.ozlabs.org; Sun, 03 Mar 2019 12:33:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45473) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UqB-0004vp-B3 for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0UqA-0001qk-8m for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:55 -0500 Received: from mail.default.ilande.uk0.bigv.io ([2001:41c9:1:41f::167]:42510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0UqA-0001pq-1b; Sun, 03 Mar 2019 12:23:54 -0500 Received: from host86-184-243-112.range86-184.btcentralplus.com ([86.184.243.112] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h0Uq8-0003k5-OG; Sun, 03 Mar 2019 17:23:53 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Sun, 3 Mar 2019 17:23:43 +0000 Message-Id: <20190303172343.13406-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> References: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.184.243.112 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH 8/8] target/ppc: simplify get_cpu_vsrh() and get_cpu_vsrl() functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that the VSX registers are all in host endian order, there is no need to go via different accessors depending upon the register number. Instead the high and low parts can be accessed directly via vsrh_offset() and vsrl_offset() accordingly. Signed-off-by: Mark Cave-Ayland --- target/ppc/translate/vsx-impl.inc.c | 34 ++++------------------------------ 1 file changed, 4 insertions(+), 30 deletions(-) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 7d02a235e7..43e97756a2 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1,49 +1,23 @@ /*** VSX extension ***/ -static inline void get_vsrl(TCGv_i64 dst, int n) -{ - tcg_gen_ld_i64(dst, cpu_env, vsrl_offset(n)); -} - -static inline void set_vsrl(int n, TCGv_i64 src) -{ - tcg_gen_st_i64(src, cpu_env, vsrl_offset(n)); -} - static inline void get_cpu_vsrh(TCGv_i64 dst, int n) { - if (n < 32) { - get_fpr(dst, n); - } else { - get_avr64(dst, n - 32, true); - } + tcg_gen_ld_i64(dst, cpu_env, vsrh_offset(n)); } static inline void get_cpu_vsrl(TCGv_i64 dst, int n) { - if (n < 32) { - get_vsrl(dst, n); - } else { - get_avr64(dst, n - 32, false); - } + tcg_gen_ld_i64(dst, cpu_env, vsrl_offset(n)); } static inline void set_cpu_vsrh(int n, TCGv_i64 src) { - if (n < 32) { - set_fpr(n, src); - } else { - set_avr64(n - 32, src, true); - } + tcg_gen_st_i64(src, cpu_env, vsrh_offset(n)); } static inline void set_cpu_vsrl(int n, TCGv_i64 src) { - if (n < 32) { - set_vsrl(n, src); - } else { - set_avr64(n - 32, src, false); - } + tcg_gen_st_i64(src, cpu_env, vsrl_offset(n)); } #define VSX_LOAD_SCALAR(name, operation) \