| Message ID | 20190303172343.13406-2-mark.cave-ayland@ilande.co.uk |
|---|---|
| State | New |
| Headers | show |
| Series | target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order | expand |
On 3/3/19 9:23 AM, Mark Cave-Ayland wrote: > Instead of having multiple copies of the offset calculation logic, move it to a > single fpr_offset() function. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > --- > target/ppc/cpu.h | 7 ++++++- > target/ppc/translate.c | 4 ++-- > 2 files changed, 8 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Sun, Mar 03, 2019 at 05:23:36PM +0000, Mark Cave-Ayland wrote: > Instead of having multiple copies of the offset calculation logic, move it to a > single fpr_offset() function. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Applied to ppc-for-4.0, thanks. > --- > target/ppc/cpu.h | 7 ++++++- > target/ppc/translate.c | 4 ++-- > 2 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 26604ddf98..4bb4e42670 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -2563,9 +2563,14 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx) > } > > /* Accessors for FP, VMX and VSX registers */ > +static inline int fpr_offset(int i) > +{ > + return offsetof(CPUPPCState, vsr[i].u64[0]); > +} > + > static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) > { > - return &env->vsr[i].u64[0]; > + return (uint64_t *)((uintptr_t)env + fpr_offset(i)); > } > > static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 819221f246..3b1992faf1 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -6677,12 +6677,12 @@ GEN_TM_PRIV_NOOP(trechkpt); > > static inline void get_fpr(TCGv_i64 dst, int regno) > { > - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); > + tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); > } > > static inline void set_fpr(int regno, TCGv_i64 src) > { > - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); > + tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); > } > > static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 26604ddf98..4bb4e42670 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2563,9 +2563,14 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx) } /* Accessors for FP, VMX and VSX registers */ +static inline int fpr_offset(int i) +{ + return offsetof(CPUPPCState, vsr[i].u64[0]); +} + static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) { - return &env->vsr[i].u64[0]; + return (uint64_t *)((uintptr_t)env + fpr_offset(i)); } static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 819221f246..3b1992faf1 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6677,12 +6677,12 @@ GEN_TM_PRIV_NOOP(trechkpt); static inline void get_fpr(TCGv_i64 dst, int regno) { - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); + tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); } static inline void set_fpr(int regno, TCGv_i64 src) { - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); + tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); } static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
Instead of having multiple copies of the offset calculation logic, move it to a single fpr_offset() function. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> --- target/ppc/cpu.h | 7 ++++++- target/ppc/translate.c | 4 ++-- 2 files changed, 8 insertions(+), 3 deletions(-)