[PULL,29/34] target/riscv: Remove decode_RV32_64G()

Message ID	20190301214945.4353-30-palmer@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> Date: Fri, 1 Mar 2019 13:49:40 -0800 Message-Id: <20190301214945.4353-30-palmer@sifive.com> In-Reply-To: <20190301214945.4353-1-palmer@sifive.com> References: <20190301214945.4353-1-palmer@sifive.com> From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 29/34] target/riscv: Remove decode_RV32_64G() Precedence: list Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Peer Adelt <peer.adelt@hni.uni-paderborn.de>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt <palmer@sifive.com> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL] target/riscv: Convert to decodetree \| expand [PULL] target/riscv: Convert to decodetree [PULL,02/34] target/riscv: Convert RVXI branch insns to decodetree [PULL,03/34] target/riscv: Convert RV32I load/store insns to decodetree [PULL,04/34] target/riscv: Convert RV64I load/store insns to decodetree [PULL,05/34] target/riscv: Convert RVXI arithmetic insns to decodetree [PULL,06/34] target/riscv: Convert RVXI fence insns to decodetree [PULL,07/34] target/riscv: Convert RVXI csr insns to decodetree [PULL,08/34] target/riscv: Convert RVXM insns to decodetree [PULL,09/34] target/riscv: Convert RV32A insns to decodetree [PULL,10/34] target/riscv: Convert RV64A insns to decodetree [PULL,11/34] target/riscv: Convert RV32F insns to decodetree [PULL,12/34] target/riscv: Convert RV64F insns to decodetree [PULL,13/34] target/riscv: Convert RV32D insns to decodetree [PULL,14/34] target/riscv: Convert RV64D insns to decodetree [PULL,15/34] target/riscv: Convert RV priv insns to decodetree [PULL,16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree [PULL,17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree [PULL,18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree [PULL,19/34] target/riscv: Remove gen_jalr() [PULL,20/34] target/riscv: Remove manual decoding from gen_branch() [PULL,21/34] target/riscv: Remove manual decoding from gen_load() [PULL,22/34] target/riscv: Remove manual decoding from gen_store() [PULL,23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions [PULL,24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists [PULL,25/34] target/riscv: Remove shift and slt insn manual decoding [PULL,26/34] target/riscv: Remove manual decoding of RV32/64M insn [PULL,27/34] target/riscv: Rename trans_arith to gen_arith [PULL,28/34] target/riscv: Remove gen_system() [PULL,29/34] target/riscv: Remove decode_RV32_64G() [PULL,30/34] target/riscv: Convert @cs_2 insns to share translation functions [PULL,31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns [PULL,32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 [PULL,33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 [PULL,34/34] target/riscv: Remaining rvc insn reuse 32 bit translators

Message ID

20190301214945.4353-30-palmer@sifive.com

State

New

Headers

Date: Fri,  1 Mar 2019 13:49:40 -0800
Message-Id: <20190301214945.4353-30-palmer@sifive.com>
In-Reply-To: <20190301214945.4353-1-palmer@sifive.com>
References: <20190301214945.4353-1-palmer@sifive.com>
From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Subject: [Qemu-devel] [PULL 29/34] target/riscv: Remove decode_RV32_64G()
Precedence: list
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Peer Adelt <peer.adelt@hni.uni-paderborn.de>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Palmer Dabbelt <palmer@sifive.com>
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

[PULL] target/riscv: Convert to decodetree | expand

Commit Message

Palmer Dabbelt March 1, 2019, 9:49 p.m. UTC

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

decodetree handles all instructions now so the fallback is not necessary
anymore.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/translate.c | 21 +--------------------
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 92be090bc7bb..049fa65c6611 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -651,24 +651,6 @@  bool decode_insn16(DisasContext *ctx, uint16_t insn);
 #include "decode_insn16.inc.c"
 #include "insn_trans/trans_rvc.inc.c"
 
-static void decode_RV32_64G(DisasContext *ctx)
-{
-    uint32_t op;
-
-    /* We do not do misaligned address check here: the address should never be
-     * misaligned at this point. Instructions that set PC must do the check,
-     * since epc must be the address of the instruction that caused us to
-     * perform the misaligned instruction fetch */
-
-    op = MASK_OP_MAJOR(ctx->opcode);
-
-    switch (op) {
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-}
-
 static void decode_opc(DisasContext *ctx)
 {
     /* check for compressed insn */
@@ -685,8 +667,7 @@  static void decode_opc(DisasContext *ctx)
     } else {
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
         if (!decode_insn32(ctx, ctx->opcode)) {
-            /* fallback to old decoder */
-            decode_RV32_64G(ctx);
+            gen_exception_illegal(ctx);
         }
     }
 }

[PULL,29/34] target/riscv: Remove decode_RV32_64G()

Commit Message

Patch