| Message ID | 20190223023957.18865-4-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Define cortex-a{73, 75, 76} | expand |
On Sat, 23 Feb 2019 at 02:40, Richard Henderson <richard.henderson@linaro.org> wrote: > > This was res0 before ARMv8.2, but will shortly be used by > new processor definitions. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 15 +++++++++++++++ > target/arm/helper.c | 4 ++-- > target/arm/kvm64.c | 2 ++ > 3 files changed, 19 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index c2899f0bed..02642a7db3 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -855,6 +855,7 @@ struct ARMCPU { > uint64_t id_aa64pfr1; > uint64_t id_aa64mmfr0; > uint64_t id_aa64mmfr1; > + uint64_t id_aa64mmfr2; > } isar; > uint32_t midr; > uint32_t revidr; > @@ -1724,6 +1725,20 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4) > FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) > FIELD(ID_AA64MMFR1, XNX, 28, 4) > > +FIELD(ID_AA64MMFR2, CNP, 0, 4) > +FIELD(ID_AA64MMFR2, UAO, 4, 4) > +FIELD(ID_AA64MMFR2, LSM, 8, 4) > +FIELD(ID_AA64MMFR2, IESB, 12, 4) > +FIELD(ID_AA64MMFR2, VARANGE, 16, 4) > +FIELD(ID_AA64MMFR2, CCIDX, 20, 4) > +FIELD(ID_AA64MMFR2, NV, 24, 4) > +FIELD(ID_AA64MMFR2, ST, 28, 4) > +FIELD(ID_AA64MMFR2, AT, 32, 4) > +FIELD(ID_AA64MMFR2, IDS, 36, 4) > +FIELD(ID_AA64MMFR2, FWB, 40, 4) > +FIELD(ID_AA64MMFR2, TTL, 48, 4) > +FIELD(ID_AA64MMFR2, BBM, 52, 4) While we're here: FIELD(ID_AA64MMFR2, EVT, 56, 4) FIELD(ID_AA64MMFR2, E0PD, 60, 4) (from arm v8.5, see https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64mmfr2_el1 ) otherwise Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c2899f0bed..02642a7db3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -855,6 +855,7 @@ struct ARMCPU { uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; + uint64_t id_aa64mmfr2; } isar; uint32_t midr; uint32_t revidr; @@ -1724,6 +1725,20 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) +FIELD(ID_AA64MMFR2, CNP, 0, 4) +FIELD(ID_AA64MMFR2, UAO, 4, 4) +FIELD(ID_AA64MMFR2, LSM, 8, 4) +FIELD(ID_AA64MMFR2, IESB, 12, 4) +FIELD(ID_AA64MMFR2, VARANGE, 16, 4) +FIELD(ID_AA64MMFR2, CCIDX, 20, 4) +FIELD(ID_AA64MMFR2, NV, 24, 4) +FIELD(ID_AA64MMFR2, ST, 28, 4) +FIELD(ID_AA64MMFR2, AT, 32, 4) +FIELD(ID_AA64MMFR2, IDS, 36, 4) +FIELD(ID_AA64MMFR2, FWB, 40, 4) +FIELD(ID_AA64MMFR2, TTL, 48, 4) +FIELD(ID_AA64MMFR2, BBM, 52, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8903cc13d8..fbdca9324b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6052,10 +6052,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->isar.id_aa64mmfr1 }, - { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64mmfr2 }, { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index e3ba149248..c3d421b53b 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -542,6 +542,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 7, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); /* * Note that if AArch32 support is not present in the host,
This was res0 before ARMv8.2, but will shortly be used by new processor definitions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 15 +++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 19 insertions(+), 2 deletions(-)