From patchwork Fri Feb 22 08:11:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 1046640 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 445PKr0G6Lz9s70 for ; Fri, 22 Feb 2019 19:15:44 +1100 (AEDT) Received: from localhost ([127.0.0.1]:46480 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gx5zh-0006Xc-Uu for incoming@patchwork.ozlabs.org; Fri, 22 Feb 2019 03:15:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43555) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gx5wN-0004LF-L8 for qemu-devel@nongnu.org; Fri, 22 Feb 2019 03:12:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gx5wL-0007Cw-NT for qemu-devel@nongnu.org; Fri, 22 Feb 2019 03:12:15 -0500 Received: from mx1.redhat.com ([209.132.183.28]:36736) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gx5wK-00079o-Nu; Fri, 22 Feb 2019 03:12:13 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D3F77300486F; Fri, 22 Feb 2019 08:12:11 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-150.ams2.redhat.com [10.36.117.150]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0618C1001947; Fri, 22 Feb 2019 08:12:09 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 09:11:53 +0100 Message-Id: <20190222081153.14206-4-david@redhat.com> In-Reply-To: <20190222081153.14206-1-david@redhat.com> References: <20190222081153.14206-1-david@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.40]); Fri, 22 Feb 2019 08:12:11 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v1 3/3] s390x/tcg: Save vregs to extended mchk save area X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" If we have vector registers and the designation is not zero, we have to try to write the vector registers. If the designation is zero or if storing fails, we must not indicate validity. s390_build_validity_mcic() automatically already sets validity if the vector instruction facility is installed. As long as we don't support the guarded-storage facility, the alignemnt & size of the area is always 1024 bytes. Signed-off-by: David Hildenbrand Reviewed-by: Thomas Huth --- target/s390x/excp_helper.c | 46 ++++++++++++++++++++++++++++++++++++-- target/s390x/internal.h | 4 +++- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index a758649f47..f84bfb1284 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -347,10 +347,41 @@ static void do_io_interrupt(CPUS390XState *env) load_psw(env, mask, addr); } +typedef struct MchkExtSaveArea { + uint64_t vregs[32][2]; /* 0x0000 */ + uint8_t pad_0x0200[0x0400 - 0x0200]; /* 0x0200 */ +} MchkExtSaveArea; +QEMU_BUILD_BUG_ON(sizeof(MchkExtSaveArea) != 1024); + +static int mchk_store_vregs(CPUS390XState *env, uint64_t mcesao) +{ + hwaddr len = sizeof(MchkExtSaveArea); + MchkExtSaveArea *sa; + int i; + + sa = cpu_physical_memory_map(mcesao, &len, 1); + if (!sa) { + return -EFAULT; + } + if (len != sizeof(MchkExtSaveArea)) { + cpu_physical_memory_unmap(sa, len, 1, 0); + return -EFAULT; + } + + for (i = 0; i < 32; i++) { + sa->vregs[i][0] = cpu_to_be64(env->vregs[i][0].ll); + sa->vregs[i][1] = cpu_to_be64(env->vregs[i][1].ll); + } + + cpu_physical_memory_unmap(sa, len, 1, len); + return 0; +} + static void do_mchk_interrupt(CPUS390XState *env) { QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic()); - uint64_t mask, addr; + uint64_t mcic = s390_build_validity_mcic() | MCIC_SC_CP; + uint64_t mask, addr, mcesao = 0; LowCore *lowcore; int i; @@ -362,6 +393,17 @@ static void do_mchk_interrupt(CPUS390XState *env) lowcore = cpu_map_lowcore(env); + /* extended save area */ + if (mcic & MCIC_VB_VR) { + /* length and alignment is 1024 bytes */ + mcesao = be64_to_cpu(lowcore->mcesad) & ~0x3ffull; + } + + /* try to store vector registers */ + if (!mcesao || mchk_store_vregs(env, mcesao)) { + mcic &= ~MCIC_VB_VR; + } + /* we are always in z/Architecture mode */ lowcore->ar_access_id = 1; @@ -377,7 +419,7 @@ static void do_mchk_interrupt(CPUS390XState *env) lowcore->cpu_timer_save_area = cpu_to_be64(env->cputm); lowcore->clock_comp_save_area = cpu_to_be64(env->ckc >> 8); - lowcore->mcic = cpu_to_be64(s390_build_validity_mcic() | MCIC_SC_CP); + lowcore->mcic = cpu_to_be64(mcic); lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env)); lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr); mask = be64_to_cpu(lowcore->mcck_new_psw.mask); diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 122fe037bc..cbeef3515b 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -101,7 +101,9 @@ typedef struct LowCore { /* whether the kernel died with panic() or not */ uint32_t panic_magic; /* 0xe00 */ - uint8_t pad13[0x11b8 - 0xe04]; /* 0xe04 */ + uint8_t pad13[0x11b0 - 0xe04]; /* 0xe04 */ + + uint64_t mcesad; /* 0x11B0 */ /* 64 bit extparam used for pfault, diag 250 etc */ uint64_t ext_params2; /* 0x11B8 */