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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.09.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:09:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:26 -0800 Message-Id: <20190211010829.29869-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 23/26] target/arm: Add allocation tag storage for user mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Control this with x-tagged-pages, which is off by default. The limitation to non-shared pages is not part of a future kernel API, but a limitation of linux-user not being able to map virtual pages back to physical pages. Signed-off-by: Richard Henderson --- v2: Add the x-tagged-pages cpu property --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 18 ++++++++++++++++++ target/arm/mte_helper.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2626af4a9c..ec5ddfbacc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -910,6 +910,7 @@ struct ARMCPU { #ifdef CONFIG_USER_ONLY bool guarded_pages; + bool tagged_pages; #endif QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c5675fe7d1..53a7d92c95 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -293,6 +293,18 @@ static void aarch64_cpu_set_guarded_pages(Object *obj, bool val, Error **errp) ARMCPU *cpu = ARM_CPU(obj); cpu->guarded_pages = val; } + +static bool aarch64_cpu_get_tagged_pages(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + return cpu->tagged_pages; +} + +static void aarch64_cpu_set_tagged_pages(Object *obj, bool val, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + cpu->tagged_pages = val; +} #endif /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); @@ -380,6 +392,12 @@ static void aarch64_max_initfn(Object *obj) aarch64_cpu_set_guarded_pages, NULL); object_property_set_description(obj, "x-guarded-pages", "Set on/off GuardPage bit for all pages", NULL); + + object_property_add_bool(obj, "x-tagged-pages", + aarch64_cpu_get_tagged_pages, + aarch64_cpu_set_tagged_pages, NULL); + object_property_set_description(obj, "x-tagged-pages", + "Set on/off MemAttr Tagged for all pages", NULL); #endif cpu->sve_max_vq = ARM_MAX_VQ; diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 93f7cccee2..ad2902472d 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -53,8 +53,45 @@ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY + ARMCPU *cpu = arm_env_get_cpu(env); + uint64_t clean_ptr = strip_tbi(env, ptr); + uint8_t *tags; + uintptr_t index; + int flags; + + flags = page_get_flags(clean_ptr); + + if (!(flags & PAGE_VALID) || !(flags & (write ? PAGE_WRITE : PAGE_READ))) { + /* SIGSEGV */ + env->exception.vaddress = ptr; + cpu_restore_state(CPU(cpu), ra, true); + raise_exception(env, EXCP_DATA_ABORT, 0, 1); + } + + if (!cpu->tagged_pages) { + /* Tag storage is disabled. */ + return NULL; + } + if (flags & PAGE_SHARED) { + /* There may be multiple mappings; pretend not implemented. */ + return NULL; + } + + tags = page_get_target_data(clean_ptr); + if (tags == NULL) { + size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags = page_alloc_target_data(clean_ptr, alloc_size); + assert(tags != NULL); + } + + index = extract32(clean_ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return tags + index; +#else /* Tag storage not implemented. */ return NULL; +#endif } static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra)