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[PULL,1/2] i386: Update stepping of Cascadelake-Server

Message ID 20190128193834.3823-2-ehabkost@redhat.com
State New
Headers show
Series [PULL,1/2] i386: Update stepping of Cascadelake-Server | expand

Commit Message

Eduardo Habkost Jan. 28, 2019, 7:38 p.m. UTC 
From: Tao Xu <tao3.xu@intel.com>

Update the stepping from 5 to 6, in order that
the Cascadelake-Server CPU model can support AVX512VNNI
and MSR based features exposed by ARCH_CAPABILITIES.

Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20181227024304.12182-2-tao3.xu@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 hw/i386/pc.c      | 1 +
 target/i386/cpu.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)
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Patch

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 747548b7aa..94ac9dee3d 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -122,6 +122,7 @@  GlobalProperty pc_compat_3_1[] = {
     { "Cascadelake-Server" "-" TYPE_X86_CPU,  "mpx", "on" },
     { "Icelake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
     { "Icelake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
+    { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
 };
 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
 
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2f5412592d..43df813327 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2503,7 +2503,7 @@  static X86CPUDefinition builtin_x86_defs[] = {
         .vendor = CPUID_VENDOR_INTEL,
         .family = 6,
         .model = 85,
-        .stepping = 5,
+        .stepping = 6,
         .features[FEAT_1_EDX] =
             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |