From patchwork Wed Jan 23 09:25:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 1029800 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mail.uni-paderborn.de Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43l0PJ4SQpz9s4s for ; Wed, 23 Jan 2019 20:29:56 +1100 (AEDT) Received: from localhost ([127.0.0.1]:58790 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gmEr4-0002QV-HA for incoming@patchwork.ozlabs.org; Wed, 23 Jan 2019 04:29:54 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40436) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gmEnq-00005e-HW for qemu-devel@nongnu.org; Wed, 23 Jan 2019 04:26:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gmEnp-0007Ll-AU for qemu-devel@nongnu.org; Wed, 23 Jan 2019 04:26:34 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:50916) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gmEnj-0007IX-6C; Wed, 23 Jan 2019 04:26:27 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 hoth) id 1gmEnh-0003lj-Rr; Wed, 23 Jan 2019 10:26:25 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3072078-4; Wed, 23 Jan 2019 09:26:24 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Wed, 23 Jan 2019 10:25:08 +0100 Message-Id: <20190123092538.8004-6-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> References: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.23.91816, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I load/store insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Alistair Francis , peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/Makefile.objs | 8 +++++--- target/riscv/insn32-64.decode | 25 +++++++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 20 ++++++++++++++++++++ target/riscv/translate.c | 7 ------- 4 files changed, 50 insertions(+), 10 deletions(-) create mode 100644 target/riscv/insn32-64.decode diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index bf0a268033..05087a91bb 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -2,10 +2,12 @@ obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py -target/riscv/decode_insn32.inc.c: \ - $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE) +decode32-y = $(SRC_PATH)/target/riscv/insn32.decode +decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode + +target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ "GEN", $(TARGET_DIR)$@) target/riscv/translate.o: target/riscv/decode_insn32.inc.c diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode new file mode 100644 index 0000000000..439d4e2c58 --- /dev/null +++ b/target/riscv/insn32-64.decode @@ -0,0 +1,25 @@ +# +# RISC-V translation routines for the RV Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +# This is concatenated with insn32.decode for risc64 targets. +# Most of the fields and formats are there. + +# *** RV64I Base Instruction Set (in addition to RV32I) *** +lwu ............ ..... 110 ..... 0000011 @i +ld ............ ..... 011 ..... 0000011 @i +sd ....... ..... ..... 011 ..... 0100011 @s diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index f3b88ebb69..39a20a70e8 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -130,3 +130,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); return true; } + +#ifdef TARGET_RISCV64 +static bool trans_lwu(DisasContext *ctx, arg_lwu *a) +{ + gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_ld(DisasContext *ctx, arg_ld *a) +{ + gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_sd(DisasContext *ctx, arg_sd *a) +{ + gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm); + return true; +} +#endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b81297f23e..609207f785 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1711,13 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) imm = GET_IMM(ctx->opcode); switch (op) { - case OPC_RISC_LOAD: - gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm); - break; - case OPC_RISC_STORE: - gen_store(ctx, MASK_OP_STORE(ctx->opcode), rs1, rs2, - GET_STORE_IMM(ctx->opcode)); - break; case OPC_RISC_ARITH_IMM: #if defined(TARGET_RISCV64) case OPC_RISC_ARITH_IMM_W: