From patchwork Tue Jan 8 22:31:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1022192 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="WMtx8eMW"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43Z6yK1wBQz9sCX for ; Wed, 9 Jan 2019 09:54:17 +1100 (AEDT) Received: from localhost ([127.0.0.1]:45262 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh0GE-0004Mg-JI for incoming@patchwork.ozlabs.org; Tue, 08 Jan 2019 17:54:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52867) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvF-0000P5-9e for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzvE-0004xk-He for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:33 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:45183) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzvE-0004x5-By for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:32 -0500 Received: by mail-pg1-x541.google.com with SMTP id y4so2343324pgc.12 for ; Tue, 08 Jan 2019 14:32:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Jm0q4VrYesXT+1aKV7gHpLk65YgMU1hEIfu+1DhEv/c=; b=WMtx8eMW2AHj0ZMaV3Cpc/+FQw6m91bFOE7+VuwQIl+sbqjLq9+o25PqWPdQyr+qut 1ZEMQ3IsimLdDqEDi0f6J6CefAl7x6OVDUoWmB719JGQ6mb5/74XWvAva73HUC5RNbP3 nbMayOMZMV91W1PFJS4PeCbFKRXmeTSuuWqdk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jm0q4VrYesXT+1aKV7gHpLk65YgMU1hEIfu+1DhEv/c=; b=M0dkomZmrQuDc09HK7Fda7tQypR4aPHizkhSSZGN1CkDl0kLW55fvZ9dRONC+j0Ppn JLWNOdQyZQVmD4Wtd7UpLN0jnm/PHQRhBM08kyiZZnC1Yk1TR8LFzZFbSWY20agmNO5j ocA2axPI6C9NEPzRSLtGxEOsExlvtvedACztQqaw8O7k/kwODSBMTm0JqGs2BY+0MyKO 6QalWTHaUOSD1B1f6qvZiuRbf4barXVO85PsnzxtcrrZT50lXO8KqGStjAPNL+RVu6Og SwTrNxNPOPOpVifcIEboPT2VNs8NzDpqSQ8070fhaYvTCzR+LFn92PGBQojlxCorzCtp BJ7Q== X-Gm-Message-State: AJcUukex0H/EVsJ8HbxZLVW/jp/Hn7XbrkInxd/Ao0mBQBsHuHV4R9lL jb+YrX2iyNj6geSzoXVl6NoBX2xODo8= X-Google-Smtp-Source: ALg8bN5KutrBPgPLVShQsk7oCQt7K9jioLYqnUa+xmD4jIUgkRdGRwHUTfzWfsNkHrdR55ovZfvEkg== X-Received: by 2002:a63:2d46:: with SMTP id t67mr3216839pgt.140.1546986751013; Tue, 08 Jan 2019 14:32:31 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:19 +1000 Message-Id: <20190108223129.5570-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 21/31] target/arm: Add aa64_va_parameters_both X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We will want to check TBI for I and D simultaneously. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 15 ++++++++++++--- target/arm/helper.c | 10 ++++++++-- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 82cf685695..acd99b579c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -957,9 +957,9 @@ typedef struct ARMVAParameters { } ARMVAParameters; #ifdef CONFIG_USER_ONLY -static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, - uint64_t va, - ARMMMUIdx mmu_idx, bool data) +static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env, + uint64_t va, + ARMMMUIdx mmu_idx) { return (ARMVAParameters) { /* 48-bit address space */ @@ -968,7 +968,16 @@ static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, .tbi = false, }; } + +static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, + uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + return aa64_va_parameters_both(env, va, mmu_idx); +} #else +ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx); ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index f4538c9f82..28322ae109 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9744,8 +9744,8 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } -ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) +ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); @@ -9799,6 +9799,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, }; } +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + return aa64_va_parameters_both(env, va, mmu_idx); +} + static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) {