| Message ID | 20181221140321.7750-1-vkuznets@redhat.com |
|---|---|
| State | New |
| Headers | show |
| Series | [RFC] i386: Enable NPT and NRIPSAVE for Epyc CPUs | expand |
Vitaly Kuznetsov <vkuznets@redhat.com> writes: > Epyc CPUs support NPT and NRIPSAVE features and KVM exposes these when > present. Add them to EPYC and EPYC-IBPB cpu models. > > Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> > --- > - RFC part: I'm not sure when these features first appeared, we may want to > modify some Opteron_* models too. According to http://instlatx64.atw.hu/ data (thanks to Radim!) NRIPSAVE apeared somewhere in Opteron_G3 lifetime (e.g. QuadCore AMD Opteron 2378 has is, QuadCore AMD Opteron HE 2344 doesn't), NPT was introduced a bit earlier. To be on the safe side we can probably add NPT and NRIPSAVE to Opteron_G4 and Opteron_G5 too and leave Opteron_G3 as it is.
On Fri, Dec 21, 2018 at 03:03:21PM +0100, Vitaly Kuznetsov wrote: > Epyc CPUs support NPT and NRIPSAVE features and KVM exposes these when > present. Add them to EPYC and EPYC-IBPB cpu models. > > Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Sorry for taking so long to reply: > --- > - RFC part: I'm not sure when these features first appeared, we may want to > modify some Opteron_* models too. > --- > target/i386/cpu.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 677a3bd5fb..0a10fbeccc 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -2843,6 +2843,8 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_XSAVE_XGETBV1, > .features[FEAT_6_EAX] = > CPUID_6_EAX_ARAT, > + .features[FEAT_SVM] = > + CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, You'll need to add EPYC*.ntp=off and EPYC*.nripsave=off to pc_compat_3_1. > .xlevel = 0x8000001E, > .model_id = "AMD EPYC Processor", > .cache_info = &epyc_cache_info, > @@ -2891,6 +2893,8 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_XSAVE_XGETBV1, > .features[FEAT_6_EAX] = > CPUID_6_EAX_ARAT, > + .features[FEAT_SVM] = > + CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, > .xlevel = 0x8000001E, > .model_id = "AMD EPYC Processor (with IBPB)", > .cache_info = &epyc_cache_info, > -- > 2.19.2 >
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 677a3bd5fb..0a10fbeccc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2843,6 +2843,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XGETBV1, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, + .features[FEAT_SVM] = + CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, .xlevel = 0x8000001E, .model_id = "AMD EPYC Processor", .cache_info = &epyc_cache_info, @@ -2891,6 +2893,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XGETBV1, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, + .features[FEAT_SVM] = + CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, .xlevel = 0x8000001E, .model_id = "AMD EPYC Processor (with IBPB)", .cache_info = &epyc_cache_info,
Epyc CPUs support NPT and NRIPSAVE features and KVM exposes these when present. Add them to EPYC and EPYC-IBPB cpu models. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> --- - RFC part: I'm not sure when these features first appeared, we may want to modify some Opteron_* models too. --- target/i386/cpu.c | 4 ++++ 1 file changed, 4 insertions(+)