| Message ID | 20181220121100.21554-1-pbonzini@redhat.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/i386: Disable MPX support on named CPU models | expand |
On 12/20/2018 10:11 AM, Paolo Bonzini wrote: > MPX support is being phased out by Intel; GCC has dropped it, Linux > is also going to do that. Even though KVM will have special code > to support MPX after the kernel proper stops enabling it in XCR0, > we probably also want to deprecate that in a few years. As a start, > do not enable it by default for any named CPU model starting with > the 4.0 machine types; this include Skylake, Icelake and Cascadelake. > > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > --- > include/hw/i386/pc.h | 29 +++++++++++++++++++++++++++++ > target/i386/cpu.c | 14 +++++++------- > 2 files changed, 36 insertions(+), 7 deletions(-) Side question: I didn't find on QEMU's user manual any reference to deprecated features for CPU models. Does that information exists somewhere? If not, should it be documented for the users? Anyway, Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> > > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h > index 9d29c4b1df..39619e9c01 100644 > --- a/include/hw/i386/pc.h > +++ b/include/hw/i386/pc.h > @@ -296,6 +296,35 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); > > #define PC_COMPAT_3_1 \ > HW_COMPAT_3_1 \ > + {\ > + .driver = "Skylake-Client" "-" TYPE_X86_CPU,\ > + .property = "mpx",\ > + .value = "on",\ > + },{\ > + .driver = "Skylake-Client-IBRS" "-" TYPE_X86_CPU,\ > + .property = "mpx",\ > + .value = "on",\ > + },{\ > + .driver = "Skylake-Server" "-" TYPE_X86_CPU,\ > + .property = "mpx",\ > + .value = "on",\ > + },{\ > + .driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU,\ > + .property = "mpx",\ > + .value = "on",\ > + },{\ > + .driver = "Cascadelake-Server" "-" TYPE_X86_CPU,\ > + .property = "mpx",\ > + .value = "on",\ > + },{\ > + .driver = "Icelake-Client" "-" TYPE_X86_CPU,\ > + .property = "mpx",\ > + .value = "on",\ > + },{\ > + .driver = "Icelake-Server" "-" TYPE_X86_CPU,\ > + .property = "mpx",\ > + .value = "on",\ > + }, > > #define PC_COMPAT_3_0 \ > HW_COMPAT_3_0 \ > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 677a3bd5fb..1dc1f569da 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -2296,7 +2296,7 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | > CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | > - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX, > + CPUID_7_0_EBX_SMAP, > /* Missing: XSAVES (not supported by some Linux versions, > * including v4.1 to v4.12). > * KVM doesn't yet expose any XSAVES state save component, > @@ -2343,7 +2343,7 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | > CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | > - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX, > + CPUID_7_0_EBX_SMAP, > /* Missing: XSAVES (not supported by some Linux versions, > * including v4.1 to v4.12). > * KVM doesn't yet expose any XSAVES state save component, > @@ -2388,7 +2388,7 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | > CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | > - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB | > + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | > CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | > CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | > CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, > @@ -2440,7 +2440,7 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | > CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | > - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB | > + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | > CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | > CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | > CPUID_7_0_EBX_AVX512VL, > @@ -2490,7 +2490,7 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | > CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | > - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB | > + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | > CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | > CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | > CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT | > @@ -2546,7 +2546,7 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | > CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | > - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INTEL_PT, > + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_INTEL_PT, > .features[FEAT_7_0_ECX] = > CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | > CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI | > @@ -2601,7 +2601,7 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | > CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | > - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB | > + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | > CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | > CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | > CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
On 20/12/18 15:18, Wainer dos Santos Moschetta wrote: > > On 12/20/2018 10:11 AM, Paolo Bonzini wrote: >> MPX support is being phased out by Intel; GCC has dropped it, Linux >> is also going to do that. Even though KVM will have special code >> to support MPX after the kernel proper stops enabling it in XCR0, >> we probably also want to deprecate that in a few years. As a start, >> do not enable it by default for any named CPU model starting with >> the 4.0 machine types; this include Skylake, Icelake and Cascadelake. >> >> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> >> --- >> include/hw/i386/pc.h | 29 +++++++++++++++++++++++++++++ >> target/i386/cpu.c | 14 +++++++------- >> 2 files changed, 36 insertions(+), 7 deletions(-) > > Side question: I didn't find on QEMU's user manual any reference to > deprecated features for CPU models. Does that information exists > somewhere? If not, should it be documented for the users? It's not deprecated yet, as it won't be removed until pc-*-3.1 is deprecated. It may be deprecated together with pc-*-3.1, or maybe not since TCG does implement MPX. Paolo
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 9d29c4b1df..39619e9c01 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -296,6 +296,35 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); #define PC_COMPAT_3_1 \ HW_COMPAT_3_1 \ + {\ + .driver = "Skylake-Client" "-" TYPE_X86_CPU,\ + .property = "mpx",\ + .value = "on",\ + },{\ + .driver = "Skylake-Client-IBRS" "-" TYPE_X86_CPU,\ + .property = "mpx",\ + .value = "on",\ + },{\ + .driver = "Skylake-Server" "-" TYPE_X86_CPU,\ + .property = "mpx",\ + .value = "on",\ + },{\ + .driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU,\ + .property = "mpx",\ + .value = "on",\ + },{\ + .driver = "Cascadelake-Server" "-" TYPE_X86_CPU,\ + .property = "mpx",\ + .value = "on",\ + },{\ + .driver = "Icelake-Client" "-" TYPE_X86_CPU,\ + .property = "mpx",\ + .value = "on",\ + },{\ + .driver = "Icelake-Server" "-" TYPE_X86_CPU,\ + .property = "mpx",\ + .value = "on",\ + }, #define PC_COMPAT_3_0 \ HW_COMPAT_3_0 \ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 677a3bd5fb..1dc1f569da 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2296,7 +2296,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX, + CPUID_7_0_EBX_SMAP, /* Missing: XSAVES (not supported by some Linux versions, * including v4.1 to v4.12). * KVM doesn't yet expose any XSAVES state save component, @@ -2343,7 +2343,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX, + CPUID_7_0_EBX_SMAP, /* Missing: XSAVES (not supported by some Linux versions, * including v4.1 to v4.12). * KVM doesn't yet expose any XSAVES state save component, @@ -2388,7 +2388,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, @@ -2440,7 +2440,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512VL, @@ -2490,7 +2490,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT | @@ -2546,7 +2546,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INTEL_PT, + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_INTEL_PT, .features[FEAT_7_0_ECX] = CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI | @@ -2601,7 +2601,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | - CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
MPX support is being phased out by Intel; GCC has dropped it, Linux is also going to do that. Even though KVM will have special code to support MPX after the kernel proper stops enabling it in XCR0, we probably also want to deprecate that in a few years. As a start, do not enable it by default for any named CPU model starting with the 4.0 machine types; this include Skylake, Icelake and Cascadelake. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- include/hw/i386/pc.h | 29 +++++++++++++++++++++++++++++ target/i386/cpu.c | 14 +++++++------- 2 files changed, 36 insertions(+), 7 deletions(-)