From patchwork Mon Dec 17 20:04:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 1014730 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43JXGs3Jbbz9s1c for ; Tue, 18 Dec 2018 07:06:29 +1100 (AEDT) Received: from localhost ([::1]:49345 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYz9m-0005ma-TX for incoming@patchwork.ozlabs.org; Mon, 17 Dec 2018 15:06:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40735) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYz8T-0005Di-HR for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gYz8Q-0001Ua-3T for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:05 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:42701 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gYz8N-0001R8-Gh for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:01 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 5BCBD1A4720; Mon, 17 Dec 2018 21:04:56 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from localhost.localdomain (unknown [109.207.46.66]) by mail.rt-rk.com (Postfix) with ESMTPSA id 102671A1D0C; Mon, 17 Dec 2018 21:04:56 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org, jancraig@amazon.com, smarkovic@wavecomp.com, amarkovic@wavecomp.com Date: Mon, 17 Dec 2018 21:04:41 +0100 Message-Id: <20181217200444.14812-4-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> References: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 3/6] target/mips: MXU: Improve textual description X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Improve textual description of MXU extension. These are mostly comment formatting changes. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 74 ++++++++++++++++++++++++----------------- 1 file changed, 44 insertions(+), 30 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 74d16ce52e..e3a5a73e59 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1399,10 +1399,12 @@ enum { /* - * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET - * ============================================ * - * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32 + * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET + * ============================================ + * + * + * MXU (full name: MIPS eXtension/enhanced Unit) is a SIMD extension of MIPS32 * instructions set. It is designed to fit the needs of signal, graphical and * video processing applications. MXU instruction set is used in Xburst family * of microprocessors by Ingenic. @@ -1410,39 +1412,31 @@ enum { * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is * the control register. * - * The notation used in MXU assembler mnemonics - * -------------------------------------------- * - * Registers: + * The notation used in MXU assembler mnemonics + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * Register operands: * * XRa, XRb, XRc, XRd - MXU registers * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers * - * Subfields: + * Non-register operands: * - * aptn1 - 1-bit accumulate add/subtract pattern - * aptn2 - 2-bit accumulate add/subtract pattern - * eptn2 - 2-bit execute add/subtract pattern - * optn2 - 2-bit operand pattern - * optn3 - 3-bit operand pattern - * sft4 - 4-bit shift amount - * strd2 - 2-bit stride amount + * aptn1 - 1-bit accumulate add/subtract pattern + * aptn2 - 2-bit accumulate add/subtract pattern + * eptn2 - 2-bit execute add/subtract pattern + * optn2 - 2-bit operand pattern + * optn3 - 3-bit operand pattern + * sft4 - 4-bit shift amount + * strd2 - 2-bit stride amount * * Prefixes: * - * - * S 32 - * D 16 - * Q 8 - * - * Suffixes: - * - * E - Expand results - * F - Fixed point multiplication - * L - Low part result - * R - Doing rounding - * V - Variable instead of immediate - * W - Combine above L and V + * Level of parallelism: Operand size: + * S - single operation at a time 32 - word + * D - two operations in parallel 16 - half word + * Q - four operations in parallel 8 - byte * * Operations: * @@ -1486,6 +1480,19 @@ enum { * SCOP - Calculate x’s scope (-1, means x<0; 0, means x==0; 1, means x>0) * XOR - Logical bitwise 'exclusive or' operation * + * Suffixes: + * + * E - Expand results + * F - Fixed point multiplication + * L - Low part result + * R - Doing rounding + * V - Variable instead of immediate + * W - Combine above L and V + * + * + * The list of MXU instructions grouped by functionality + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * * Load/Store instructions Multiplication instructions * ----------------------- --------------------------- * @@ -1563,6 +1570,13 @@ enum { * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb * * + * The opcode organization of MXU instructions + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * The bits 31..26 of all MXU instructions are equal to 0x1C (also referred + * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning of + * other bits up to the instruction level is as follows: + * * bits * 05..00 * @@ -1700,7 +1714,7 @@ enum { * │ ├─ 010 ─ OPC_MXU_D16MOVZ * │ ├─ 011 ─ OPC_MXU_D16MOVN * │ ├─ 100 ─ OPC_MXU_S32MOVZ - * │ └─ 101 ─ OPC_MXU_S32MOV + * │ └─ 101 ─ OPC_MXU_S32MOVN * │ * │ 23..22 * ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC @@ -1712,10 +1726,10 @@ enum { * └─ 111111 ─ (overlaps with SDBBP) * * - * Compiled after: + * Compiled after: * * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit - * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017 + * Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2, 2017 */ enum {