From patchwork Sun Dec 9 19:46:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1010109 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43CchY08Y3z9s3C for ; Mon, 10 Dec 2018 07:08:13 +1100 (AEDT) Received: from localhost ([::1]:56545 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gW5N4-0008Jw-Gr for incoming@patchwork.ozlabs.org; Sun, 09 Dec 2018 15:08:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36667) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gW53G-00028D-Aa for qemu-devel@nongnu.org; Sun, 09 Dec 2018 14:47:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gW53C-0006iu-5b for qemu-devel@nongnu.org; Sun, 09 Dec 2018 14:47:42 -0500 Received: from 16.mo6.mail-out.ovh.net ([87.98.139.208]:50957) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gW539-0006UY-UQ for qemu-devel@nongnu.org; Sun, 09 Dec 2018 14:47:37 -0500 Received: from player695.ha.ovh.net (unknown [10.109.159.139]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id 4052919D3BD for ; Sun, 9 Dec 2018 20:47:32 +0100 (CET) Received: from kaod.org (lfbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player695.ha.ovh.net (Postfix) with ESMTPSA id CB4098A228F; Sun, 9 Dec 2018 19:47:26 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: David Gibson Date: Sun, 9 Dec 2018 20:46:04 +0100 Message-Id: <20181209194610.29727-14-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181209194610.29727-1-clg@kaod.org> References: <20181209194610.29727-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 8166152025876302822 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrudegfedgudefudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.139.208 Subject: [Qemu-devel] [PATCH v7 13/19] spapr: add an extra OV5 field to the sPAPR IRQ backend X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This field defines the interrupt modes supported by the hypervisor in the "ibm,arch-vec-5-platform-support" property. The CAS negotiation process will select which mode to use. Signed-off-by: Cédric Le Goater --- include/hw/ppc/spapr.h | 6 ++++++ include/hw/ppc/spapr_irq.h | 1 + hw/ppc/spapr.c | 23 ++++++++++++++++++----- hw/ppc/spapr_irq.c | 3 +++ 4 files changed, 28 insertions(+), 5 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 6bf028a02fe2..daced428a42c 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -824,5 +824,11 @@ int spapr_caps_post_migration(sPAPRMachineState *spapr); void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize, Error **errp); +/* + * XIVE definitions + */ +#define SPAPR_OV5_XIVE_LEGACY 0x0 +#define SPAPR_OV5_XIVE_EXPLOIT 0x40 +#define SPAPR_OV5_XIVE_BOTH 0x80 #endif /* HW_SPAPR_H */ diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 63061a009b4c..b34d5a00381b 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -33,6 +33,7 @@ void spapr_irq_msi_reset(sPAPRMachineState *spapr); typedef struct sPAPRIrq { uint32_t nr_irqs; uint32_t nr_msis; + uint8_t ov5; void (*init)(sPAPRMachineState *spapr, Error **errp); int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 98d69f09e080..5ef87a00f68b 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1095,12 +1095,14 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) spapr_dt_rtas_tokens(fdt, rtas); } -/* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features - * that the guest may request and thus the valid values for bytes 24..26 of - * option vector 5: */ -static void spapr_dt_ov5_platform_support(void *fdt, int chosen) +/* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU + * and the XIVE features that the guest may request and thus the valid + * values for bytes 23..26 of option vector 5: */ +static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr, void *fdt, + int chosen) { PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); + sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); char val[2 * 4] = { 23, 0x00, /* Xive mode, filled in below. */ @@ -1121,7 +1123,13 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen) } else { val[3] = 0x00; /* Hash */ } + /* If the KVM XIVE device is not available, the machine can + * still operate with kernel_irqchip=off + */ + val[1] = smc->irq->ov5; } else { + val[1] = smc->irq->ov5; + /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ val[3] = 0xC0; } @@ -1189,7 +1197,7 @@ static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); } - spapr_dt_ov5_platform_support(fdt, chosen); + spapr_dt_ov5_platform_support(spapr, fdt, chosen); g_free(stdout_path); g_free(bootlist); @@ -2622,6 +2630,11 @@ static void spapr_machine_init(MachineState *machine) /* advertise support for ibm,dyamic-memory-v2 */ spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); + /* advertise XIVE */ + if (smc->irq->ov5 == SPAPR_OV5_XIVE_EXPLOIT) { + spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); + } + /* init CPUs */ spapr_init_cpus(spapr); diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 04f5c9665550..7a0d4f529763 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -220,6 +220,7 @@ static void spapr_irq_reset_xics(sPAPRMachineState *spapr, Error **errp) sPAPRIrq spapr_irq_xics = { .nr_irqs = SPAPR_IRQ_XICS_NR_IRQS, .nr_msis = SPAPR_IRQ_XICS_NR_MSIS, + .ov5 = SPAPR_OV5_XIVE_LEGACY, .init = spapr_irq_init_xics, .claim = spapr_irq_claim_xics, @@ -358,6 +359,7 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp) sPAPRIrq spapr_irq_xive = { .nr_irqs = SPAPR_IRQ_XIVE_NR_IRQS, .nr_msis = SPAPR_IRQ_XIVE_NR_MSIS, + .ov5 = SPAPR_OV5_XIVE_EXPLOIT, .init = spapr_irq_init_xive, .claim = spapr_irq_claim_xive, @@ -482,6 +484,7 @@ int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp) sPAPRIrq spapr_irq_xics_legacy = { .nr_irqs = SPAPR_IRQ_XICS_LEGACY_NR_IRQS, .nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_IRQS, + .ov5 = SPAPR_OV5_XIVE_LEGACY, .init = spapr_irq_init_xics, .claim = spapr_irq_claim_xics,