From patchwork Wed Dec 5 23:22:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1008540 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 439FqT20Bkz9s47 for ; Thu, 6 Dec 2018 10:51:01 +1100 (AEDT) Received: from localhost ([::1]:38056 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUgwU-0003CQ-Pi for incoming@patchwork.ozlabs.org; Wed, 05 Dec 2018 18:50:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44885) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUgYC-0007xM-9F for qemu-devel@nongnu.org; Wed, 05 Dec 2018 18:25:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUgY7-0004GZ-9z for qemu-devel@nongnu.org; Wed, 05 Dec 2018 18:25:52 -0500 Received: from 2.mo177.mail-out.ovh.net ([178.33.109.80]:55326) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUgY6-0004CV-OS for qemu-devel@nongnu.org; Wed, 05 Dec 2018 18:25:46 -0500 Received: from player714.ha.ovh.net (unknown [10.109.159.248]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 52F2DD5D62 for ; Thu, 6 Dec 2018 00:25:40 +0100 (CET) Received: from kaod.org (lfbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player714.ha.ovh.net (Postfix) with ESMTPSA id 154CE7D9A47; Wed, 5 Dec 2018 23:25:35 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: David Gibson Date: Thu, 6 Dec 2018 00:22:43 +0100 Message-Id: <20181205232251.10446-30-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181205232251.10446-1-clg@kaod.org> References: <20181205232251.10446-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6806064940785568742 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrudefiedguddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.109.80 Subject: [Qemu-devel] [PATCH v6 29/37] spapr: set the interrupt presenter at reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Currently, the interrupt presenter of the vCPU is set at realize time. Setting it at reset will become useful when the new machine supporting both interrupt modes is introduced. In this machine, the interrupt mode is chosen at CAS time and activated after a reset. Signed-off-by: Cédric Le Goater --- include/hw/ppc/spapr_cpu_core.h | 2 ++ hw/ppc/spapr_cpu_core.c | 26 ++++++++++++++++++++++++++ hw/ppc/spapr_irq.c | 11 +++++++++++ 3 files changed, 39 insertions(+) diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h index 9e2821e4b31f..fc8ea9021656 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -53,4 +53,6 @@ static inline sPAPRCPUState *spapr_cpu_state(PowerPCCPU *cpu) return (sPAPRCPUState *)cpu->machine_data; } +void spapr_cpu_core_set_intc(PowerPCCPU *cpu, const char *intc_type); + #endif diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 1811cd48db90..529de0b6b9c8 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -398,3 +398,29 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { }; DEFINE_TYPES(spapr_cpu_core_type_infos) + +typedef struct ForeachFindIntCArgs { + const char *intc_type; + Object *intc; +} ForeachFindIntCArgs; + +static int spapr_cpu_core_find_intc(Object *child, void *opaque) +{ + ForeachFindIntCArgs *args = opaque; + + if (object_dynamic_cast(child, args->intc_type)) { + args->intc = child; + } + + return args->intc != NULL; +} + +void spapr_cpu_core_set_intc(PowerPCCPU *cpu, const char *intc_type) +{ + ForeachFindIntCArgs args = { intc_type, NULL }; + + object_child_foreach(OBJECT(cpu), spapr_cpu_core_find_intc, &args); + g_assert(args.intc); + + cpu->intc = args.intc; +} diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 951d4ff1350a..f9b5564b271c 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -211,6 +211,11 @@ static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id) static void spapr_irq_reset_xics(sPAPRMachineState *spapr, Error **errp) { + CPUState *cs; + + CPU_FOREACH(cs) { + spapr_cpu_core_set_intc(POWERPC_CPU(cs), spapr->icp_type); + } } #define SPAPR_IRQ_XICS_NR_IRQS 0x1000 @@ -349,6 +354,12 @@ static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id) static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp) { + CPUState *cs; + + CPU_FOREACH(cs) { + spapr_cpu_core_set_intc(POWERPC_CPU(cs), TYPE_XIVE_TCTX); + } + /* * Set the OS CAM line of the cpu interrupt thread context. Needs * to come after the XiveTCTX reset handlers.