From patchwork Mon Dec 3 20:38:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1007199 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="SlFAKUcz"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 437xlz3xgWz9sBZ for ; Tue, 4 Dec 2018 07:43:27 +1100 (AEDT) Received: from localhost ([::1]:52378 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTv3t-00011M-32 for incoming@patchwork.ozlabs.org; Mon, 03 Dec 2018 15:43:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTuzb-000689-6E for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:39:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTuzX-0005pE-DC for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:59 -0500 Received: from mail-oi1-x233.google.com ([2607:f8b0:4864:20::233]:40813) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTuzX-0005nq-7a for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:55 -0500 Received: by mail-oi1-x233.google.com with SMTP id t204so12202010oie.7 for ; Mon, 03 Dec 2018 12:38:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AJQZzqFLlfuj708kX3oy8RQC53MDVoDX42PYSFxzklA=; b=SlFAKUczHxErsjJKhv8S5p3qh98lH/Fis637HBpIBjl5iWkkpJwFt7BYjFTY6yr0VG S2ZnQzozuAzg7tJL3gjXlFtzD09w3mNXWqEk/2AiKxvnFik5viC/WVowNtJ91+1mPIvp rPt7h0gaUxVhk4ihkRQhWOP7T/iuqtl5staF4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AJQZzqFLlfuj708kX3oy8RQC53MDVoDX42PYSFxzklA=; b=LIMSW8XFCohrBtXNot6a5gIjBnOAZaYO2Mhh2Hrhq57S71xeTqmXRUfd+SjdTaPlza e51CQzZIZ3uGMbVLNL2W1laErRvAEw7DEPL0fkeyExu60JOLw0N7jNJo03b21J++3zGW FdUugqwzyVFUfN9Inpk05Krp9Zcoh0/SckbdbzOW4SUImiTQSI/P/nOmq7jlm7sBzJQF 3vQUAE/QRdIQzn5YG8BscYdVOdyUtN76JSbgQb4/SSXv4QUY+vYq3O2r54pJjIlhGrXr FWjJHe15fLg+qgx3ZB+ysfllGwJSBvFOIlhbSav6v3HTXpnphi48Nf+tO9SeC6uJQH+c rpng== X-Gm-Message-State: AA+aEWa4YQsJzPjlnZGetHcZyFXL0SDJDkUkJjiW7VrbpBVhtBH3LQ44 MxfmfSADvoF6IbHUQ6i+GROrFP2bF24= X-Google-Smtp-Source: AFSGD/UF7cpDuMA4fvGCn2w0/Txso0pD1PAHsP/hrG4glm8ENr8sSg/E3EHWPBAN6XpGfxTSEnbe0w== X-Received: by 2002:aca:53cd:: with SMTP id h196mr11407859oib.355.1543869533899; Mon, 03 Dec 2018 12:38:53 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:36 -0600 Message-Id: <20181203203839.757-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::233 Subject: [Qemu-devel] [PATCH v2 07/10] target/arm: Tidy scr_write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Because EL3 has a fixed execution mode, we can properly decide which of the bits are RES{0,1}. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 2 -- target/arm/helper.c | 14 +++++++++----- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e871b946c8..a84101efa9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1312,8 +1312,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_FIEN (1U << 21) #define SCR_ENSCXT (1U << 25) #define SCR_ATA (1U << 26) -#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) -#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index b248dfcd39..faf7f922bf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1279,11 +1279,15 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* We only mask off bits that are RES0 both for AArch64 and AArch32. - * For bits that vary between AArch32/64, code needs to check the - * current execution mode before directly using the feature bit. - */ - uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; + /* Begin with base v8.0 state. */ + uint32_t valid_mask = 0x3fff; + + if (arm_el_is_aa64(env, 3)) { + value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ + valid_mask &= ~SCR_NET; + } else { + valid_mask &= ~(SCR_RW | SCR_ST); + } if (!arm_feature(env, ARM_FEATURE_EL2)) { valid_mask &= ~SCR_HCE;