From patchwork Thu Oct 25 13:32:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Eduardo Habkost X-Patchwork-Id: 989072 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42gpHw4m5kz9sBN for ; Fri, 26 Oct 2018 00:43:56 +1100 (AEDT) Received: from localhost ([::1]:54536 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFfvW-0001Vq-37 for incoming@patchwork.ozlabs.org; Thu, 25 Oct 2018 09:43:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57990) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFfnh-00031x-B2 for qemu-devel@nongnu.org; Thu, 25 Oct 2018 09:35:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFfnf-00007x-BM for qemu-devel@nongnu.org; Thu, 25 Oct 2018 09:35:48 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55700) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gFfmP-0007dh-BP; Thu, 25 Oct 2018 09:34:30 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 525EE37E8F; Thu, 25 Oct 2018 13:34:24 +0000 (UTC) Received: from localhost (unknown [10.33.36.149]) by smtp.corp.redhat.com (Postfix) with ESMTP id 58ACB5D763; Thu, 25 Oct 2018 13:34:17 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Date: Thu, 25 Oct 2018 10:32:28 -0300 Message-Id: <20181025133301.16578-11-ehabkost@redhat.com> In-Reply-To: <20181025133301.16578-1-ehabkost@redhat.com> References: <20181025133301.16578-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Thu, 25 Oct 2018 13:34:24 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL v2 10/43] hw/mips/gt64xxx_pci: Convert gt64120_reset() function into Device reset method X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" , libvir-list@redhat.com, Jason Wang , Mark Cave-Ayland , Markus Armbruster , Max Filippov , "Edgar E. Iglesias" , Rob Herring , Alexander Graf , Richard Henderson , Artyom Tarasenko , Laurent Vivier , Thomas Huth , Eduardo Habkost , Alistair Francis , qemu-arm@nongnu.org, Paolo Bonzini , David Gibson , Xiao Guangrong , Peter Crosthwaite , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Walle , qemu-ppc@nongnu.org, Aleksandar Markovic , Igor Mammedov , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Convert the gt64120_reset() function into a proper Device reset method. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Cédric Le Goater Message-Id: <20181002212522.23303-8-f4bug@amsat.org> Signed-off-by: Eduardo Habkost --- hw/mips/gt64xxx_pci.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 24ad0ad024..dcd1a66329 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -992,9 +992,9 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) } -static void gt64120_reset(void *opaque) +static void gt64120_reset(DeviceState *dev) { - GT64120State *s = opaque; + GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); /* FIXME: Malta specific hw assumptions ahead */ @@ -1184,16 +1184,6 @@ PCIBus *gt64120_register(qemu_irq *pic) return phb->bus; } -static int gt64120_init(SysBusDevice *dev) -{ - GT64120State *s; - - s = GT64120_PCI_HOST_BRIDGE(dev); - - qemu_register_reset(gt64120_reset, s); - return 0; -} - static void gt64120_pci_realize(PCIDevice *d, Error **errp) { /* FIXME: Malta specific hw assumptions ahead */ @@ -1241,9 +1231,8 @@ static const TypeInfo gt64120_pci_info = { static void gt64120_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); - sdc->init = gt64120_init; + dc->reset = gt64120_reset; dc->vmsd = &vmstate_gt64120; }