[v2,28/29] target/riscv: Remove decode_RV32_64G()

Message ID	20181020071451.27808-29-kbastian@mail.uni-paderborn.de
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Sat, 20 Oct 2018 09:14:50 +0200 Message-Id: <20181020071451.27808-29-kbastian@mail.uni-paderborn.de> In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.20.70616, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 Subject: [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G() Precedence: list Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/riscv: Convert to decodetree \| expand [v2,00/29] target/riscv: Convert to decodetree [v2,01/29] target/riscv: Move CPURISCVState pointer to DisasContext [v2,02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC [v2,03/29] target/riscv: Convert RVXI branch insns to decodetree [v2,04/29] target/riscv: Convert RVXI load/store insns to decodetree [v2,05/29] target/riscv: Convert RVXI arithmetic insns to decodetree [v2,06/29] target/riscv: Convert RVXI fence insns to decodetree [v2,07/29] target/riscv: Convert RVXI csr insns to decodetree [v2,08/29] target/riscv: Convert RVXM insns to decodetree [v2,09/29] target/riscv: Convert RV32A insns to decodetree [v2,11/29] target/riscv: Convert RV32F insns to decodetree [v2,12/29] target/riscv: Convert RV64F insns to decodetree [v2,13/29] target/riscv: Convert RV32D insns to decodetree [v2,14/29] target/riscv: Convert RV64D insns to decodetree [v2,15/29] target/riscv: Convert RV priv insns to decodetree [v2,16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree [v2,17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree [v2,18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree [v2,19/29] target/riscv: Remove gen_jalr() [v2,20/29] target/riscv: Remove manual decoding from gen_branch() [v2,21/29] target/riscv: Remove manual decoding from gen_load() [v2,22/29] target/riscv: Remove manual decoding from gen_store() [v2,23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions [v2,24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists [v2,25/29] target/riscv: Remove shift and slt insn manual decoding [v2,26/29] target/riscv: Remove manual decoding of RV32/64M insn [v2,27/29] target/riscv: Remove gen_system() [v2,28/29] target/riscv: Remove decode_RV32_64G() [v2,29/29] target/riscv: Rename trans_arith to gen_arith

Message ID

20181020071451.27808-29-kbastian@mail.uni-paderborn.de

State

New

Headers

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com,
	kbastian@mail.uni-paderborn.de
Date: Sat, 20 Oct 2018 09:14:50 +0200
Message-Id: <20181020071451.27808-29-kbastian@mail.uni-paderborn.de>
In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de>
References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G()
Precedence: list
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
	Alistair.Francis@wdc.com, qemu-devel@nongnu.org
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

target/riscv: Convert to decodetree | expand

Commit Message

Bastian Koppelmann Oct. 20, 2018, 7:14 a.m. UTC

decodetree handles all instructions now so the fallback is not necessary
anymore.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
    - Add missing gen_exception_illegal

 target/riscv/translate.c | 24 +-----------------------
 1 file changed, 1 insertion(+), 23 deletions(-)

Comments

Richard Henderson Oct. 23, 2018, 9:04 a.m. UTC | #1

On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> decodetree handles all instructions now so the fallback is not necessary
> anymore.
> 
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
> ---
> v1 -> v2:
>     - Add missing gen_exception_illegal

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a3b8792a1a..66241ecf33 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -415,27 +415,6 @@  bool decode_insn16(DisasContext *ctx, uint16_t insn);
 #include "decode_insn16.inc.c"
 #include "insn_trans/trans_rvc.inc.c"
 
-static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
-{
-    int rs1, rd;
-    uint32_t op;
-
-    /* We do not do misaligned address check here: the address should never be
-     * misaligned at this point. Instructions that set PC must do the check,
-     * since epc must be the address of the instruction that caused us to
-     * perform the misaligned instruction fetch */
-
-    op = MASK_OP_MAJOR(ctx->opcode);
-    rs1 = GET_RS1(ctx->opcode);
-    rd = GET_RD(ctx->opcode);
-
-    switch (op) {
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-}
-
 static void decode_opc(DisasContext *ctx)
 {
     /* check for compressed insn */
@@ -451,8 +430,7 @@  static void decode_opc(DisasContext *ctx)
     } else {
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
         if (!decode_insn32(ctx, ctx->opcode)) {
-            /* fallback to old decoder */
-            decode_RV32_64G(ctx->env, ctx);
+            gen_exception_illegal(ctx);
         }
     }
 }

[v2,28/29] target/riscv: Remove decode_RV32_64G()

Commit Message

Comments

Patch