From patchwork Sat Oct 20 07:14:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 987142 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mail.uni-paderborn.de Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42cZCj3WqCz9sD9 for ; Sat, 20 Oct 2018 18:29:05 +1100 (AEDT) Received: from localhost ([::1]:54027 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDlh1-0005dx-34 for incoming@patchwork.ozlabs.org; Sat, 20 Oct 2018 03:29:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDlU3-0002W0-1b for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDlU0-0004k2-DH for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:38 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:40690) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gDlTy-0004Ux-4d for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:36 -0400 Received: from pova.uni-paderborn.de ([131.234.189.23] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 spheron) id 1gDlTg-00059Y-GX; Sat, 20 Oct 2018 09:15:16 +0200 Received: from mail.uni-paderborn.de by pova with queue id 2944831-2; Sat, 20 Oct 2018 07:15:16 GMT X-Envelope-From: Received: from aftr-95-222-26-83.unity-media.net ([95.222.26.83] helo=schnipp.lan) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89 telepax) id 1gDlTf-0008Eu-60; Sat, 20 Oct 2018 09:15:15 +0200 From: Bastian Koppelmann To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Sat, 20 Oct 2018 09:14:48 +0200 Message-Id: <20181020071451.27808-27-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 X-PMX-Version: 6.4.5.2775670, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.20.70616, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- v1 -> v2: - Add missing TARGET_RISCV64 conditions - trans_arith_w -> gen_arith_w target/riscv/insn_trans/trans_rvm.inc.c | 75 ++++--- target/riscv/translate.c | 268 +++++++++++------------- 2 files changed, 173 insertions(+), 170 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c index ffeae57a36..93859745b8 100644 --- a/target/riscv/insn_trans/trans_rvm.inc.c +++ b/target/riscv/insn_trans/trans_rvm.inc.c @@ -21,78 +21,105 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_mul_tl); } static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2); + TCGv source1 = tcg_temp_new(); + TCGv source2 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_muls2_tl(source2, source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); return true; } static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_mulhsu); } static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2); + TCGv source1 = tcg_temp_new(); + TCGv source2 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_mulu2_tl(source2, source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); return true; } static bool trans_div(DisasContext *ctx, arg_div *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_div); } static bool trans_divu(DisasContext *ctx, arg_divu *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_divu); } static bool trans_rem(DisasContext *ctx, arg_rem *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_rem); } static bool trans_remu(DisasContext *ctx, arg_remu *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_remu); } static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2); - return true; +#ifdef TARGET_RISCV64 + return trans_arith(ctx, a, &tcg_gen_mul_tl); +#else + return false; +#endif } static bool trans_divw(DisasContext *ctx, arg_divw *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2); - return true; +#ifdef TARGET_RISCV64 + return gen_arith_w(ctx, a, &gen_div); +#else + return false; +#endif } static bool trans_divuw(DisasContext *ctx, arg_divuw *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2); - return true; +#ifdef TARGET_RISCV64 + return gen_arith_w(ctx, a, &gen_divu); +#else + return false; +#endif } static bool trans_remw(DisasContext *ctx, arg_remw *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2); - return true; +#ifdef TARGET_RISCV64 + return gen_arith_w(ctx, a, &gen_rem); +#else + return false; +#endif } static bool trans_remuw(DisasContext *ctx, arg_remuw *a, uint32_t insn) { - gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2); - return true; +#ifdef TARGET_RISCV64 + return gen_arith_w(ctx, a, &gen_remu); +#else + return false; +#endif } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d85c21ee91..b542daf844 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -166,156 +166,110 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(rh); } -static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, - int rs2) +static void gen_div(TCGv ret, TCGv source1, TCGv source2) { - TCGv source1, source2, cond1, cond2, zeroreg, resultopt1; - source1 = tcg_temp_new(); - source2 = tcg_temp_new(); - gen_get_gpr(source1, rs1); - gen_get_gpr(source2, rs2); + TCGv cond1, cond2, zeroreg, resultopt1; + /* Handle by altering args to tcg_gen_div to produce req'd results: + * For overflow: want source1 in source1 and 1 in source2 + * For div by zero: want -1 in source1 and 1 in source2 -> -1 result */ + cond1 = tcg_temp_new(); + cond2 = tcg_temp_new(); + zeroreg = tcg_const_tl(0); + resultopt1 = tcg_temp_new(); + + tcg_gen_movi_tl(resultopt1, (target_ulong)-1); + tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, + ((target_ulong)1) << (TARGET_LONG_BITS - 1)); + tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ + tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ + /* if div by zero, set source1 to -1, otherwise don't change */ + tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, + resultopt1); + /* if overflow or div by zero, set source2 to 1, else don't change */ + tcg_gen_or_tl(cond1, cond1, cond2); + tcg_gen_movi_tl(resultopt1, (target_ulong)1); + tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, + resultopt1); + tcg_gen_div_tl(ret, source1, source2); + + tcg_temp_free(cond1); + tcg_temp_free(cond2); + tcg_temp_free(zeroreg); + tcg_temp_free(resultopt1); +} - switch (opc) { - CASE_OP_32_64(OPC_RISC_MUL): - tcg_gen_mul_tl(source1, source1, source2); - break; - case OPC_RISC_MULH: - tcg_gen_muls2_tl(source2, source1, source1, source2); - break; - case OPC_RISC_MULHSU: - gen_mulhsu(source1, source1, source2); - break; - case OPC_RISC_MULHU: - tcg_gen_mulu2_tl(source2, source1, source1, source2); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_DIVW: - tcg_gen_ext32s_tl(source1, source1); - tcg_gen_ext32s_tl(source2, source2); - /* fall through to DIV */ -#endif - case OPC_RISC_DIV: - /* Handle by altering args to tcg_gen_div to produce req'd results: - * For overflow: want source1 in source1 and 1 in source2 - * For div by zero: want -1 in source1 and 1 in source2 -> -1 result */ - cond1 = tcg_temp_new(); - cond2 = tcg_temp_new(); - zeroreg = tcg_const_tl(0); - resultopt1 = tcg_temp_new(); - - tcg_gen_movi_tl(resultopt1, (target_ulong)-1); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, - ((target_ulong)1) << (TARGET_LONG_BITS - 1)); - tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ - /* if div by zero, set source1 to -1, otherwise don't change */ - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, - resultopt1); - /* if overflow or div by zero, set source2 to 1, else don't change */ - tcg_gen_or_tl(cond1, cond1, cond2); - tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_div_tl(source1, source1, source2); - - tcg_temp_free(cond1); - tcg_temp_free(cond2); - tcg_temp_free(zeroreg); - tcg_temp_free(resultopt1); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_DIVUW: - tcg_gen_ext32u_tl(source1, source1); - tcg_gen_ext32u_tl(source2, source2); - /* fall through to DIVU */ -#endif - case OPC_RISC_DIVU: - cond1 = tcg_temp_new(); - zeroreg = tcg_const_tl(0); - resultopt1 = tcg_temp_new(); - - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); - tcg_gen_movi_tl(resultopt1, (target_ulong)-1); - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, - resultopt1); - tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_divu_tl(source1, source1, source2); - - tcg_temp_free(cond1); - tcg_temp_free(zeroreg); - tcg_temp_free(resultopt1); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_REMW: - tcg_gen_ext32s_tl(source1, source1); - tcg_gen_ext32s_tl(source2, source2); - /* fall through to REM */ -#endif - case OPC_RISC_REM: - cond1 = tcg_temp_new(); - cond2 = tcg_temp_new(); - zeroreg = tcg_const_tl(0); - resultopt1 = tcg_temp_new(); - - tcg_gen_movi_tl(resultopt1, 1L); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, - (target_ulong)1 << (TARGET_LONG_BITS - 1)); - tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ - /* if overflow or div by zero, set source2 to 1, else don't change */ - tcg_gen_or_tl(cond2, cond1, cond2); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, - resultopt1); - tcg_gen_rem_tl(resultopt1, source1, source2); - /* if div by zero, just return the original dividend */ - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt1, - source1); - - tcg_temp_free(cond1); - tcg_temp_free(cond2); - tcg_temp_free(zeroreg); - tcg_temp_free(resultopt1); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_REMUW: - tcg_gen_ext32u_tl(source1, source1); - tcg_gen_ext32u_tl(source2, source2); - /* fall through to REMU */ -#endif - case OPC_RISC_REMU: - cond1 = tcg_temp_new(); - zeroreg = tcg_const_tl(0); - resultopt1 = tcg_temp_new(); - - tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_remu_tl(resultopt1, source1, source2); - /* if div by zero, just return the original dividend */ - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt1, - source1); - - tcg_temp_free(cond1); - tcg_temp_free(zeroreg); - tcg_temp_free(resultopt1); - break; - default: - gen_exception_illegal(ctx); - return; - } +static void gen_divu(TCGv ret, TCGv source1, TCGv source2) +{ + TCGv cond1, zeroreg, resultopt1; + cond1 = tcg_temp_new(); + + zeroreg = tcg_const_tl(0); + resultopt1 = tcg_temp_new(); + + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); + tcg_gen_movi_tl(resultopt1, (target_ulong)-1); + tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, + resultopt1); + tcg_gen_movi_tl(resultopt1, (target_ulong)1); + tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, + resultopt1); + tcg_gen_divu_tl(ret, source1, source2); + + tcg_temp_free(cond1); + tcg_temp_free(zeroreg); + tcg_temp_free(resultopt1); +} - if (opc & 0x8) { /* sign extend for W instructions */ - tcg_gen_ext32s_tl(source1, source1); - } +static void gen_rem(TCGv ret, TCGv source1, TCGv source2) +{ + TCGv cond1, cond2, zeroreg, resultopt1; + + cond1 = tcg_temp_new(); + cond2 = tcg_temp_new(); + zeroreg = tcg_const_tl(0); + resultopt1 = tcg_temp_new(); + + tcg_gen_movi_tl(resultopt1, 1L); + tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, + (target_ulong)1 << (TARGET_LONG_BITS - 1)); + tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ + /* if overflow or div by zero, set source2 to 1, else don't change */ + tcg_gen_or_tl(cond2, cond1, cond2); + tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, + resultopt1); + tcg_gen_rem_tl(resultopt1, source1, source2); + /* if div by zero, just return the original dividend */ + tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, + source1); + + tcg_temp_free(cond1); + tcg_temp_free(cond2); + tcg_temp_free(zeroreg); + tcg_temp_free(resultopt1); +} - gen_set_gpr(rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); +static void gen_remu(TCGv ret, TCGv source1, TCGv source2) +{ + TCGv cond1, zeroreg, resultopt1; + cond1 = tcg_temp_new(); + zeroreg = tcg_const_tl(0); + resultopt1 = tcg_temp_new(); + + tcg_gen_movi_tl(resultopt1, (target_ulong)1); + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); + tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, + resultopt1); + tcg_gen_remu_tl(resultopt1, source1, source2); + /* if div by zero, just return the original dividend */ + tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, + source1); + + tcg_temp_free(cond1); + tcg_temp_free(zeroreg); + tcg_temp_free(resultopt1); } static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd, @@ -436,6 +390,28 @@ static bool trans_arith(DisasContext *ctx, arg_arith *a, return true; } +#ifdef TARGET_RISCV64 +static bool gen_arith_w(DisasContext *ctx, arg_arith *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1, source2; + source1 = tcg_temp_new(); + source2 = tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + tcg_gen_ext32s_tl(source1, source1); + tcg_gen_ext32s_tl(source2, source2); + + (*func)(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} +#endif + static bool gen_shift(DisasContext *ctx, arg_arith *a, void(*func)(TCGv, TCGv, TCGv)) {