[27/28] target/riscv: Remove decode_RV32_64G()

Message ID	20181012173047.25420-28-kbastian@mail.uni-paderborn.de
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de Date: Fri, 12 Oct 2018 19:30:46 +0200 Message-Id: <20181012173047.25420-28-kbastian@mail.uni-paderborn.de> In-Reply-To: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> References: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.12.172416, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 Subject: [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G() Precedence: list Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/riscv: Convert to decodetree \| expand [00/28] target/riscv: Convert to decodetree [01/28] targer/riscv: Activate decodetree and implemnt LUI & AUIPC [02/28] target/riscv: Convert RVXI branch insns to decodetree [03/28] target/riscv: Convert RVXI load/store insns to decodetree [04/28] target/riscv: Convert RVXI arithmetic insns to decodetree [05/28] target/riscv: Convert RVXI fence insns to decodetree [07/28] target/riscv: Convert RVXM insns to decodetree [08/28] target/riscv: Convert RV32A insns to decodetree [09/28] target/riscv: Convert RV64A insns to decodetree [10/28] target/riscv: Convert RV32F insns to decodetree [11/28] target/riscv: Convert RV64F insns to decodetree [12/28] target/riscv: Convert RV32D insns to decodetree [13/28] target/riscv: Convert RV64D insns to decodetree [14/28] target/riscv: Convert RV priv insns to decodetree [15/28] target/riscv: Convert quadrant 0 of RVXC insns to decodetree [16/28] target/riscv: Convert quadrant 1 of RVXC insns to decodetree [17/28] target/riscv: Convert quadrant 2 of RVXC insns to decodetree [18/28] target/riscv: Remove gen_jalr() [19/28] target/riscv: Replace gen_branch() with trans_branch() [20/28] target/riscv: Replace gen_load() with trans_load() [21/28] target/riscv: Replace gen_store() with trans_store() [22/28] target/riscv: Move gen_arith_imm() decoding into trans_* functions [23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists [24/28] target/riscv: Remove shift and slt insn manual decoding [25/28] target/riscv: Remove manual decoding of RV32/64M insn [26/28] target/riscv: Remove gen_system() [27/28] target/riscv: Remove decode_RV32_64G() [28/28] target/riscv: Replace gen_exception_illegal with return false

Message ID

20181012173047.25420-28-kbastian@mail.uni-paderborn.de

State

New

Headers

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu,
	kbastian@mail.uni-paderborn.de
Date: Fri, 12 Oct 2018 19:30:46 +0200
Message-Id: <20181012173047.25420-28-kbastian@mail.uni-paderborn.de>
In-Reply-To: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de>
References: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G()
Precedence: list
Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com,
	qemu-devel@nongnu.org
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

target/riscv: Convert to decodetree | expand

Commit Message

Bastian Koppelmann Oct. 12, 2018, 5:30 p.m. UTC

decodetree handles all instructions now so the fallback is not necessary
anymore.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
 target/riscv/translate.c | 23 -----------------------
 1 file changed, 23 deletions(-)

Comments

Richard Henderson Oct. 13, 2018, 8:01 p.m. UTC | #1

On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
>          if (!decode_insn32(ctx, ctx->opcode)) {
> -            /* fallback to old decoder */
> -            decode_RV32_64G(env, ctx);
>          }

Still need gen_exception_illegal.


r~

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 86ca885c7e..8ef943f6c8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -412,27 +412,6 @@  bool decode_insn16(DisasContext *ctx, uint16_t insn);
 #include "decode_insn16.inc.c"
 #include "insn_trans/trans_rvc.inc.c"
 
-static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
-{
-    int rs1, rd;
-    uint32_t op;
-
-    /* We do not do misaligned address check here: the address should never be
-     * misaligned at this point. Instructions that set PC must do the check,
-     * since epc must be the address of the instruction that caused us to
-     * perform the misaligned instruction fetch */
-
-    op = MASK_OP_MAJOR(ctx->opcode);
-    rs1 = GET_RS1(ctx->opcode);
-    rd = GET_RD(ctx->opcode);
-
-    switch (op) {
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-}
-
 static void decode_opc(CPURISCVState *env, DisasContext *ctx)
 {
     /* check for compressed insn */
@@ -448,8 +427,6 @@  static void decode_opc(CPURISCVState *env, DisasContext *ctx)
     } else {
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
         if (!decode_insn32(ctx, ctx->opcode)) {
-            /* fallback to old decoder */
-            decode_RV32_64G(env, ctx);
         }
     }
 }

[27/28] target/riscv: Remove decode_RV32_64G()

Commit Message

Comments

Patch