From patchwork Fri Oct 12 17:30:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 983243 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mail.uni-paderborn.de Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42WwNq1dL0z9s7W for ; Sat, 13 Oct 2018 04:50:51 +1100 (AEDT) Received: from localhost ([::1]:41995 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1aK-0008I3-RI for incoming@patchwork.ozlabs.org; Fri, 12 Oct 2018 13:50:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40099) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1Ht-000203-3m for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB1Hp-0000Ry-Uy for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:45 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:33844) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB1Hp-0000EJ-I6 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:41 -0400 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 hoth) id 1gB1Hc-000665-Q4; Fri, 12 Oct 2018 19:31:28 +0200 Received: from mail.uni-paderborn.de by wormulon with queue id 2934321-5; Fri, 12 Oct 2018 17:31:27 GMT X-Envelope-From: Received: from aftr-95-222-26-80.unity-media.net ([95.222.26.80] helo=schnipp.lan) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89 nylar) id 1gB1Hb-0006OT-P3; Fri, 12 Oct 2018 19:31:27 +0200 From: Bastian Koppelmann To: mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de Date: Fri, 12 Oct 2018 19:30:41 +0200 Message-Id: <20181012173047.25420-23-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> References: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 X-PMX-Version: 6.4.5.2775670, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.12.172416, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH 22/28] target/riscv: Move gen_arith_imm() decoding into trans_* functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvi.inc.c | 52 +++++++++---- target/riscv/translate.c | 99 +++++-------------------- 3 files changed, 60 insertions(+), 94 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7c71f8338b..806315b830 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -39,6 +39,7 @@ # Argument sets: &branch imm rs2 rs1 +&arith_imm imm rs1 rd &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd @@ -48,7 +49,7 @@ @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd -@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd +@i ............ ..... ... ..... ....... &arith_imm imm=%imm_i %rs1 %rd @b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1 @s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1 @u .................... ..... ....... imm=%imm_u %rd diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index b09c52a708..76d4baab69 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -235,37 +235,50 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a, uint32_t insn) static bool trans_addi(DisasContext *ctx, arg_addi *a, uint32_t insn) { - gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm); - return true; + return trans_arith_imm(ctx, a, &tcg_gen_add_tl); } static bool trans_slti(DisasContext *ctx, arg_slti *a, uint32_t insn) { - gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm); + TCGv source1; + source1 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + + tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); return true; } static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a, uint32_t insn) { - gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm); + TCGv source1; + source1 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + + tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); return true; } static bool trans_xori(DisasContext *ctx, arg_xori *a, uint32_t insn) { - gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm); - return true; + return trans_arith_imm(ctx, a, &tcg_gen_xor_tl); } + static bool trans_ori(DisasContext *ctx, arg_ori *a, uint32_t insn) { - gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm); - return true; + return trans_arith_imm(ctx, a, &tcg_gen_or_tl); } + static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn) { - gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm); - return true; + return trans_arith_imm(ctx, a, &tcg_gen_and_tl); } + static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn) { if (a->rd != 0) { @@ -370,13 +383,26 @@ static bool trans_and(DisasContext *ctx, arg_and *a, uint32_t insn) static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn) { - gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm); - return true; +#ifdef TARGET_RISCV64 + bool res = trans_arith_imm(ctx, a, &tcg_gen_add_tl); + tcg_gen_ext32s_tl(cpu_gpr[a->rd], cpu_gpr[a->rd]); + return res; +#else + return false; +#endif } static bool trans_slliw(DisasContext *ctx, arg_slliw *a, uint32_t insn) { - gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt); + TCGv source1; + source1 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + + tcg_gen_shli_tl(source1, source1, a->shamt); + tcg_gen_ext32s_tl(source1, source1); + gen_set_gpr(a->rd, source1); + + tcg_temp_free(source1); return true; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index feae31cb94..ed1d93af47 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -373,86 +373,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, tcg_temp_free(source2); } -static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd, - int rs1, target_long imm) -{ - TCGv source1 = tcg_temp_new(); - int shift_len = TARGET_LONG_BITS; - int shift_a; - - gen_get_gpr(source1, rs1); - - switch (opc) { - case OPC_RISC_ADDI: -#if defined(TARGET_RISCV64) - case OPC_RISC_ADDIW: -#endif - tcg_gen_addi_tl(source1, source1, imm); - break; - case OPC_RISC_SLTI: - tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, imm); - break; - case OPC_RISC_SLTIU: - tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, imm); - break; - case OPC_RISC_XORI: - tcg_gen_xori_tl(source1, source1, imm); - break; - case OPC_RISC_ORI: - tcg_gen_ori_tl(source1, source1, imm); - break; - case OPC_RISC_ANDI: - tcg_gen_andi_tl(source1, source1, imm); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_SLLIW: - shift_len = 32; - /* FALLTHRU */ -#endif - case OPC_RISC_SLLI: - if (imm >= shift_len) { - goto do_illegal; - } - tcg_gen_shli_tl(source1, source1, imm); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_SHIFT_RIGHT_IW: - shift_len = 32; - /* FALLTHRU */ -#endif - case OPC_RISC_SHIFT_RIGHT_I: - /* differentiate on IMM */ - shift_a = imm & 0x400; - imm &= 0x3ff; - if (imm >= shift_len) { - goto do_illegal; - } - if (imm != 0) { - if (shift_a) { - /* SRAI[W] */ - tcg_gen_sextract_tl(source1, source1, imm, shift_len - imm); - } else { - /* SRLI[W] */ - tcg_gen_extract_tl(source1, source1, imm, shift_len - imm); - } - /* No further sign-extension needed for W instructions. */ - opc &= ~0x8; - } - break; - default: - do_illegal: - gen_exception_illegal(ctx); - return; - } - - if (opc & 0x8) { /* sign-extend for W instructions */ - tcg_gen_ext32s_tl(source1, source1); - } - - gen_set_gpr(rd, source1); - tcg_temp_free(source1); -} - static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd, target_ulong imm) { @@ -534,6 +454,25 @@ static int64_t ex_rvc_register(int reg) bool decode_insn32(DisasContext *ctx, uint32_t insn); /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" + +static bool trans_arith_imm(DisasContext *ctx, arg_arith_imm *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1, source2; + source1 = tcg_temp_new(); + source2 = tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + tcg_gen_movi_tl(source2, a->imm); + + (*func)(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.inc.c" #include "insn_trans/trans_rvm.inc.c"