From patchwork Fri Oct 12 17:30:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 983228 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mail.uni-paderborn.de Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42Ww6x2N4Wz9s7T for ; Sat, 13 Oct 2018 04:38:49 +1100 (AEDT) Received: from localhost ([::1]:41917 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1Og-0006wk-Su for incoming@patchwork.ozlabs.org; Fri, 12 Oct 2018 13:38:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39893) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1Hj-0001rQ-5t for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB1Hh-0000IF-Nj for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:35 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:33836) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB1Hf-00006M-LZ for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:31 -0400 Received: from magmaria.uni-paderborn.de ([131.234.189.24] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 hoth) id 1gB1HS-00065b-Qs; Fri, 12 Oct 2018 19:31:18 +0200 Received: from mail.uni-paderborn.de by magmaria with queue id 2927548-3; Fri, 12 Oct 2018 17:31:18 GMT X-Envelope-From: Received: from aftr-95-222-26-80.unity-media.net ([95.222.26.80] helo=schnipp.lan) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89 nylar) id 1gB1HS-0006OT-Mv; Fri, 12 Oct 2018 19:31:18 +0200 From: Bastian Koppelmann To: mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de Date: Fri, 12 Oct 2018 19:30:38 +0200 Message-Id: <20181012173047.25420-20-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> References: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 X-PMX-Version: 6.4.5.2775670, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.12.172416, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The latter utilizes argument-sets of decodetree such that no manual decoding is necessary as in gen_branch(). Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.inc.c | 56 +++++++++++++++++-------- target/riscv/translate.c | 47 --------------------- 2 files changed, 38 insertions(+), 65 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 2668beb990..6097b82df4 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -73,42 +73,62 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a, uint32_t insn) return true; } -static bool trans_beq(DisasContext *ctx, arg_beq *a, uint32_t insn) +static bool trans_branch(DisasContext *ctx, arg_branch *a, TCGCond cond) { + TCGLabel *l = gen_new_label(); + TCGv source1, source2; + source1 = tcg_temp_new(); + source2 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_brcond_tl(cond, source1, source2, l); + gen_goto_tb(ctx, 1, ctx->pc_succ_insn); + gen_set_label(l); /* branch taken */ + CPURISCVState *env = current_cpu->env_ptr; - gen_branch(env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm); + if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { + /* misaligned */ + gen_exception_inst_addr_mis(ctx); + } else { + gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm); + } + ctx->base.is_jmp = DISAS_NORETURN; + + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; } + +static bool trans_beq(DisasContext *ctx, arg_beq *a, uint32_t insn) +{ + return trans_branch(ctx, a, TCG_COND_EQ); +} + static bool trans_bne(DisasContext *ctx, arg_bne *a, uint32_t insn) { - CPURISCVState *env = current_cpu->env_ptr; - gen_branch(env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm); - return true; + return trans_branch(ctx, a, TCG_COND_NE); } + static bool trans_blt(DisasContext *ctx, arg_blt *a, uint32_t insn) { - CPURISCVState *env = current_cpu->env_ptr; - gen_branch(env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm); - return true; + return trans_branch(ctx, a, TCG_COND_LT); } + static bool trans_bge(DisasContext *ctx, arg_bge *a, uint32_t insn) { - CPURISCVState *env = current_cpu->env_ptr; - gen_branch(env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm); - return true; + return trans_branch(ctx, a, TCG_COND_GE); } + static bool trans_bltu(DisasContext *ctx, arg_bltu *a, uint32_t insn) { - CPURISCVState *env = current_cpu->env_ptr; - gen_branch(env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm); - return true; + return trans_branch(ctx, a, TCG_COND_LTU); } + static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a, uint32_t insn) { - - CPURISCVState *env = current_cpu->env_ptr; - gen_branch(env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm); - return true; + return trans_branch(ctx, a, TCG_COND_GEU); } static bool trans_lb(DisasContext *ctx, arg_lb *a, uint32_t insn) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a0da694aa3..b8a9b1c64b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -488,53 +488,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd, ctx->base.is_jmp = DISAS_NORETURN; } -static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc, - int rs1, int rs2, target_long bimm) -{ - TCGLabel *l = gen_new_label(); - TCGv source1, source2; - source1 = tcg_temp_new(); - source2 = tcg_temp_new(); - gen_get_gpr(source1, rs1); - gen_get_gpr(source2, rs2); - - switch (opc) { - case OPC_RISC_BEQ: - tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l); - break; - case OPC_RISC_BNE: - tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l); - break; - case OPC_RISC_BLT: - tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l); - break; - case OPC_RISC_BGE: - tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l); - break; - case OPC_RISC_BLTU: - tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l); - break; - case OPC_RISC_BGEU: - tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l); - break; - default: - gen_exception_illegal(ctx); - return; - } - tcg_temp_free(source1); - tcg_temp_free(source2); - - gen_goto_tb(ctx, 1, ctx->pc_succ_insn); - gen_set_label(l); /* branch taken */ - if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) { - /* misaligned */ - gen_exception_inst_addr_mis(ctx); - } else { - gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm); - } - ctx->base.is_jmp = DISAS_NORETURN; -} - static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) {