From patchwork Tue Sep 25 13:41:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 974436 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42KN8B2Lhhz9s3Z for ; Wed, 26 Sep 2018 00:03:22 +1000 (AEST) Received: from localhost ([::1]:53263 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g4nvr-0007en-4S for incoming@patchwork.ozlabs.org; Tue, 25 Sep 2018 10:03:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40045) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g4ngf-0001S2-95 for qemu-devel@nongnu.org; Tue, 25 Sep 2018 09:47:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g4nbz-0005XC-Ig for qemu-devel@nongnu.org; Tue, 25 Sep 2018 09:42:48 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48608) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g4nbz-0003RA-80 for qemu-devel@nongnu.org; Tue, 25 Sep 2018 09:42:47 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1g4nbO-0001Bo-6F for qemu-devel@nongnu.org; Tue, 25 Sep 2018 14:42:10 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 25 Sep 2018 14:41:44 +0100 Message-Id: <20180925134144.21741-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180925134144.21741-1-peter.maydell@linaro.org> References: <20180925134144.21741-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 21/21] target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The ARMv8 architecture defines that an AArch32 CPU starts in SVC mode, unless EL2 is the highest available EL, in which case it starts in Hyp mode. (In ARMv7 a CPU with EL2 but not EL3 was not a valid configuration, but we don't specifically reject this if the user asks for one.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20180823135047.16525-1-peter.maydell@linaro.org --- target/arm/cpu.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 258ba6dcaad..b5e61cc1775 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -199,8 +199,18 @@ static void arm_cpu_reset(CPUState *s) env->cp15.c15_cpar = 1; } #else - /* SVC mode with interrupts disabled. */ - env->uncached_cpsr = ARM_CPU_MODE_SVC; + + /* + * If the highest available EL is EL2, AArch32 will start in Hyp + * mode; otherwise it starts in SVC. Note that if we start in + * AArch64 then these values in the uncached_cpsr will be ignored. + */ + if (arm_feature(env, ARM_FEATURE_EL2) && + !arm_feature(env, ARM_FEATURE_EL3)) { + env->uncached_cpsr = ARM_CPU_MODE_HYP; + } else { + env->uncached_cpsr = ARM_CPU_MODE_SVC; + } env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; if (arm_feature(env, ARM_FEATURE_M)) {