From patchwork Tue Sep 25 13:41:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 974439 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42KNHC4kqBz9s3Z for ; Wed, 26 Sep 2018 00:09:27 +1000 (AEST) Received: from localhost ([::1]:53303 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g4o1k-00054c-FQ for incoming@patchwork.ozlabs.org; Tue, 25 Sep 2018 10:09:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39971) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g4ngl-0001Mg-Ad for qemu-devel@nongnu.org; Tue, 25 Sep 2018 09:47:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g4nbI-0003cS-U1 for qemu-devel@nongnu.org; Tue, 25 Sep 2018 09:42:05 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48608) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g4nbI-0003RA-H6 for qemu-devel@nongnu.org; Tue, 25 Sep 2018 09:42:04 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1g4nbE-000193-M7 for qemu-devel@nongnu.org; Tue, 25 Sep 2018 14:42:00 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 25 Sep 2018 14:41:34 +0100 Message-Id: <20180925134144.21741-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180925134144.21741-1-peter.maydell@linaro.org> References: <20180925134144.21741-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/21] hw/arm/smmuv3: fix eventq recording and IRQ triggerring X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger The event queue management is broken today. Event records are not properly written as EVT_SET_* macro was not updating the actual event record. Also the event queue interrupt is not correctly triggered. Fixes: bb981004eaf4 ("hw/arm/smmuv3: Event queue recording helper") Signed-off-by: Eric Auger Message-id: 20180921070138.10114-3-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 26 +++++++++++++------------- hw/arm/smmuv3.c | 2 +- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index bab25d640eb..19540f8f411 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -442,17 +442,17 @@ typedef struct SMMUEventInfo { #define EVT_Q_OVERFLOW (1 << 31) -#define EVT_SET_TYPE(x, v) deposit32((x)->word[0], 0 , 8 , v) -#define EVT_SET_SSV(x, v) deposit32((x)->word[0], 11, 1 , v) -#define EVT_SET_SSID(x, v) deposit32((x)->word[0], 12, 20, v) -#define EVT_SET_SID(x, v) ((x)->word[1] = v) -#define EVT_SET_STAG(x, v) deposit32((x)->word[2], 0 , 16, v) -#define EVT_SET_STALL(x, v) deposit32((x)->word[2], 31, 1 , v) -#define EVT_SET_PNU(x, v) deposit32((x)->word[3], 1 , 1 , v) -#define EVT_SET_IND(x, v) deposit32((x)->word[3], 2 , 1 , v) -#define EVT_SET_RNW(x, v) deposit32((x)->word[3], 3 , 1 , v) -#define EVT_SET_S2(x, v) deposit32((x)->word[3], 7 , 1 , v) -#define EVT_SET_CLASS(x, v) deposit32((x)->word[3], 8 , 2 , v) +#define EVT_SET_TYPE(x, v) ((x)->word[0] = deposit32((x)->word[0], 0 , 8 , v)) +#define EVT_SET_SSV(x, v) ((x)->word[0] = deposit32((x)->word[0], 11, 1 , v)) +#define EVT_SET_SSID(x, v) ((x)->word[0] = deposit32((x)->word[0], 12, 20, v)) +#define EVT_SET_SID(x, v) ((x)->word[1] = v) +#define EVT_SET_STAG(x, v) ((x)->word[2] = deposit32((x)->word[2], 0 , 16, v)) +#define EVT_SET_STALL(x, v) ((x)->word[2] = deposit32((x)->word[2], 31, 1 , v)) +#define EVT_SET_PNU(x, v) ((x)->word[3] = deposit32((x)->word[3], 1 , 1 , v)) +#define EVT_SET_IND(x, v) ((x)->word[3] = deposit32((x)->word[3], 2 , 1 , v)) +#define EVT_SET_RNW(x, v) ((x)->word[3] = deposit32((x)->word[3], 3 , 1 , v)) +#define EVT_SET_S2(x, v) ((x)->word[3] = deposit32((x)->word[3], 7 , 1 , v)) +#define EVT_SET_CLASS(x, v) ((x)->word[3] = deposit32((x)->word[3], 8 , 2 , v)) #define EVT_SET_ADDR(x, addr) \ do { \ (x)->word[5] = (uint32_t)(addr >> 32); \ @@ -460,8 +460,8 @@ typedef struct SMMUEventInfo { } while (0) #define EVT_SET_ADDR2(x, addr) \ do { \ - deposit32((x)->word[7], 3, 29, addr >> 16); \ - deposit32((x)->word[7], 0, 16, addr & 0xffff);\ + (x)->word[7] = deposit32((x)->word[7], 3, 29, addr >> 16); \ + (x)->word[7] = deposit32((x)->word[7], 0, 16, addr & 0xffff);\ } while (0) void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index bb6a24e9b84..8c4e99fecc6 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -136,7 +136,7 @@ static MemTxResult smmuv3_write_eventq(SMMUv3State *s, Evt *evt) return r; } - if (smmuv3_q_empty(q)) { + if (!smmuv3_q_empty(q)) { smmuv3_trigger_irq(s, SMMU_IRQ_EVTQ, 0); } return MEMTX_OK;