From patchwork Fri Sep 21 16:19:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 973320 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42GzsP2LTwz9s8F for ; Sat, 22 Sep 2018 02:42:15 +1000 (AEST) Received: from localhost ([::1]:56518 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OVQ-0006ei-4d for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2018 12:42:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42981) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3OQm-0002a1-Ko for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:37:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3OBS-0004fK-5W for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:37 -0400 Received: from 10.mo178.mail-out.ovh.net ([46.105.76.150]:50672) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3OBR-0004eN-D9 for qemu-devel@nongnu.org; Fri, 21 Sep 2018 12:21:34 -0400 Received: from player799.ha.ovh.net (unknown [10.109.146.143]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 2E1E2332D4 for ; Fri, 21 Sep 2018 18:21:31 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id AE1FD5200B6; Fri, 21 Sep 2018 18:21:21 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2018 18:19:38 +0200 Message-Id: <20180921161939.822-11-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921161939.822-1-clg@kaod.org> References: <20180921161939.822-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1912340993998490432 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrledvgddutddvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.76.150 Subject: [Qemu-devel] [PATCH v2 10/11] aspeed/smc: inject errors in DMA checksum X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?b?Q8Op?= =?utf-8?q?dric_Le_Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Emulate read errors in the DMA Checksum Register for high frequencies and optimistic settings of the Read Timing Compensation Register. This will help in tuning the SPI timing calibration algorithm. The values below are those to expect from the first flash device of the FMC controller of a palmetto-bmc machine. Signed-off-by: Cédric Le Goater --- hw/ssi/aspeed_smc.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index db89c54dfc9f..01c3fd7b2666 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -751,6 +751,30 @@ static void aspeed_smc_dma_calibration(AspeedSMCState *s) s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); } +static bool aspeed_smc_inject_read_failure(AspeedSMCState *s) +{ + uint8_t delay = + (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; + uint8_t hclk_mask = + (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; + + /* + * Typical values of a palmetto-bmc machine. + */ + switch (aspeed_smc_hclk_divisor(hclk_mask)) { + case 4 ... 16: + return false; + case 3: /* at least one HCLK cycle delay */ + return (delay & 0x7) < 1; + case 2: /* at least two HCLK cycle delay */ + return (delay & 0x7) < 2; + case 1: /* (> 100MHz) is above the max freq of the controller */ + return true; + default: + g_assert_not_reached(); + } +} + /* * Accumulate the result of the reads to provide a checksum that will * be used to validate the read timing settings. @@ -788,6 +812,11 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) s->regs[R_DMA_FLASH_ADDR] += 4; s->regs[R_DMA_LEN] -= 4; } + + if (aspeed_smc_inject_read_failure(s)) { + s->regs[R_DMA_CHECKSUM] = 0xbadc0de; + } + } static void aspeed_smc_dma_rw(AspeedSMCState *s)