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[27/35] hw/sparc64: access cpu->interrupt_request with atomics

Message ID 20180917163103.6113-28-cota@braap.org
State New
Headers show
Series exec: drop BQL from interrupt handling | expand

Commit Message

Emilio Cota Sept. 17, 2018, 4:30 p.m. UTC 
From: Paolo Bonzini <pbonzini@redhat.com>

Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
 hw/sparc64/sparc64.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Philippe Mathieu-Daudé Sept. 19, 2018, 9:11 p.m. UTC | #1 
On 9/17/18 6:30 PM, Emilio G. Cota wrote:
> From: Paolo Bonzini <pbonzini@redhat.com>
> 
> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Cc: Artyom Tarasenko <atar4qemu@gmail.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Emilio G. Cota <cota@braap.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  hw/sparc64/sparc64.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
> index 408388945e..d7be7a2fb2 100644
> --- a/hw/sparc64/sparc64.c
> +++ b/hw/sparc64/sparc64.c
> @@ -56,7 +56,7 @@ void cpu_check_irqs(CPUSPARCState *env)
>      /* The bit corresponding to psrpil is (1<< psrpil), the next bit
>         is (2 << psrpil). */
>      if (pil < (2 << env->psrpil)) {
> -        if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
> +        if (atomic_read(&cs->interrupt_request) & CPU_INTERRUPT_HARD) {
>              trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
>              env->interrupt_index = 0;
>              cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
> @@ -87,7 +87,7 @@ void cpu_check_irqs(CPUSPARCState *env)
>                  break;
>              }
>          }
> -    } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
> +    } else if (atomic_read(&cs->interrupt_request) & CPU_INTERRUPT_HARD) {
>          trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
>                                                env->interrupt_index);
>          env->interrupt_index = 0;
>
diff mbox series

Patch

diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index 408388945e..d7be7a2fb2 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -56,7 +56,7 @@  void cpu_check_irqs(CPUSPARCState *env)
     /* The bit corresponding to psrpil is (1<< psrpil), the next bit
        is (2 << psrpil). */
     if (pil < (2 << env->psrpil)) {
-        if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
+        if (atomic_read(&cs->interrupt_request) & CPU_INTERRUPT_HARD) {
             trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
             env->interrupt_index = 0;
             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
@@ -87,7 +87,7 @@  void cpu_check_irqs(CPUSPARCState *env)
                 break;
             }
         }
-    } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
+    } else if (atomic_read(&cs->interrupt_request) & CPU_INTERRUPT_HARD) {
         trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
                                               env->interrupt_index);
         env->interrupt_index = 0;