From patchwork Mon Sep 17 16:30:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emilio Cota X-Patchwork-Id: 970682 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=braap.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=braap.org header.i=@braap.org header.b="T7Qdoz1Y"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="UtQ4iA0q"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42DWr071vdz9sfR for ; Tue, 18 Sep 2018 02:32:32 +1000 (AEST) Received: from localhost ([::1]:36437 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1wRq-0006d1-IW for incoming@patchwork.ozlabs.org; Mon, 17 Sep 2018 12:32:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40756) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1wQd-0006Er-5J for qemu-devel@nongnu.org; Mon, 17 Sep 2018 12:31:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g1wQZ-0001nM-2D for qemu-devel@nongnu.org; Mon, 17 Sep 2018 12:31:15 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:54581) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g1wQY-0001jV-RC for qemu-devel@nongnu.org; Mon, 17 Sep 2018 12:31:10 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2C4E221A02; Mon, 17 Sep 2018 12:31:09 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Mon, 17 Sep 2018 12:31:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=+fpC6XFI1T10Ax e3Y9ywrFE0ldzOnO5n9Atk7tj63U8=; b=T7Qdoz1Y17zFteNT+GS4sK3uXFTHOO e0VfZ5rFdnQGEX2gu1RqLzsSk4tSYw+1QC5CjyObKm1DKPi/cH8qOzKnZYuhyCOo NsgxEzI5qBoIqed3L4h/lk+wHGeSfsB++eZpcHhz5dhAIOY4nrJ8PVWNSZKp2YcW wr34kTVno8OlA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=+fpC6XFI1T10Axe3Y9ywrFE0ldzOnO5n9Atk7tj63U8=; b=UtQ4iA0q Ah4d97DXvckolWNsPShpMIcBXOl+jTmggOjkTdV/i0AbMEBf4P7cyKukxiFKeofn yzDlif2OE++rsw1fQyXx1zZ3pM7rAWje+UBvQcfRkCI0z5rIyhzhrmLamqyIb1FK 7gfvTVFDOD9k1I7dgygZuVsj2rGECRw3ESW68fArsIvod9pW/hWUOEtIWN0wC4/U mBOfBXzoX0zoQLKlDToTyMI6JsrxAcHCqC/CQWUE2uTCE7aRv8Jd0JirH/hQXcfx PZFVVtNAl61ywqW1NgcU9EngxxhAEsdaMwE06wbfipDcBiZy9+HaG4+zcuUmxmL5 Oa3GBq+fIV6IzA== X-ME-Proxy: X-ME-Sender: Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id AAD6BE4121; Mon, 17 Sep 2018 12:31:08 -0400 (EDT) From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2018 12:30:46 -0400 Message-Id: <20180917163103.6113-19-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917163103.6113-1-cota@braap.org> References: <20180917163103.6113-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH 18/35] target/mips: access cpu->interrupt_request with atomics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Aleksandar Markovic , Aurelien Jarno , James Hogan Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Paolo Bonzini Cc: Aurelien Jarno Cc: Aleksandar Markovic Cc: James Hogan Signed-off-by: Paolo Bonzini Signed-off-by: Emilio G. Cota --- target/mips/cpu.c | 7 ++++--- target/mips/kvm.c | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 497706b669..8d07696825 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -56,11 +56,12 @@ static bool mips_cpu_has_work(CPUState *cs) MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; bool has_work = false; + uint32_t interrupt_request = atomic_read(&cs->interrupt_request); /* Prior to MIPS Release 6 it is implementation dependent if non-enabled interrupts wake-up the CPU, however most of the implementations only check for interrupts that can be taken. */ - if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if ((interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { if (cpu_mips_hw_interrupts_enabled(env) || (env->insn_flags & ISA_MIPS32R6)) { @@ -72,7 +73,7 @@ static bool mips_cpu_has_work(CPUState *cs) if (env->CP0_Config3 & (1 << CP0C3_MT)) { /* The QEMU model will issue an _WAKE request whenever the CPUs should be woken up. */ - if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + if (interrupt_request & CPU_INTERRUPT_WAKE) { has_work = true; } @@ -82,7 +83,7 @@ static bool mips_cpu_has_work(CPUState *cs) } /* MIPS Release 6 has the ability to halt the CPU. */ if (env->CP0_Config5 & (1 << CP0C5_VP)) { - if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + if (interrupt_request & CPU_INTERRUPT_WAKE) { has_work = true; } if (!mips_vp_active(env)) { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 8e72850962..71fe3501a8 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -135,7 +135,7 @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) qemu_mutex_lock_iothread(); - if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if ((atomic_read(&cs->interrupt_request) & CPU_INTERRUPT_HARD) && cpu_mips_io_interrupts_pending(cpu)) { intr.cpu = -1; intr.irq = 2;