| Message ID | 20180917163103.6113-10-cota@braap.org |
|---|---|
| State | New |
| Headers | show |
| Series | exec: drop BQL from interrupt handling | expand |
On 9/17/18 6:30 PM, Emilio G. Cota wrote: > From: Paolo Bonzini <pbonzini@redhat.com> > > Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/cris/cpu.c | 3 ++- > target/cris/helper.c | 8 ++++---- > 2 files changed, 6 insertions(+), 5 deletions(-) > > diff --git a/target/cris/cpu.c b/target/cris/cpu.c > index a23aba2688..849e4718ba 100644 > --- a/target/cris/cpu.c > +++ b/target/cris/cpu.c > @@ -37,7 +37,8 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) > > static bool cris_cpu_has_work(CPUState *cs) > { > - return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); > + return atomic_read(&cs->interrupt_request) & (CPU_INTERRUPT_HARD | > + CPU_INTERRUPT_NMI); > } > > /* CPUClass::reset() */ > diff --git a/target/cris/helper.c b/target/cris/helper.c > index d2ec349191..15bad34d44 100644 > --- a/target/cris/helper.c > +++ b/target/cris/helper.c > @@ -116,8 +116,8 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, > if (r > 0) { > qemu_log_mask(CPU_LOG_MMU, > "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x" > - " pc=%x\n", __func__, r, cs->interrupt_request, address, > - res.phy, res.bf_vec, env->pc); > + " pc=%x\n", __func__, r, atomic_read(&cs->interrupt_request), > + address, res.phy, res.bf_vec, env->pc); > } > return r; > } > @@ -130,7 +130,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) > > D_LOG("exception index=%d interrupt_req=%d\n", > cs->exception_index, > - cs->interrupt_request); > + atomic_read(&cs->interrupt_request)); > > if (env->dslot) { > /* CRISv10 never takes interrupts while in a delay-slot. */ > @@ -192,7 +192,7 @@ void cris_cpu_do_interrupt(CPUState *cs) > > D_LOG("exception index=%d interrupt_req=%d\n", > cs->exception_index, > - cs->interrupt_request); > + atomic_read(&cs->interrupt_request)); > > switch (cs->exception_index) { > case EXCP_BREAK: >
diff --git a/target/cris/cpu.c b/target/cris/cpu.c index a23aba2688..849e4718ba 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -37,7 +37,8 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) static bool cris_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); + return atomic_read(&cs->interrupt_request) & (CPU_INTERRUPT_HARD | + CPU_INTERRUPT_NMI); } /* CPUClass::reset() */ diff --git a/target/cris/helper.c b/target/cris/helper.c index d2ec349191..15bad34d44 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -116,8 +116,8 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, if (r > 0) { qemu_log_mask(CPU_LOG_MMU, "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x" - " pc=%x\n", __func__, r, cs->interrupt_request, address, - res.phy, res.bf_vec, env->pc); + " pc=%x\n", __func__, r, atomic_read(&cs->interrupt_request), + address, res.phy, res.bf_vec, env->pc); } return r; } @@ -130,7 +130,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) D_LOG("exception index=%d interrupt_req=%d\n", cs->exception_index, - cs->interrupt_request); + atomic_read(&cs->interrupt_request)); if (env->dslot) { /* CRISv10 never takes interrupts while in a delay-slot. */ @@ -192,7 +192,7 @@ void cris_cpu_do_interrupt(CPUState *cs) D_LOG("exception index=%d interrupt_req=%d\n", cs->exception_index, - cs->interrupt_request); + atomic_read(&cs->interrupt_request)); switch (cs->exception_index) { case EXCP_BREAK: